Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8246082 |
1 |
|
|
T31 |
75820 |
|
T32 |
235 |
|
T19 |
42 |
| auto[1] |
5962312 |
1 |
|
|
T31 |
61083 |
|
T32 |
116 |
|
T19 |
16 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13440425 |
1 |
|
|
T31 |
128985 |
|
T32 |
343 |
|
T19 |
57 |
| auto[1] |
767969 |
1 |
|
|
T31 |
7918 |
|
T32 |
8 |
|
T19 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8187282 |
1 |
|
|
T31 |
76004 |
|
T32 |
158 |
|
T19 |
38 |
| auto[1] |
6021112 |
1 |
|
|
T31 |
60899 |
|
T32 |
193 |
|
T19 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2647528 |
1 |
|
|
T31 |
26387 |
|
T32 |
123 |
|
T19 |
11 |
| auto[1] |
auto[0] |
auto[1] |
386690 |
1 |
|
|
T31 |
3888 |
|
T32 |
6 |
|
T19 |
1 |
| auto[1] |
auto[1] |
auto[0] |
2605615 |
1 |
|
|
T31 |
26594 |
|
T32 |
62 |
|
T19 |
8 |
| auto[1] |
auto[1] |
auto[1] |
381279 |
1 |
|
|
T31 |
4030 |
|
T32 |
2 |
|
T22 |
114 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |