Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8161751 |
1 |
|
|
T31 |
73602 |
|
T32 |
118 |
|
T19 |
37 |
| auto[1] |
6046643 |
1 |
|
|
T31 |
63301 |
|
T32 |
233 |
|
T19 |
21 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13438391 |
1 |
|
|
T31 |
129046 |
|
T32 |
344 |
|
T19 |
58 |
| auto[1] |
770003 |
1 |
|
|
T31 |
7857 |
|
T32 |
7 |
|
T22 |
246 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8192929 |
1 |
|
|
T31 |
76734 |
|
T32 |
245 |
|
T19 |
45 |
| auto[1] |
6015465 |
1 |
|
|
T31 |
60169 |
|
T32 |
106 |
|
T19 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2634401 |
1 |
|
|
T31 |
26199 |
|
T32 |
28 |
|
T19 |
5 |
| auto[1] |
auto[0] |
auto[1] |
386592 |
1 |
|
|
T31 |
3958 |
|
T32 |
1 |
|
T22 |
105 |
| auto[1] |
auto[1] |
auto[0] |
2611061 |
1 |
|
|
T31 |
26113 |
|
T32 |
71 |
|
T19 |
8 |
| auto[1] |
auto[1] |
auto[1] |
383411 |
1 |
|
|
T31 |
3899 |
|
T32 |
6 |
|
T22 |
141 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |