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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.97


Total test records in report: 943
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T769 /workspace/coverage/cover_reg_top/49.gpio_intr_test.314808284 Jul 20 04:44:28 PM PDT 24 Jul 20 04:44:30 PM PDT 24 15543351 ps
T770 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.134054407 Jul 20 04:44:15 PM PDT 24 Jul 20 04:44:21 PM PDT 24 42326468 ps
T771 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3824012409 Jul 20 04:44:13 PM PDT 24 Jul 20 04:44:14 PM PDT 24 48027092 ps
T772 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3817991514 Jul 20 04:43:52 PM PDT 24 Jul 20 04:43:55 PM PDT 24 45671795 ps
T100 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3980807671 Jul 20 04:44:16 PM PDT 24 Jul 20 04:44:19 PM PDT 24 66009727 ps
T773 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2931630714 Jul 20 04:44:24 PM PDT 24 Jul 20 04:44:26 PM PDT 24 15463942 ps
T774 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1601247246 Jul 20 04:44:30 PM PDT 24 Jul 20 04:44:33 PM PDT 24 18427269 ps
T86 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1160635150 Jul 20 04:43:46 PM PDT 24 Jul 20 04:43:48 PM PDT 24 31232906 ps
T101 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.657843015 Jul 20 04:44:05 PM PDT 24 Jul 20 04:44:07 PM PDT 24 21114800 ps
T775 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.716529294 Jul 20 04:43:53 PM PDT 24 Jul 20 04:43:55 PM PDT 24 46776550 ps
T102 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2136242213 Jul 20 04:44:14 PM PDT 24 Jul 20 04:44:18 PM PDT 24 23760967 ps
T776 /workspace/coverage/cover_reg_top/16.gpio_intr_test.3963103246 Jul 20 04:44:16 PM PDT 24 Jul 20 04:44:19 PM PDT 24 33205492 ps
T777 /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.541259944 Jul 20 04:44:16 PM PDT 24 Jul 20 04:44:19 PM PDT 24 20236697 ps
T778 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2738124255 Jul 20 04:43:47 PM PDT 24 Jul 20 04:43:50 PM PDT 24 296021353 ps
T87 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3795356066 Jul 20 04:43:54 PM PDT 24 Jul 20 04:43:56 PM PDT 24 14380130 ps
T103 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3422972030 Jul 20 04:43:51 PM PDT 24 Jul 20 04:43:53 PM PDT 24 123495979 ps
T779 /workspace/coverage/cover_reg_top/43.gpio_intr_test.4085359187 Jul 20 04:44:24 PM PDT 24 Jul 20 04:44:26 PM PDT 24 34944829 ps
T780 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3395607508 Jul 20 04:44:24 PM PDT 24 Jul 20 04:44:26 PM PDT 24 43472055 ps
T104 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.329447538 Jul 20 04:44:05 PM PDT 24 Jul 20 04:44:08 PM PDT 24 61827108 ps
T781 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.4134474360 Jul 20 04:43:55 PM PDT 24 Jul 20 04:43:58 PM PDT 24 86668566 ps
T782 /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3164957374 Jul 20 04:43:49 PM PDT 24 Jul 20 04:43:54 PM PDT 24 326341943 ps
T783 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2535262237 Jul 20 04:43:49 PM PDT 24 Jul 20 04:43:53 PM PDT 24 90115931 ps
T784 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.365466237 Jul 20 04:44:14 PM PDT 24 Jul 20 04:44:19 PM PDT 24 405910082 ps
T88 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.191359030 Jul 20 04:44:00 PM PDT 24 Jul 20 04:44:04 PM PDT 24 315813225 ps
T785 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3111533922 Jul 20 04:44:13 PM PDT 24 Jul 20 04:44:14 PM PDT 24 88647934 ps
T786 /workspace/coverage/cover_reg_top/6.gpio_intr_test.1185625892 Jul 20 04:44:05 PM PDT 24 Jul 20 04:44:07 PM PDT 24 23005572 ps
T787 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.151908041 Jul 20 04:44:13 PM PDT 24 Jul 20 04:44:16 PM PDT 24 24230628 ps
T788 /workspace/coverage/cover_reg_top/19.gpio_intr_test.1897755452 Jul 20 04:44:21 PM PDT 24 Jul 20 04:44:23 PM PDT 24 23622041 ps
T789 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1805745005 Jul 20 04:44:04 PM PDT 24 Jul 20 04:44:05 PM PDT 24 45719182 ps
T790 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1542725032 Jul 20 04:44:07 PM PDT 24 Jul 20 04:44:10 PM PDT 24 155448644 ps
T791 /workspace/coverage/cover_reg_top/2.gpio_intr_test.2885102089 Jul 20 04:43:48 PM PDT 24 Jul 20 04:43:50 PM PDT 24 44483309 ps
T89 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.531926697 Jul 20 04:43:48 PM PDT 24 Jul 20 04:43:50 PM PDT 24 16137508 ps
T792 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3958546383 Jul 20 04:44:14 PM PDT 24 Jul 20 04:44:16 PM PDT 24 18166659 ps
T793 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2219759729 Jul 20 04:44:23 PM PDT 24 Jul 20 04:44:25 PM PDT 24 35466400 ps
T794 /workspace/coverage/cover_reg_top/24.gpio_intr_test.3465216971 Jul 20 04:44:22 PM PDT 24 Jul 20 04:44:23 PM PDT 24 49324425 ps
T795 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.847430649 Jul 20 04:44:03 PM PDT 24 Jul 20 04:44:05 PM PDT 24 119024720 ps
T796 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2220928128 Jul 20 04:43:51 PM PDT 24 Jul 20 04:43:53 PM PDT 24 34071645 ps
T797 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.15710560 Jul 20 04:43:59 PM PDT 24 Jul 20 04:44:02 PM PDT 24 73000544 ps
T798 /workspace/coverage/cover_reg_top/42.gpio_intr_test.2483548853 Jul 20 04:44:21 PM PDT 24 Jul 20 04:44:23 PM PDT 24 16857583 ps
T90 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1609582196 Jul 20 04:43:57 PM PDT 24 Jul 20 04:43:59 PM PDT 24 12978805 ps
T799 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2153924739 Jul 20 04:44:13 PM PDT 24 Jul 20 04:44:17 PM PDT 24 286126854 ps
T800 /workspace/coverage/cover_reg_top/37.gpio_intr_test.3072333404 Jul 20 04:44:22 PM PDT 24 Jul 20 04:44:24 PM PDT 24 32836523 ps
T51 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.434149360 Jul 20 04:44:16 PM PDT 24 Jul 20 04:44:19 PM PDT 24 171481772 ps
T801 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3233344111 Jul 20 04:43:47 PM PDT 24 Jul 20 04:43:51 PM PDT 24 408869576 ps
T802 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2261337995 Jul 20 04:44:00 PM PDT 24 Jul 20 04:44:02 PM PDT 24 29006946 ps
T803 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2444189223 Jul 20 04:44:06 PM PDT 24 Jul 20 04:44:09 PM PDT 24 94360195 ps
T91 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3449666721 Jul 20 04:43:58 PM PDT 24 Jul 20 04:44:00 PM PDT 24 122493150 ps
T92 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2535922244 Jul 20 04:43:48 PM PDT 24 Jul 20 04:43:50 PM PDT 24 16124691 ps
T93 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1188132130 Jul 20 04:44:21 PM PDT 24 Jul 20 04:44:23 PM PDT 24 43968312 ps
T804 /workspace/coverage/cover_reg_top/3.gpio_intr_test.2974302651 Jul 20 04:43:55 PM PDT 24 Jul 20 04:43:58 PM PDT 24 23093156 ps
T805 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3859051118 Jul 20 04:44:13 PM PDT 24 Jul 20 04:44:15 PM PDT 24 28354362 ps
T806 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3021451961 Jul 20 04:43:59 PM PDT 24 Jul 20 04:44:02 PM PDT 24 151366791 ps
T807 /workspace/coverage/cover_reg_top/46.gpio_intr_test.407736574 Jul 20 04:44:24 PM PDT 24 Jul 20 04:44:26 PM PDT 24 12691948 ps
T94 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.4284603161 Jul 20 04:43:52 PM PDT 24 Jul 20 04:43:55 PM PDT 24 122006357 ps
T808 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2980363776 Jul 20 04:44:13 PM PDT 24 Jul 20 04:44:16 PM PDT 24 56851891 ps
T809 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2837921266 Jul 20 04:44:14 PM PDT 24 Jul 20 04:44:18 PM PDT 24 23625761 ps
T810 /workspace/coverage/cover_reg_top/35.gpio_intr_test.1225276036 Jul 20 04:44:24 PM PDT 24 Jul 20 04:44:26 PM PDT 24 44867922 ps
T811 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2302867278 Jul 20 04:44:15 PM PDT 24 Jul 20 04:44:18 PM PDT 24 23322898 ps
T812 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3514101337 Jul 20 04:43:52 PM PDT 24 Jul 20 04:43:54 PM PDT 24 50281390 ps
T813 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.21441256 Jul 20 04:44:15 PM PDT 24 Jul 20 04:44:19 PM PDT 24 242251640 ps
T814 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2090123267 Jul 20 04:44:23 PM PDT 24 Jul 20 04:44:25 PM PDT 24 24135616 ps
T815 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1202840419 Jul 20 04:44:05 PM PDT 24 Jul 20 04:44:07 PM PDT 24 40977251 ps
T816 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.207082782 Jul 20 04:43:55 PM PDT 24 Jul 20 04:44:00 PM PDT 24 159231238 ps
T817 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1299207266 Jul 20 04:43:48 PM PDT 24 Jul 20 04:43:50 PM PDT 24 63374230 ps
T818 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3630939478 Jul 20 04:43:52 PM PDT 24 Jul 20 04:43:56 PM PDT 24 278995267 ps
T49 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.98539875 Jul 20 04:43:46 PM PDT 24 Jul 20 04:43:49 PM PDT 24 1025957867 ps
T819 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2205771236 Jul 20 04:44:11 PM PDT 24 Jul 20 04:44:14 PM PDT 24 40414426 ps
T820 /workspace/coverage/cover_reg_top/29.gpio_intr_test.539465348 Jul 20 04:44:25 PM PDT 24 Jul 20 04:44:27 PM PDT 24 19315802 ps
T821 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4167387779 Jul 20 04:43:55 PM PDT 24 Jul 20 04:43:58 PM PDT 24 94996191 ps
T822 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1208523144 Jul 20 04:44:14 PM PDT 24 Jul 20 04:44:16 PM PDT 24 30065570 ps
T823 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2085972070 Jul 20 04:44:12 PM PDT 24 Jul 20 04:44:14 PM PDT 24 239682244 ps
T824 /workspace/coverage/cover_reg_top/4.gpio_intr_test.2935043852 Jul 20 04:43:55 PM PDT 24 Jul 20 04:43:58 PM PDT 24 13000901 ps
T825 /workspace/coverage/cover_reg_top/39.gpio_intr_test.3548005750 Jul 20 04:44:23 PM PDT 24 Jul 20 04:44:25 PM PDT 24 16719439 ps
T826 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.914156447 Jul 20 04:44:14 PM PDT 24 Jul 20 04:44:17 PM PDT 24 15787728 ps
T827 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.846956415 Jul 20 04:44:04 PM PDT 24 Jul 20 04:44:05 PM PDT 24 72378600 ps
T828 /workspace/coverage/cover_reg_top/22.gpio_intr_test.4056287005 Jul 20 04:44:20 PM PDT 24 Jul 20 04:44:22 PM PDT 24 17308991 ps
T829 /workspace/coverage/cover_reg_top/10.gpio_intr_test.205339749 Jul 20 04:44:15 PM PDT 24 Jul 20 04:44:19 PM PDT 24 53775147 ps
T830 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3460894546 Jul 20 04:44:05 PM PDT 24 Jul 20 04:44:07 PM PDT 24 94480454 ps
T831 /workspace/coverage/cover_reg_top/17.gpio_intr_test.2892626218 Jul 20 04:44:21 PM PDT 24 Jul 20 04:44:22 PM PDT 24 53440185 ps
T832 /workspace/coverage/cover_reg_top/12.gpio_intr_test.4021422665 Jul 20 04:44:15 PM PDT 24 Jul 20 04:44:18 PM PDT 24 23366872 ps
T833 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1686631340 Jul 20 04:44:23 PM PDT 24 Jul 20 04:44:27 PM PDT 24 498743862 ps
T834 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3545818222 Jul 20 04:43:57 PM PDT 24 Jul 20 04:43:59 PM PDT 24 61286712 ps
T835 /workspace/coverage/cover_reg_top/0.gpio_intr_test.3849583497 Jul 20 04:43:48 PM PDT 24 Jul 20 04:43:50 PM PDT 24 39583270 ps
T836 /workspace/coverage/cover_reg_top/47.gpio_intr_test.2549325338 Jul 20 04:44:24 PM PDT 24 Jul 20 04:44:26 PM PDT 24 23939858 ps
T837 /workspace/coverage/cover_reg_top/7.gpio_intr_test.1615895922 Jul 20 04:44:05 PM PDT 24 Jul 20 04:44:07 PM PDT 24 45505872 ps
T95 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.807584081 Jul 20 04:43:56 PM PDT 24 Jul 20 04:43:59 PM PDT 24 53965528 ps
T838 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1798967372 Jul 20 04:44:22 PM PDT 24 Jul 20 04:44:23 PM PDT 24 11554730 ps
T839 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3832294857 Jul 20 04:44:15 PM PDT 24 Jul 20 04:44:19 PM PDT 24 38222791 ps
T840 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2543521149 Jul 20 04:43:59 PM PDT 24 Jul 20 04:44:01 PM PDT 24 177551891 ps
T841 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1459107914 Jul 20 04:44:15 PM PDT 24 Jul 20 04:44:21 PM PDT 24 750975129 ps
T842 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.4183451574 Jul 20 04:44:12 PM PDT 24 Jul 20 04:44:14 PM PDT 24 32240863 ps
T96 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1408978406 Jul 20 04:43:46 PM PDT 24 Jul 20 04:43:48 PM PDT 24 41431204 ps
T843 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3141044707 Jul 20 04:44:21 PM PDT 24 Jul 20 04:44:23 PM PDT 24 143534027 ps
T844 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.233104028 Jul 20 04:33:32 PM PDT 24 Jul 20 04:33:42 PM PDT 24 65870513 ps
T845 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1758539075 Jul 20 04:33:38 PM PDT 24 Jul 20 04:33:46 PM PDT 24 35059323 ps
T846 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2811635829 Jul 20 04:33:31 PM PDT 24 Jul 20 04:33:41 PM PDT 24 39292528 ps
T847 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4122168205 Jul 20 04:33:34 PM PDT 24 Jul 20 04:33:43 PM PDT 24 108067014 ps
T848 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3926305299 Jul 20 04:33:25 PM PDT 24 Jul 20 04:33:33 PM PDT 24 78721729 ps
T849 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3887629689 Jul 20 04:33:26 PM PDT 24 Jul 20 04:33:34 PM PDT 24 368989564 ps
T850 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2122773840 Jul 20 04:33:35 PM PDT 24 Jul 20 04:33:45 PM PDT 24 34518469 ps
T851 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.369420319 Jul 20 04:34:20 PM PDT 24 Jul 20 04:34:22 PM PDT 24 163132764 ps
T852 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3547703568 Jul 20 04:33:33 PM PDT 24 Jul 20 04:33:42 PM PDT 24 108229551 ps
T853 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4222751143 Jul 20 04:33:29 PM PDT 24 Jul 20 04:33:38 PM PDT 24 373581957 ps
T854 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4153202431 Jul 20 04:33:30 PM PDT 24 Jul 20 04:33:40 PM PDT 24 115251242 ps
T855 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.551479551 Jul 20 04:33:40 PM PDT 24 Jul 20 04:33:48 PM PDT 24 207180705 ps
T856 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3357991266 Jul 20 04:33:20 PM PDT 24 Jul 20 04:33:27 PM PDT 24 52602312 ps
T857 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3725792522 Jul 20 04:33:29 PM PDT 24 Jul 20 04:33:38 PM PDT 24 91137011 ps
T858 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.763302857 Jul 20 04:33:30 PM PDT 24 Jul 20 04:33:39 PM PDT 24 145726332 ps
T859 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1740026931 Jul 20 04:34:34 PM PDT 24 Jul 20 04:34:39 PM PDT 24 262846361 ps
T860 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.324745925 Jul 20 04:33:26 PM PDT 24 Jul 20 04:33:35 PM PDT 24 359442286 ps
T861 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1544997206 Jul 20 04:33:33 PM PDT 24 Jul 20 04:33:43 PM PDT 24 43541150 ps
T862 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2563577987 Jul 20 04:33:24 PM PDT 24 Jul 20 04:33:33 PM PDT 24 68457096 ps
T863 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3664712551 Jul 20 04:33:30 PM PDT 24 Jul 20 04:33:39 PM PDT 24 72041697 ps
T864 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.415303101 Jul 20 04:33:42 PM PDT 24 Jul 20 04:33:49 PM PDT 24 255623013 ps
T865 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3849466787 Jul 20 04:34:46 PM PDT 24 Jul 20 04:34:48 PM PDT 24 177350874 ps
T866 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1930774199 Jul 20 04:33:33 PM PDT 24 Jul 20 04:33:43 PM PDT 24 50459784 ps
T867 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.747410970 Jul 20 04:33:35 PM PDT 24 Jul 20 04:33:45 PM PDT 24 41882014 ps
T868 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3209960695 Jul 20 04:33:31 PM PDT 24 Jul 20 04:33:40 PM PDT 24 26724163 ps
T869 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3300027764 Jul 20 04:33:30 PM PDT 24 Jul 20 04:33:39 PM PDT 24 108569373 ps
T870 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2671992067 Jul 20 04:33:28 PM PDT 24 Jul 20 04:33:37 PM PDT 24 89684065 ps
T871 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4284243645 Jul 20 04:33:29 PM PDT 24 Jul 20 04:33:38 PM PDT 24 203776686 ps
T872 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.805693341 Jul 20 04:34:21 PM PDT 24 Jul 20 04:34:23 PM PDT 24 152677894 ps
T873 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1815396912 Jul 20 04:33:25 PM PDT 24 Jul 20 04:33:33 PM PDT 24 44343326 ps
T874 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1229373764 Jul 20 04:33:33 PM PDT 24 Jul 20 04:33:42 PM PDT 24 49235364 ps
T875 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2376626595 Jul 20 04:33:29 PM PDT 24 Jul 20 04:33:38 PM PDT 24 177279432 ps
T876 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.614012242 Jul 20 04:33:42 PM PDT 24 Jul 20 04:33:49 PM PDT 24 311031440 ps
T877 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1156456724 Jul 20 04:33:37 PM PDT 24 Jul 20 04:33:46 PM PDT 24 294935437 ps
T878 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1524916804 Jul 20 04:33:35 PM PDT 24 Jul 20 04:33:45 PM PDT 24 31937113 ps
T879 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.156020483 Jul 20 04:33:31 PM PDT 24 Jul 20 04:33:40 PM PDT 24 218070743 ps
T880 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3671203635 Jul 20 04:33:37 PM PDT 24 Jul 20 04:33:47 PM PDT 24 277300891 ps
T881 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2049188139 Jul 20 04:34:46 PM PDT 24 Jul 20 04:34:48 PM PDT 24 305975757 ps
T882 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3086032241 Jul 20 04:33:38 PM PDT 24 Jul 20 04:33:47 PM PDT 24 36489131 ps
T883 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.441226378 Jul 20 04:33:41 PM PDT 24 Jul 20 04:33:49 PM PDT 24 152715783 ps
T884 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4282044906 Jul 20 04:33:38 PM PDT 24 Jul 20 04:33:47 PM PDT 24 381612821 ps
T885 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.115752620 Jul 20 04:33:37 PM PDT 24 Jul 20 04:33:47 PM PDT 24 54271717 ps
T886 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.791261739 Jul 20 04:33:30 PM PDT 24 Jul 20 04:33:39 PM PDT 24 134197936 ps
T887 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3524950348 Jul 20 04:34:21 PM PDT 24 Jul 20 04:34:22 PM PDT 24 57158462 ps
T888 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1795093768 Jul 20 04:33:31 PM PDT 24 Jul 20 04:33:40 PM PDT 24 132606251 ps
T889 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.120254528 Jul 20 04:33:31 PM PDT 24 Jul 20 04:33:40 PM PDT 24 47735280 ps
T890 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1509245050 Jul 20 04:33:30 PM PDT 24 Jul 20 04:33:40 PM PDT 24 70499635 ps
T891 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.14776387 Jul 20 04:33:35 PM PDT 24 Jul 20 04:33:45 PM PDT 24 91644502 ps
T892 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.592342769 Jul 20 04:33:29 PM PDT 24 Jul 20 04:33:38 PM PDT 24 62723148 ps
T893 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.827212953 Jul 20 04:33:29 PM PDT 24 Jul 20 04:33:38 PM PDT 24 69989228 ps
T894 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1504913373 Jul 20 04:33:41 PM PDT 24 Jul 20 04:33:49 PM PDT 24 33454871 ps
T895 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.832730226 Jul 20 04:33:29 PM PDT 24 Jul 20 04:33:38 PM PDT 24 38205166 ps
T896 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.130086944 Jul 20 04:33:27 PM PDT 24 Jul 20 04:33:35 PM PDT 24 56436005 ps
T897 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3225982341 Jul 20 04:33:43 PM PDT 24 Jul 20 04:33:49 PM PDT 24 29035408 ps
T898 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1995291777 Jul 20 04:33:41 PM PDT 24 Jul 20 04:33:48 PM PDT 24 83578392 ps
T899 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2788896740 Jul 20 04:33:38 PM PDT 24 Jul 20 04:33:47 PM PDT 24 83667288 ps
T900 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3573554614 Jul 20 04:33:38 PM PDT 24 Jul 20 04:33:47 PM PDT 24 49924321 ps
T901 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.976736206 Jul 20 04:33:25 PM PDT 24 Jul 20 04:33:33 PM PDT 24 62466067 ps
T902 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.530085956 Jul 20 04:33:41 PM PDT 24 Jul 20 04:33:49 PM PDT 24 154030839 ps
T903 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2223488471 Jul 20 04:33:36 PM PDT 24 Jul 20 04:33:45 PM PDT 24 113778359 ps
T904 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1654434057 Jul 20 04:33:37 PM PDT 24 Jul 20 04:33:47 PM PDT 24 61673329 ps
T905 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1747781764 Jul 20 04:33:18 PM PDT 24 Jul 20 04:33:25 PM PDT 24 23515817 ps
T906 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2152145309 Jul 20 04:33:26 PM PDT 24 Jul 20 04:33:35 PM PDT 24 100892038 ps
T907 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.930538825 Jul 20 04:34:21 PM PDT 24 Jul 20 04:34:23 PM PDT 24 306605725 ps
T908 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3876352349 Jul 20 04:33:30 PM PDT 24 Jul 20 04:33:40 PM PDT 24 244708346 ps
T909 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.666495033 Jul 20 04:33:33 PM PDT 24 Jul 20 04:33:43 PM PDT 24 176161313 ps
T910 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3779043167 Jul 20 04:33:33 PM PDT 24 Jul 20 04:33:47 PM PDT 24 142252847 ps
T911 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.723324316 Jul 20 04:33:24 PM PDT 24 Jul 20 04:33:32 PM PDT 24 138290585 ps
T912 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.4136543006 Jul 20 04:33:31 PM PDT 24 Jul 20 04:33:40 PM PDT 24 127604990 ps
T913 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1986637616 Jul 20 04:33:39 PM PDT 24 Jul 20 04:33:47 PM PDT 24 43920551 ps
T914 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1140464711 Jul 20 04:33:35 PM PDT 24 Jul 20 04:33:45 PM PDT 24 188378064 ps
T915 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2051945288 Jul 20 04:34:34 PM PDT 24 Jul 20 04:34:39 PM PDT 24 62158250 ps
T916 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1972121532 Jul 20 04:33:30 PM PDT 24 Jul 20 04:33:40 PM PDT 24 52428601 ps
T917 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3880780995 Jul 20 04:33:24 PM PDT 24 Jul 20 04:33:32 PM PDT 24 123059486 ps
T918 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1279954548 Jul 20 04:33:32 PM PDT 24 Jul 20 04:33:42 PM PDT 24 526559649 ps
T919 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.271623863 Jul 20 04:33:32 PM PDT 24 Jul 20 04:33:41 PM PDT 24 1246099775 ps
T920 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.473985374 Jul 20 04:33:40 PM PDT 24 Jul 20 04:33:48 PM PDT 24 349247826 ps
T921 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4118609223 Jul 20 04:33:27 PM PDT 24 Jul 20 04:33:36 PM PDT 24 53763591 ps
T922 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1049464749 Jul 20 04:33:33 PM PDT 24 Jul 20 04:33:43 PM PDT 24 93335043 ps
T923 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.194467913 Jul 20 04:33:29 PM PDT 24 Jul 20 04:33:38 PM PDT 24 128883601 ps
T924 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3664097488 Jul 20 04:33:25 PM PDT 24 Jul 20 04:33:33 PM PDT 24 184533305 ps
T925 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2770314138 Jul 20 04:33:38 PM PDT 24 Jul 20 04:33:47 PM PDT 24 481202664 ps
T926 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3921398888 Jul 20 04:33:32 PM PDT 24 Jul 20 04:33:42 PM PDT 24 62364779 ps
T927 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1042590706 Jul 20 04:33:29 PM PDT 24 Jul 20 04:33:38 PM PDT 24 187579587 ps
T928 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3279010937 Jul 20 04:33:33 PM PDT 24 Jul 20 04:33:43 PM PDT 24 41702964 ps
T929 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2233743936 Jul 20 04:33:32 PM PDT 24 Jul 20 04:33:46 PM PDT 24 209660915 ps
T930 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.224080483 Jul 20 04:34:47 PM PDT 24 Jul 20 04:34:48 PM PDT 24 34594305 ps
T931 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3193643948 Jul 20 04:33:30 PM PDT 24 Jul 20 04:33:39 PM PDT 24 34183883 ps
T932 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3114197555 Jul 20 04:33:27 PM PDT 24 Jul 20 04:33:36 PM PDT 24 97333613 ps
T933 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.289794973 Jul 20 04:33:37 PM PDT 24 Jul 20 04:33:46 PM PDT 24 53552321 ps
T934 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.693275002 Jul 20 04:33:30 PM PDT 24 Jul 20 04:33:39 PM PDT 24 231129446 ps
T935 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.840827652 Jul 20 04:34:34 PM PDT 24 Jul 20 04:34:39 PM PDT 24 221910967 ps
T936 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1941540944 Jul 20 04:33:34 PM PDT 24 Jul 20 04:33:43 PM PDT 24 170722953 ps
T937 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3225609330 Jul 20 04:33:39 PM PDT 24 Jul 20 04:33:47 PM PDT 24 47504923 ps
T938 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3597313675 Jul 20 04:33:29 PM PDT 24 Jul 20 04:33:38 PM PDT 24 130545393 ps
T939 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.501619189 Jul 20 04:33:26 PM PDT 24 Jul 20 04:33:34 PM PDT 24 36639457 ps
T940 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3428760626 Jul 20 04:33:36 PM PDT 24 Jul 20 04:33:46 PM PDT 24 40819691 ps
T941 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2647899656 Jul 20 04:33:29 PM PDT 24 Jul 20 04:33:38 PM PDT 24 427700539 ps
T942 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1815077446 Jul 20 04:34:34 PM PDT 24 Jul 20 04:34:39 PM PDT 24 34396122 ps
T943 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.567083468 Jul 20 04:33:20 PM PDT 24 Jul 20 04:33:28 PM PDT 24 971541713 ps

Test location /workspace/coverage/default/31.gpio_stress_all.568290510
Short name T31
Test name
Test status
Simulation time 59385931693 ps
CPU time 211.97 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:39:08 PM PDT 24
Peak memory 191892 kb
Host smart-1996ca3b-2420-4f0c-b8fe-9b10ae32e34a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568290510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.568290510
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.902756272
Short name T70
Test name
Test status
Simulation time 72508589 ps
CPU time 2.73 seconds
Started Jul 20 04:35:25 PM PDT 24
Finished Jul 20 04:35:31 PM PDT 24
Peak memory 198160 kb
Host smart-0da2a27e-f679-4179-b8f3-e69e5f6c5111
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902756272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 33.gpio_intr_with_filter_rand_intr_event.902756272
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.4189182963
Short name T27
Test name
Test status
Simulation time 42164306595 ps
CPU time 1077.18 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:53:33 PM PDT 24
Peak memory 198360 kb
Host smart-fda81f23-cfc8-46e0-8c62-48c8e35a6b6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4189182963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.4189182963
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3018646720
Short name T11
Test name
Test status
Simulation time 564316925 ps
CPU time 17.34 seconds
Started Jul 20 04:36:09 PM PDT 24
Finished Jul 20 04:36:28 PM PDT 24
Peak memory 198160 kb
Host smart-298efd08-3e14-4336-992f-4da3f305cfe4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018646720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3018646720
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2461987169
Short name T38
Test name
Test status
Simulation time 604708992 ps
CPU time 0.9 seconds
Started Jul 20 04:33:56 PM PDT 24
Finished Jul 20 04:33:57 PM PDT 24
Peak memory 214232 kb
Host smart-7ba8fb62-e54a-4230-a827-8ae29ef6b29f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461987169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2461987169
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2119861303
Short name T83
Test name
Test status
Simulation time 17069297 ps
CPU time 0.75 seconds
Started Jul 20 04:43:52 PM PDT 24
Finished Jul 20 04:43:55 PM PDT 24
Peak memory 196780 kb
Host smart-7c8698d3-70ec-4868-8aa3-a4445101c234
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119861303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2119861303
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.4039886808
Short name T3
Test name
Test status
Simulation time 1437689385 ps
CPU time 1.96 seconds
Started Jul 20 04:33:42 PM PDT 24
Finished Jul 20 04:33:50 PM PDT 24
Peak memory 197764 kb
Host smart-cb5912c5-22a0-4757-afab-63925020db00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039886808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.4039886808
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.4022090968
Short name T47
Test name
Test status
Simulation time 123306229 ps
CPU time 1.43 seconds
Started Jul 20 04:44:13 PM PDT 24
Finished Jul 20 04:44:15 PM PDT 24
Peak memory 198260 kb
Host smart-f32110ce-3772-4614-8d42-c14286d85e3b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022090968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.4022090968
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/13.gpio_alert_test.825490170
Short name T198
Test name
Test status
Simulation time 56824132 ps
CPU time 0.58 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:35 PM PDT 24
Peak memory 194560 kb
Host smart-a9dc4c07-3b18-457d-9b2a-242533451ed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825490170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.825490170
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.3422972030
Short name T103
Test name
Test status
Simulation time 123495979 ps
CPU time 0.78 seconds
Started Jul 20 04:43:51 PM PDT 24
Finished Jul 20 04:43:53 PM PDT 24
Peak memory 196364 kb
Host smart-58d0cedd-3443-4ae8-980f-a220790d2ef1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422972030 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.3422972030
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2652303331
Short name T78
Test name
Test status
Simulation time 84640444 ps
CPU time 2.97 seconds
Started Jul 20 04:43:57 PM PDT 24
Finished Jul 20 04:44:01 PM PDT 24
Peak memory 198128 kb
Host smart-015a50d5-93aa-4989-b719-f03ed91c98a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652303331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2652303331
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.98539875
Short name T49
Test name
Test status
Simulation time 1025957867 ps
CPU time 1.27 seconds
Started Jul 20 04:43:46 PM PDT 24
Finished Jul 20 04:43:49 PM PDT 24
Peak memory 198244 kb
Host smart-1d42e3be-a5fa-4006-ab0c-819ed6e22ad2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98539875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UV
M_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_tl_intg_err.98539875
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.4284603161
Short name T94
Test name
Test status
Simulation time 122006357 ps
CPU time 0.9 seconds
Started Jul 20 04:43:52 PM PDT 24
Finished Jul 20 04:43:55 PM PDT 24
Peak memory 196672 kb
Host smart-cd3ca4be-6aae-4ea2-a7e3-510d05ed6a98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284603161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.4284603161
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3233344111
Short name T801
Test name
Test status
Simulation time 408869576 ps
CPU time 2.28 seconds
Started Jul 20 04:43:47 PM PDT 24
Finished Jul 20 04:43:51 PM PDT 24
Peak memory 198300 kb
Host smart-d543f3df-c330-4f21-80eb-285413a0f4a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233344111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3233344111
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.2535922244
Short name T92
Test name
Test status
Simulation time 16124691 ps
CPU time 0.64 seconds
Started Jul 20 04:43:48 PM PDT 24
Finished Jul 20 04:43:50 PM PDT 24
Peak memory 195336 kb
Host smart-3d0bd812-669c-43e0-bb8c-7229d742b3dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535922244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.2535922244
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.716529294
Short name T775
Test name
Test status
Simulation time 46776550 ps
CPU time 0.65 seconds
Started Jul 20 04:43:53 PM PDT 24
Finished Jul 20 04:43:55 PM PDT 24
Peak memory 197172 kb
Host smart-28914ebd-59ef-4942-91ed-bf88e0a8c7cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716529294 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.716529294
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.531926697
Short name T89
Test name
Test status
Simulation time 16137508 ps
CPU time 0.61 seconds
Started Jul 20 04:43:48 PM PDT 24
Finished Jul 20 04:43:50 PM PDT 24
Peak memory 194640 kb
Host smart-085d0ae4-d5bc-4e5d-8648-d967b1f23925
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531926697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.531926697
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.3849583497
Short name T835
Test name
Test status
Simulation time 39583270 ps
CPU time 0.6 seconds
Started Jul 20 04:43:48 PM PDT 24
Finished Jul 20 04:43:50 PM PDT 24
Peak memory 193916 kb
Host smart-3fa0ebc7-4b37-41a9-904c-74452719bd1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849583497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.3849583497
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.2738124255
Short name T778
Test name
Test status
Simulation time 296021353 ps
CPU time 1.82 seconds
Started Jul 20 04:43:47 PM PDT 24
Finished Jul 20 04:43:50 PM PDT 24
Peak memory 198304 kb
Host smart-5de518eb-21a2-4808-89c0-e94d3f5a4bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738124255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.2738124255
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1408978406
Short name T96
Test name
Test status
Simulation time 41431204 ps
CPU time 0.63 seconds
Started Jul 20 04:43:46 PM PDT 24
Finished Jul 20 04:43:48 PM PDT 24
Peak memory 194724 kb
Host smart-bc2f5a74-02ee-448a-88eb-58bf6747d447
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408978406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1408978406
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.3163327282
Short name T732
Test name
Test status
Simulation time 28365761 ps
CPU time 1.38 seconds
Started Jul 20 04:43:51 PM PDT 24
Finished Jul 20 04:43:53 PM PDT 24
Peak memory 198356 kb
Host smart-501f4019-490c-4e10-9ee2-862f461f9148
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163327282 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.3163327282
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1160635150
Short name T86
Test name
Test status
Simulation time 31232906 ps
CPU time 0.57 seconds
Started Jul 20 04:43:46 PM PDT 24
Finished Jul 20 04:43:48 PM PDT 24
Peak memory 193456 kb
Host smart-3eda1910-2b56-4da7-affe-8c5cec1dd2ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160635150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1160635150
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3817991514
Short name T772
Test name
Test status
Simulation time 45671795 ps
CPU time 0.6 seconds
Started Jul 20 04:43:52 PM PDT 24
Finished Jul 20 04:43:55 PM PDT 24
Peak memory 194648 kb
Host smart-1d92a0c2-d1e4-49be-8b14-67a9ae59914b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817991514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3817991514
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.1488266695
Short name T98
Test name
Test status
Simulation time 43252088 ps
CPU time 0.69 seconds
Started Jul 20 04:43:51 PM PDT 24
Finished Jul 20 04:43:53 PM PDT 24
Peak memory 196444 kb
Host smart-9f15f19b-f0e2-4d15-8f45-b47c73b3307f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488266695 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.1488266695
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.2535262237
Short name T783
Test name
Test status
Simulation time 90115931 ps
CPU time 2.14 seconds
Started Jul 20 04:43:49 PM PDT 24
Finished Jul 20 04:43:53 PM PDT 24
Peak memory 198296 kb
Host smart-5a12b549-5c87-4f00-90a7-3b9861f1bef4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535262237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.2535262237
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2160375762
Short name T44
Test name
Test status
Simulation time 270471065 ps
CPU time 1.13 seconds
Started Jul 20 04:43:56 PM PDT 24
Finished Jul 20 04:43:59 PM PDT 24
Peak memory 198264 kb
Host smart-c78e5458-27de-413b-9813-61e228dfd103
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2160375762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2160375762
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.2326900950
Short name T725
Test name
Test status
Simulation time 40991232 ps
CPU time 1.64 seconds
Started Jul 20 04:44:12 PM PDT 24
Finished Jul 20 04:44:14 PM PDT 24
Peak memory 198356 kb
Host smart-e39daf6d-2de4-4ed6-b5f1-82049c61b317
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326900950 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.2326900950
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.740515218
Short name T81
Test name
Test status
Simulation time 44159320 ps
CPU time 0.62 seconds
Started Jul 20 04:44:13 PM PDT 24
Finished Jul 20 04:44:14 PM PDT 24
Peak memory 195032 kb
Host smart-4365679b-2552-4540-8926-b43dc010e937
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740515218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio
_csr_rw.740515218
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.205339749
Short name T829
Test name
Test status
Simulation time 53775147 ps
CPU time 0.67 seconds
Started Jul 20 04:44:15 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 194684 kb
Host smart-f51b48fb-440f-4800-9999-88b86c20c83b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205339749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.205339749
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3832294857
Short name T839
Test name
Test status
Simulation time 38222791 ps
CPU time 0.87 seconds
Started Jul 20 04:44:15 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 198036 kb
Host smart-a6fad1d2-0e97-480b-9b78-341530b456e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832294857 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3832294857
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.496397376
Short name T726
Test name
Test status
Simulation time 132076823 ps
CPU time 1.81 seconds
Started Jul 20 04:44:16 PM PDT 24
Finished Jul 20 04:44:21 PM PDT 24
Peak memory 198432 kb
Host smart-2345484e-7a4d-4642-9768-9bff4b53d4bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496397376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.496397376
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2918073937
Short name T740
Test name
Test status
Simulation time 41339857 ps
CPU time 0.84 seconds
Started Jul 20 04:44:13 PM PDT 24
Finished Jul 20 04:44:16 PM PDT 24
Peak memory 197296 kb
Host smart-259f9b88-0a1d-4fbe-8d90-2f959ecd61c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918073937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2918073937
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.914156447
Short name T826
Test name
Test status
Simulation time 15787728 ps
CPU time 0.79 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:17 PM PDT 24
Peak memory 198136 kb
Host smart-e84f5515-99d2-4228-8b96-ce1c44a31bad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914156447 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.914156447
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1934824769
Short name T79
Test name
Test status
Simulation time 13480974 ps
CPU time 0.63 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:17 PM PDT 24
Peak memory 194964 kb
Host smart-eaa0c60a-452b-4759-8cd8-05346c106899
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934824769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1934824769
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3615774537
Short name T753
Test name
Test status
Simulation time 29227883 ps
CPU time 0.58 seconds
Started Jul 20 04:44:13 PM PDT 24
Finished Jul 20 04:44:15 PM PDT 24
Peak memory 193876 kb
Host smart-0115d0cd-1e6a-4b55-a21e-5c3f54739ca1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615774537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3615774537
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2980363776
Short name T808
Test name
Test status
Simulation time 56851891 ps
CPU time 0.82 seconds
Started Jul 20 04:44:13 PM PDT 24
Finished Jul 20 04:44:16 PM PDT 24
Peak memory 198076 kb
Host smart-bceabe03-f828-4225-9a63-53716980ad3b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980363776 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2980363776
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.134054407
Short name T770
Test name
Test status
Simulation time 42326468 ps
CPU time 2.1 seconds
Started Jul 20 04:44:15 PM PDT 24
Finished Jul 20 04:44:21 PM PDT 24
Peak memory 197884 kb
Host smart-ea99e3ea-c55f-40df-8821-35854bcc4d60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134054407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.134054407
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.920568952
Short name T37
Test name
Test status
Simulation time 160014387 ps
CPU time 0.91 seconds
Started Jul 20 04:44:16 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 197664 kb
Host smart-fa44af82-b616-4d08-9216-f05164e5bed0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920568952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.920568952
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2804759650
Short name T729
Test name
Test status
Simulation time 19132646 ps
CPU time 0.78 seconds
Started Jul 20 04:44:16 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 198128 kb
Host smart-fdb1f79e-d190-4a70-a067-4531dafe3976
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804759650 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2804759650
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2961654996
Short name T762
Test name
Test status
Simulation time 16423957 ps
CPU time 0.66 seconds
Started Jul 20 04:44:16 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 195896 kb
Host smart-6dd0b408-e679-4222-9fcc-c51b70b55bee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961654996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2961654996
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.4021422665
Short name T832
Test name
Test status
Simulation time 23366872 ps
CPU time 0.61 seconds
Started Jul 20 04:44:15 PM PDT 24
Finished Jul 20 04:44:18 PM PDT 24
Peak memory 194000 kb
Host smart-f480eb60-cce4-4853-8761-12e18c3b34a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021422665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.4021422665
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2837921266
Short name T809
Test name
Test status
Simulation time 23625761 ps
CPU time 0.78 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:18 PM PDT 24
Peak memory 196168 kb
Host smart-fc7249d4-dafe-4189-b4e2-ab2912206d8d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837921266 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2837921266
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.1459107914
Short name T841
Test name
Test status
Simulation time 750975129 ps
CPU time 2.96 seconds
Started Jul 20 04:44:15 PM PDT 24
Finished Jul 20 04:44:21 PM PDT 24
Peak memory 198248 kb
Host smart-e8217411-b9b0-48cb-a8cc-94c0645264ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459107914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.1459107914
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3111533922
Short name T785
Test name
Test status
Simulation time 88647934 ps
CPU time 0.91 seconds
Started Jul 20 04:44:13 PM PDT 24
Finished Jul 20 04:44:14 PM PDT 24
Peak memory 198136 kb
Host smart-69e70986-f35d-4cd8-83e9-6321967497cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111533922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3111533922
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.229293774
Short name T738
Test name
Test status
Simulation time 29693271 ps
CPU time 0.73 seconds
Started Jul 20 04:44:15 PM PDT 24
Finished Jul 20 04:44:18 PM PDT 24
Peak memory 198012 kb
Host smart-e077f668-d50d-440c-9ea3-99536f860288
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229293774 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.229293774
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3822143889
Short name T743
Test name
Test status
Simulation time 50877131 ps
CPU time 0.59 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:17 PM PDT 24
Peak memory 195000 kb
Host smart-97b4395d-d883-408a-9ef0-e452a826a0be
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822143889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3822143889
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2630867067
Short name T752
Test name
Test status
Simulation time 11422829 ps
CPU time 0.65 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:17 PM PDT 24
Peak memory 194652 kb
Host smart-55cb9aa0-7ce9-47f2-aa7d-6811b7e263f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630867067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2630867067
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3980807671
Short name T100
Test name
Test status
Simulation time 66009727 ps
CPU time 0.74 seconds
Started Jul 20 04:44:16 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 197228 kb
Host smart-be7662bc-ebab-4198-8be7-65a94c278628
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980807671 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3980807671
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.2153924739
Short name T799
Test name
Test status
Simulation time 286126854 ps
CPU time 2.44 seconds
Started Jul 20 04:44:13 PM PDT 24
Finished Jul 20 04:44:17 PM PDT 24
Peak memory 198364 kb
Host smart-b89f4e7f-ca75-4f2c-949e-646709b2312f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153924739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.2153924739
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.4183451574
Short name T842
Test name
Test status
Simulation time 32240863 ps
CPU time 0.82 seconds
Started Jul 20 04:44:12 PM PDT 24
Finished Jul 20 04:44:14 PM PDT 24
Peak memory 198060 kb
Host smart-47f2f20b-690a-4e9c-acae-d8c21b487b96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183451574 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.4183451574
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.4253503714
Short name T749
Test name
Test status
Simulation time 63014171 ps
CPU time 0.57 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:17 PM PDT 24
Peak memory 194896 kb
Host smart-2af1cd1b-1599-40cc-8912-34d88445cb95
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253503714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.4253503714
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.352795710
Short name T758
Test name
Test status
Simulation time 11972266 ps
CPU time 0.6 seconds
Started Jul 20 04:44:15 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 193900 kb
Host smart-f2d5bf0a-fcf1-4068-b7ea-ea9da010247d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352795710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.352795710
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2485344745
Short name T97
Test name
Test status
Simulation time 18123955 ps
CPU time 0.88 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:17 PM PDT 24
Peak memory 197244 kb
Host smart-baf2322d-e268-4285-b204-c3484662431f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485344745 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2485344745
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.743838228
Short name T733
Test name
Test status
Simulation time 354185157 ps
CPU time 1.96 seconds
Started Jul 20 04:44:15 PM PDT 24
Finished Jul 20 04:44:20 PM PDT 24
Peak memory 198252 kb
Host smart-1aebde5d-40eb-4f27-9eb1-29e895ad3dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743838228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.743838228
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1453120399
Short name T745
Test name
Test status
Simulation time 160368005 ps
CPU time 0.94 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:17 PM PDT 24
Peak memory 198048 kb
Host smart-b21f3323-b017-4c8f-a0e9-2956907dc254
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453120399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1453120399
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.541259944
Short name T777
Test name
Test status
Simulation time 20236697 ps
CPU time 0.65 seconds
Started Jul 20 04:44:16 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 197080 kb
Host smart-9ec69552-dafa-4bd4-808f-bb65f8de8b34
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541259944 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.541259944
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.321260291
Short name T80
Test name
Test status
Simulation time 14663311 ps
CPU time 0.64 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:16 PM PDT 24
Peak memory 195092 kb
Host smart-fa66da7b-368a-4efe-be80-2f62e209d6b8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321260291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.321260291
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3824012409
Short name T771
Test name
Test status
Simulation time 48027092 ps
CPU time 0.62 seconds
Started Jul 20 04:44:13 PM PDT 24
Finished Jul 20 04:44:14 PM PDT 24
Peak memory 193940 kb
Host smart-5064c6ac-03b9-4876-a3a9-3e850ee200d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824012409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3824012409
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.3859051118
Short name T805
Test name
Test status
Simulation time 28354362 ps
CPU time 0.77 seconds
Started Jul 20 04:44:13 PM PDT 24
Finished Jul 20 04:44:15 PM PDT 24
Peak memory 197052 kb
Host smart-d6615faa-de35-4454-86f5-1024cf973ca0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859051118 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.3859051118
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.365466237
Short name T784
Test name
Test status
Simulation time 405910082 ps
CPU time 2.12 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 198232 kb
Host smart-967c1256-c3bc-45e8-89a8-10ebe1a51e57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365466237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.365466237
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.517953470
Short name T45
Test name
Test status
Simulation time 188435321 ps
CPU time 0.88 seconds
Started Jul 20 04:44:16 PM PDT 24
Finished Jul 20 04:44:20 PM PDT 24
Peak memory 198008 kb
Host smart-cec23e45-2aa7-4a9f-bcd8-94cf6cc6954e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517953470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 15.gpio_tl_intg_err.517953470
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.21441256
Short name T813
Test name
Test status
Simulation time 242251640 ps
CPU time 0.79 seconds
Started Jul 20 04:44:15 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 198360 kb
Host smart-d28d8ae2-65f7-4e6a-b160-38b295ead509
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21441256 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.21441256
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.151908041
Short name T787
Test name
Test status
Simulation time 24230628 ps
CPU time 0.57 seconds
Started Jul 20 04:44:13 PM PDT 24
Finished Jul 20 04:44:16 PM PDT 24
Peak memory 195056 kb
Host smart-fef79cef-db8a-4247-b965-47ae3c6e031b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151908041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.151908041
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3963103246
Short name T776
Test name
Test status
Simulation time 33205492 ps
CPU time 0.57 seconds
Started Jul 20 04:44:16 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 193872 kb
Host smart-97793063-7372-4d95-a65d-9a571155993d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963103246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3963103246
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2136242213
Short name T102
Test name
Test status
Simulation time 23760967 ps
CPU time 0.65 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:18 PM PDT 24
Peak memory 194716 kb
Host smart-2ed95fac-1920-47ae-9d1c-182829a8fbb4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136242213 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2136242213
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.357540249
Short name T760
Test name
Test status
Simulation time 259965925 ps
CPU time 2.48 seconds
Started Jul 20 04:44:13 PM PDT 24
Finished Jul 20 04:44:18 PM PDT 24
Peak memory 198248 kb
Host smart-d27e5aa0-3be0-4e12-9c0c-d5cd6405564a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357540249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.357540249
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.142125846
Short name T767
Test name
Test status
Simulation time 64856217 ps
CPU time 0.83 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:17 PM PDT 24
Peak memory 197480 kb
Host smart-0f3a158d-a0d7-4276-9669-50bed68dc106
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142125846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.142125846
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2302867278
Short name T811
Test name
Test status
Simulation time 23322898 ps
CPU time 0.78 seconds
Started Jul 20 04:44:15 PM PDT 24
Finished Jul 20 04:44:18 PM PDT 24
Peak memory 198092 kb
Host smart-c77ff0f1-b23e-400c-a75c-fb8679658e39
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302867278 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2302867278
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3845788356
Short name T117
Test name
Test status
Simulation time 27445765 ps
CPU time 0.62 seconds
Started Jul 20 04:44:15 PM PDT 24
Finished Jul 20 04:44:18 PM PDT 24
Peak memory 193508 kb
Host smart-3bdf0f92-a7c3-4a92-b663-250397b5dedc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845788356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3845788356
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2892626218
Short name T831
Test name
Test status
Simulation time 53440185 ps
CPU time 0.57 seconds
Started Jul 20 04:44:21 PM PDT 24
Finished Jul 20 04:44:22 PM PDT 24
Peak memory 193928 kb
Host smart-01c23836-28fb-4459-b3f8-42f61c1f6bca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892626218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2892626218
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3958546383
Short name T792
Test name
Test status
Simulation time 18166659 ps
CPU time 0.7 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:16 PM PDT 24
Peak memory 194864 kb
Host smart-9bec6407-1eac-47d7-af6c-3dd9b62210ca
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958546383 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3958546383
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2085972070
Short name T823
Test name
Test status
Simulation time 239682244 ps
CPU time 1.42 seconds
Started Jul 20 04:44:12 PM PDT 24
Finished Jul 20 04:44:14 PM PDT 24
Peak memory 198172 kb
Host smart-1fa7d507-271f-4100-9253-63c7dacbae30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085972070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2085972070
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.3064713567
Short name T764
Test name
Test status
Simulation time 180185118 ps
CPU time 0.82 seconds
Started Jul 20 04:44:13 PM PDT 24
Finished Jul 20 04:44:16 PM PDT 24
Peak memory 197108 kb
Host smart-4e9eeb85-ba88-45ac-883b-c8bbf9412296
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064713567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.3064713567
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.3968032388
Short name T739
Test name
Test status
Simulation time 128596640 ps
CPU time 1.64 seconds
Started Jul 20 04:44:23 PM PDT 24
Finished Jul 20 04:44:26 PM PDT 24
Peak memory 198412 kb
Host smart-f5f60430-e8f1-40f4-a0f8-1d7c209e1bea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968032388 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.3968032388
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.1188132130
Short name T93
Test name
Test status
Simulation time 43968312 ps
CPU time 0.6 seconds
Started Jul 20 04:44:21 PM PDT 24
Finished Jul 20 04:44:23 PM PDT 24
Peak memory 195144 kb
Host smart-410c8b6c-0c40-46b5-b65f-54fd17033a97
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188132130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.1188132130
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.925573550
Short name T746
Test name
Test status
Simulation time 13526925 ps
CPU time 0.57 seconds
Started Jul 20 04:44:20 PM PDT 24
Finished Jul 20 04:44:21 PM PDT 24
Peak memory 194604 kb
Host smart-7baf5f89-aaed-4004-9af7-6682d9ec4d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925573550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.925573550
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2219759729
Short name T793
Test name
Test status
Simulation time 35466400 ps
CPU time 0.82 seconds
Started Jul 20 04:44:23 PM PDT 24
Finished Jul 20 04:44:25 PM PDT 24
Peak memory 197092 kb
Host smart-5375ba6c-eee5-493f-b923-8a5645d3c95a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219759729 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2219759729
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3141044707
Short name T843
Test name
Test status
Simulation time 143534027 ps
CPU time 1.93 seconds
Started Jul 20 04:44:21 PM PDT 24
Finished Jul 20 04:44:23 PM PDT 24
Peak memory 198228 kb
Host smart-e1e3ad15-14a4-40a6-9b6b-ae5eb911bf0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141044707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3141044707
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.457712619
Short name T119
Test name
Test status
Simulation time 45819727 ps
CPU time 0.91 seconds
Started Jul 20 04:44:23 PM PDT 24
Finished Jul 20 04:44:26 PM PDT 24
Peak memory 198020 kb
Host smart-bb05dc71-500d-4662-81fe-f9f79316eae3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457712619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 18.gpio_tl_intg_err.457712619
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.544038081
Short name T724
Test name
Test status
Simulation time 25190642 ps
CPU time 0.73 seconds
Started Jul 20 04:44:23 PM PDT 24
Finished Jul 20 04:44:25 PM PDT 24
Peak memory 198132 kb
Host smart-58c03c27-8943-4236-bbd1-a3dae9b9e99a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544038081 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.544038081
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1282667521
Short name T118
Test name
Test status
Simulation time 34425684 ps
CPU time 0.58 seconds
Started Jul 20 04:44:27 PM PDT 24
Finished Jul 20 04:44:28 PM PDT 24
Peak memory 193512 kb
Host smart-a363d724-cd7f-462d-a959-2497e86f75dd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282667521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1282667521
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.1897755452
Short name T788
Test name
Test status
Simulation time 23622041 ps
CPU time 0.59 seconds
Started Jul 20 04:44:21 PM PDT 24
Finished Jul 20 04:44:23 PM PDT 24
Peak memory 193944 kb
Host smart-69dd2c97-d806-48cc-a4db-d1c78ff2a087
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897755452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.1897755452
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.684426101
Short name T82
Test name
Test status
Simulation time 40327011 ps
CPU time 0.66 seconds
Started Jul 20 04:44:23 PM PDT 24
Finished Jul 20 04:44:25 PM PDT 24
Peak memory 194744 kb
Host smart-9cee50bf-7d0a-46c2-a74e-0a853c8940ce
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684426101 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.684426101
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1686631340
Short name T833
Test name
Test status
Simulation time 498743862 ps
CPU time 2.65 seconds
Started Jul 20 04:44:23 PM PDT 24
Finished Jul 20 04:44:27 PM PDT 24
Peak memory 198212 kb
Host smart-130f8f92-9f81-406a-8230-63be6cfdb9fa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686631340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1686631340
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3564382286
Short name T36
Test name
Test status
Simulation time 3926967929 ps
CPU time 1.46 seconds
Started Jul 20 04:44:22 PM PDT 24
Finished Jul 20 04:44:24 PM PDT 24
Peak memory 198328 kb
Host smart-d952660e-05c3-4878-8a42-27170ade636f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564382286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3564382286
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1299207266
Short name T817
Test name
Test status
Simulation time 63374230 ps
CPU time 0.72 seconds
Started Jul 20 04:43:48 PM PDT 24
Finished Jul 20 04:43:50 PM PDT 24
Peak memory 195500 kb
Host smart-72c40f93-ae1f-4a45-b2c6-b7e584228588
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299207266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1299207266
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3164957374
Short name T782
Test name
Test status
Simulation time 326341943 ps
CPU time 3.08 seconds
Started Jul 20 04:43:49 PM PDT 24
Finished Jul 20 04:43:54 PM PDT 24
Peak memory 198364 kb
Host smart-40c286bf-1bb3-4a93-959a-f01035158a0c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164957374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3164957374
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3514101337
Short name T812
Test name
Test status
Simulation time 50281390 ps
CPU time 0.68 seconds
Started Jul 20 04:43:52 PM PDT 24
Finished Jul 20 04:43:54 PM PDT 24
Peak memory 195208 kb
Host smart-261e3b0b-56c1-4204-ab50-38ab2d95246c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514101337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3514101337
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2703157066
Short name T766
Test name
Test status
Simulation time 32181240 ps
CPU time 0.86 seconds
Started Jul 20 04:43:55 PM PDT 24
Finished Jul 20 04:43:57 PM PDT 24
Peak memory 198100 kb
Host smart-1e13b463-8c8c-4cdf-bc53-2ae308897ea9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703157066 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2703157066
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1007081943
Short name T84
Test name
Test status
Simulation time 21890932 ps
CPU time 0.63 seconds
Started Jul 20 04:43:48 PM PDT 24
Finished Jul 20 04:43:50 PM PDT 24
Peak memory 194820 kb
Host smart-22cf7463-2415-48ce-ad29-caadf61dc43e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007081943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1007081943
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2885102089
Short name T791
Test name
Test status
Simulation time 44483309 ps
CPU time 0.57 seconds
Started Jul 20 04:43:48 PM PDT 24
Finished Jul 20 04:43:50 PM PDT 24
Peak memory 194572 kb
Host smart-0a0299a4-211c-4544-bba5-fb63c8d014c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885102089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2885102089
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2220928128
Short name T796
Test name
Test status
Simulation time 34071645 ps
CPU time 0.78 seconds
Started Jul 20 04:43:51 PM PDT 24
Finished Jul 20 04:43:53 PM PDT 24
Peak memory 196352 kb
Host smart-b4bc4b44-d372-4aea-a9f0-fe68272e1c8c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220928128 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2220928128
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.352246505
Short name T750
Test name
Test status
Simulation time 243330772 ps
CPU time 1.46 seconds
Started Jul 20 04:43:52 PM PDT 24
Finished Jul 20 04:43:55 PM PDT 24
Peak memory 198280 kb
Host smart-b364806e-af30-4a9f-92e9-850a64f67d8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352246505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.352246505
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.3630939478
Short name T818
Test name
Test status
Simulation time 278995267 ps
CPU time 1.54 seconds
Started Jul 20 04:43:52 PM PDT 24
Finished Jul 20 04:43:56 PM PDT 24
Peak memory 198256 kb
Host smart-fe9d6a74-eb84-46d5-95e2-1f54772338a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630939478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.3630939478
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1995035580
Short name T727
Test name
Test status
Simulation time 14923879 ps
CPU time 0.63 seconds
Started Jul 20 04:44:30 PM PDT 24
Finished Jul 20 04:44:33 PM PDT 24
Peak memory 194284 kb
Host smart-ae444ce7-7b02-4293-ba1d-2998578bacb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995035580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1995035580
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2833017400
Short name T730
Test name
Test status
Simulation time 12626737 ps
CPU time 0.62 seconds
Started Jul 20 04:44:24 PM PDT 24
Finished Jul 20 04:44:27 PM PDT 24
Peak memory 193972 kb
Host smart-cb87da39-2eed-4491-a2c8-87f85f8dbe10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833017400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2833017400
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.4056287005
Short name T828
Test name
Test status
Simulation time 17308991 ps
CPU time 0.6 seconds
Started Jul 20 04:44:20 PM PDT 24
Finished Jul 20 04:44:22 PM PDT 24
Peak memory 193980 kb
Host smart-8bb8dea4-f6fd-4eb3-863b-2ddecde1dfd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056287005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.4056287005
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.3618167367
Short name T728
Test name
Test status
Simulation time 48797338 ps
CPU time 0.63 seconds
Started Jul 20 04:44:26 PM PDT 24
Finished Jul 20 04:44:28 PM PDT 24
Peak memory 194764 kb
Host smart-68245480-962f-4b08-ac6b-457f280c26d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618167367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.3618167367
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.3465216971
Short name T794
Test name
Test status
Simulation time 49324425 ps
CPU time 0.58 seconds
Started Jul 20 04:44:22 PM PDT 24
Finished Jul 20 04:44:23 PM PDT 24
Peak memory 193964 kb
Host smart-f1c4ec6e-9502-429b-ace6-b29151dedab9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465216971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.3465216971
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.624451948
Short name T744
Test name
Test status
Simulation time 41049464 ps
CPU time 0.55 seconds
Started Jul 20 04:44:21 PM PDT 24
Finished Jul 20 04:44:23 PM PDT 24
Peak memory 193964 kb
Host smart-2455f14d-18e9-4f37-a45a-ef5de15319e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624451948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.624451948
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3468849346
Short name T757
Test name
Test status
Simulation time 31526801 ps
CPU time 0.57 seconds
Started Jul 20 04:44:22 PM PDT 24
Finished Jul 20 04:44:24 PM PDT 24
Peak memory 193900 kb
Host smart-9afbedf7-6d58-43fa-b5d6-14db4cb44524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468849346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3468849346
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1798967372
Short name T838
Test name
Test status
Simulation time 11554730 ps
CPU time 0.58 seconds
Started Jul 20 04:44:22 PM PDT 24
Finished Jul 20 04:44:23 PM PDT 24
Peak memory 194500 kb
Host smart-9ad7008f-ac92-4f0f-9acd-6b1d36f0900f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798967372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1798967372
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2948246252
Short name T756
Test name
Test status
Simulation time 18814250 ps
CPU time 0.64 seconds
Started Jul 20 04:44:25 PM PDT 24
Finished Jul 20 04:44:27 PM PDT 24
Peak memory 193992 kb
Host smart-df7c73e4-db75-4c2d-bd8d-dace73d13b12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948246252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2948246252
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.539465348
Short name T820
Test name
Test status
Simulation time 19315802 ps
CPU time 0.62 seconds
Started Jul 20 04:44:25 PM PDT 24
Finished Jul 20 04:44:27 PM PDT 24
Peak memory 193992 kb
Host smart-d0587fea-050f-487c-ba50-0621d4448288
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539465348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.539465348
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2345747291
Short name T77
Test name
Test status
Simulation time 57148398 ps
CPU time 0.65 seconds
Started Jul 20 04:43:56 PM PDT 24
Finished Jul 20 04:43:58 PM PDT 24
Peak memory 195300 kb
Host smart-e7ecbe38-1bba-455c-91fa-954268121688
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345747291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2345747291
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.4053238879
Short name T737
Test name
Test status
Simulation time 167678245 ps
CPU time 2.9 seconds
Started Jul 20 04:43:54 PM PDT 24
Finished Jul 20 04:43:59 PM PDT 24
Peak memory 196956 kb
Host smart-b3d43540-5561-407e-ab37-5cba1b9089ce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053238879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.4053238879
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.807584081
Short name T95
Test name
Test status
Simulation time 53965528 ps
CPU time 0.67 seconds
Started Jul 20 04:43:56 PM PDT 24
Finished Jul 20 04:43:59 PM PDT 24
Peak memory 195720 kb
Host smart-82174733-e2f4-4bcb-8b8a-319c64d888de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807584081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.807584081
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.4167387779
Short name T821
Test name
Test status
Simulation time 94996191 ps
CPU time 0.8 seconds
Started Jul 20 04:43:55 PM PDT 24
Finished Jul 20 04:43:58 PM PDT 24
Peak memory 198064 kb
Host smart-ce664ef3-0bc6-475a-bbf1-7270aad08e53
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167387779 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.4167387779
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.25072990
Short name T115
Test name
Test status
Simulation time 47603754 ps
CPU time 0.58 seconds
Started Jul 20 04:43:54 PM PDT 24
Finished Jul 20 04:43:56 PM PDT 24
Peak memory 194180 kb
Host smart-5258772d-cef1-4aa3-9376-ffda1c7f98c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25072990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_c
sr_rw.25072990
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.2974302651
Short name T804
Test name
Test status
Simulation time 23093156 ps
CPU time 0.66 seconds
Started Jul 20 04:43:55 PM PDT 24
Finished Jul 20 04:43:58 PM PDT 24
Peak memory 194596 kb
Host smart-e2e1c4f6-07c7-40e0-b285-75ef8ea61788
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974302651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.2974302651
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3545818222
Short name T834
Test name
Test status
Simulation time 61286712 ps
CPU time 0.83 seconds
Started Jul 20 04:43:57 PM PDT 24
Finished Jul 20 04:43:59 PM PDT 24
Peak memory 196524 kb
Host smart-0018d4a5-91c3-42e5-8e59-95f561d548cb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545818222 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3545818222
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.15710560
Short name T797
Test name
Test status
Simulation time 73000544 ps
CPU time 1.6 seconds
Started Jul 20 04:43:59 PM PDT 24
Finished Jul 20 04:44:02 PM PDT 24
Peak memory 198200 kb
Host smart-cc86d92f-1072-4647-aa1b-e7c3b93b512d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15710560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.15710560
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.442719407
Short name T35
Test name
Test status
Simulation time 90083557 ps
CPU time 1.17 seconds
Started Jul 20 04:43:57 PM PDT 24
Finished Jul 20 04:44:00 PM PDT 24
Peak memory 198232 kb
Host smart-a8bc129b-4cf8-4a35-bcd4-c790e3e16437
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442719407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.442719407
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3395607508
Short name T780
Test name
Test status
Simulation time 43472055 ps
CPU time 0.59 seconds
Started Jul 20 04:44:24 PM PDT 24
Finished Jul 20 04:44:26 PM PDT 24
Peak memory 193944 kb
Host smart-41bf9c06-ca23-47b0-b4c0-77f886207710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395607508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3395607508
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2090123267
Short name T814
Test name
Test status
Simulation time 24135616 ps
CPU time 0.58 seconds
Started Jul 20 04:44:23 PM PDT 24
Finished Jul 20 04:44:25 PM PDT 24
Peak memory 194556 kb
Host smart-d27047e3-0c55-41f6-880e-96c49e71c365
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090123267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2090123267
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3323406951
Short name T731
Test name
Test status
Simulation time 84077368 ps
CPU time 0.61 seconds
Started Jul 20 04:44:30 PM PDT 24
Finished Jul 20 04:44:33 PM PDT 24
Peak memory 193812 kb
Host smart-2f7049fd-545c-4f5b-a0ce-65e5c111d9be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323406951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3323406951
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.3127342616
Short name T742
Test name
Test status
Simulation time 49062663 ps
CPU time 0.61 seconds
Started Jul 20 04:44:24 PM PDT 24
Finished Jul 20 04:44:26 PM PDT 24
Peak memory 194184 kb
Host smart-36d4aabb-3795-47a5-acfa-637a94011b75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127342616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.3127342616
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3470649927
Short name T735
Test name
Test status
Simulation time 17570112 ps
CPU time 0.58 seconds
Started Jul 20 04:44:24 PM PDT 24
Finished Jul 20 04:44:27 PM PDT 24
Peak memory 193908 kb
Host smart-7699c56d-a45f-4eeb-9202-fd2ee64d9ef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470649927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3470649927
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.1225276036
Short name T810
Test name
Test status
Simulation time 44867922 ps
CPU time 0.63 seconds
Started Jul 20 04:44:24 PM PDT 24
Finished Jul 20 04:44:26 PM PDT 24
Peak memory 193992 kb
Host smart-b8a8fb68-21de-41ca-b76d-4fbb02347906
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225276036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.1225276036
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2931630714
Short name T773
Test name
Test status
Simulation time 15463942 ps
CPU time 0.62 seconds
Started Jul 20 04:44:24 PM PDT 24
Finished Jul 20 04:44:26 PM PDT 24
Peak memory 194676 kb
Host smart-870e0eac-8f9b-49d5-bae4-4f5a483c7db0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931630714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2931630714
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3072333404
Short name T800
Test name
Test status
Simulation time 32836523 ps
CPU time 0.57 seconds
Started Jul 20 04:44:22 PM PDT 24
Finished Jul 20 04:44:24 PM PDT 24
Peak memory 193912 kb
Host smart-fadd3da3-b9fb-4818-8e5e-e3e7d9e329bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072333404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3072333404
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.1719175501
Short name T765
Test name
Test status
Simulation time 14408626 ps
CPU time 0.66 seconds
Started Jul 20 04:44:21 PM PDT 24
Finished Jul 20 04:44:23 PM PDT 24
Peak memory 193984 kb
Host smart-89653167-7727-4b33-8f28-89308e56f393
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719175501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.1719175501
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3548005750
Short name T825
Test name
Test status
Simulation time 16719439 ps
CPU time 0.62 seconds
Started Jul 20 04:44:23 PM PDT 24
Finished Jul 20 04:44:25 PM PDT 24
Peak memory 194044 kb
Host smart-8877c7e8-c74b-444c-b34a-018fa88b44a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548005750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3548005750
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3449666721
Short name T91
Test name
Test status
Simulation time 122493150 ps
CPU time 0.93 seconds
Started Jul 20 04:43:58 PM PDT 24
Finished Jul 20 04:44:00 PM PDT 24
Peak memory 196384 kb
Host smart-8380fb23-9ae6-4591-86ce-c441efc0f380
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449666721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3449666721
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.191359030
Short name T88
Test name
Test status
Simulation time 315813225 ps
CPU time 3.02 seconds
Started Jul 20 04:44:00 PM PDT 24
Finished Jul 20 04:44:04 PM PDT 24
Peak memory 197124 kb
Host smart-c227d2a4-3a96-4e66-a408-6283c3fc6309
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191359030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.191359030
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2630954384
Short name T751
Test name
Test status
Simulation time 14764205 ps
CPU time 0.61 seconds
Started Jul 20 04:43:56 PM PDT 24
Finished Jul 20 04:43:58 PM PDT 24
Peak memory 195116 kb
Host smart-7a07cd5a-616a-4b82-8303-c5f369c293cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630954384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2630954384
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2261337995
Short name T802
Test name
Test status
Simulation time 29006946 ps
CPU time 0.94 seconds
Started Jul 20 04:44:00 PM PDT 24
Finished Jul 20 04:44:02 PM PDT 24
Peak memory 198088 kb
Host smart-2a709837-d427-4ab6-b327-c6cd0e94d39a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261337995 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2261337995
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.1609582196
Short name T90
Test name
Test status
Simulation time 12978805 ps
CPU time 0.65 seconds
Started Jul 20 04:43:57 PM PDT 24
Finished Jul 20 04:43:59 PM PDT 24
Peak memory 193440 kb
Host smart-dde47024-d637-4d2b-a32b-bb76b66984a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609582196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.1609582196
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2935043852
Short name T824
Test name
Test status
Simulation time 13000901 ps
CPU time 0.62 seconds
Started Jul 20 04:43:55 PM PDT 24
Finished Jul 20 04:43:58 PM PDT 24
Peak memory 194000 kb
Host smart-4b12740d-bf59-4df5-a32a-037be2d749a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935043852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2935043852
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2243992428
Short name T99
Test name
Test status
Simulation time 23613843 ps
CPU time 0.75 seconds
Started Jul 20 04:43:54 PM PDT 24
Finished Jul 20 04:43:56 PM PDT 24
Peak memory 196856 kb
Host smart-fe4beb77-1470-4be3-a7f5-204ba8e2b538
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243992428 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2243992428
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.207082782
Short name T816
Test name
Test status
Simulation time 159231238 ps
CPU time 2.96 seconds
Started Jul 20 04:43:55 PM PDT 24
Finished Jul 20 04:44:00 PM PDT 24
Peak memory 198232 kb
Host smart-0cff7abb-9aa0-4dfd-b90c-41dffa443652
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207082782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.207082782
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.418144816
Short name T48
Test name
Test status
Simulation time 158728587 ps
CPU time 1.18 seconds
Started Jul 20 04:43:54 PM PDT 24
Finished Jul 20 04:43:57 PM PDT 24
Peak memory 197724 kb
Host smart-71aaa9e3-f3e9-4b47-8c85-7644518321c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418144816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 4.gpio_tl_intg_err.418144816
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1758168790
Short name T755
Test name
Test status
Simulation time 11697773 ps
CPU time 0.58 seconds
Started Jul 20 04:44:30 PM PDT 24
Finished Jul 20 04:44:33 PM PDT 24
Peak memory 193860 kb
Host smart-2fcdd6b7-7a0c-4cf2-89ab-560f85d50f30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758168790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1758168790
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1601247246
Short name T774
Test name
Test status
Simulation time 18427269 ps
CPU time 0.62 seconds
Started Jul 20 04:44:30 PM PDT 24
Finished Jul 20 04:44:33 PM PDT 24
Peak memory 194476 kb
Host smart-4a31f64d-b988-4601-9bc2-61f722b0a756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601247246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1601247246
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.2483548853
Short name T798
Test name
Test status
Simulation time 16857583 ps
CPU time 0.62 seconds
Started Jul 20 04:44:21 PM PDT 24
Finished Jul 20 04:44:23 PM PDT 24
Peak memory 194024 kb
Host smart-2bd0fe8d-cc3d-43a0-b921-dc9b0431fb8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483548853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.2483548853
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.4085359187
Short name T779
Test name
Test status
Simulation time 34944829 ps
CPU time 0.61 seconds
Started Jul 20 04:44:24 PM PDT 24
Finished Jul 20 04:44:26 PM PDT 24
Peak memory 194032 kb
Host smart-749118f5-3c2b-43ae-aeb8-2c8500136a48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085359187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.4085359187
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.4063706714
Short name T759
Test name
Test status
Simulation time 20262435 ps
CPU time 0.61 seconds
Started Jul 20 04:44:22 PM PDT 24
Finished Jul 20 04:44:24 PM PDT 24
Peak memory 194552 kb
Host smart-b4ebf91e-188f-40bd-9138-75b6efd1ce1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063706714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.4063706714
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1587416468
Short name T736
Test name
Test status
Simulation time 49970140 ps
CPU time 0.62 seconds
Started Jul 20 04:44:26 PM PDT 24
Finished Jul 20 04:44:28 PM PDT 24
Peak memory 194620 kb
Host smart-f68d9c0f-a3e1-45aa-b3f3-8e491d2c08e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587416468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1587416468
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.407736574
Short name T807
Test name
Test status
Simulation time 12691948 ps
CPU time 0.57 seconds
Started Jul 20 04:44:24 PM PDT 24
Finished Jul 20 04:44:26 PM PDT 24
Peak memory 194600 kb
Host smart-3e4e0a74-9769-4395-8c26-22afb9898705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407736574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.407736574
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2549325338
Short name T836
Test name
Test status
Simulation time 23939858 ps
CPU time 0.61 seconds
Started Jul 20 04:44:24 PM PDT 24
Finished Jul 20 04:44:26 PM PDT 24
Peak memory 194052 kb
Host smart-07ab90ee-c2e4-4f6b-a764-646e1b1b0e27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549325338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2549325338
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.717863239
Short name T747
Test name
Test status
Simulation time 43656919 ps
CPU time 0.6 seconds
Started Jul 20 04:44:31 PM PDT 24
Finished Jul 20 04:44:34 PM PDT 24
Peak memory 193956 kb
Host smart-7999107e-f250-4170-a077-25c1b40beadb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717863239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.717863239
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.314808284
Short name T769
Test name
Test status
Simulation time 15543351 ps
CPU time 0.61 seconds
Started Jul 20 04:44:28 PM PDT 24
Finished Jul 20 04:44:30 PM PDT 24
Peak memory 193896 kb
Host smart-a76f8a3f-3b2f-495d-9b32-a62dea59fe0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314808284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.314808284
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1526669451
Short name T768
Test name
Test status
Simulation time 35425373 ps
CPU time 0.97 seconds
Started Jul 20 04:43:54 PM PDT 24
Finished Jul 20 04:43:57 PM PDT 24
Peak memory 198204 kb
Host smart-b5523857-ee23-42eb-954f-3b4d27c41036
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526669451 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1526669451
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.3795356066
Short name T87
Test name
Test status
Simulation time 14380130 ps
CPU time 0.6 seconds
Started Jul 20 04:43:54 PM PDT 24
Finished Jul 20 04:43:56 PM PDT 24
Peak memory 194948 kb
Host smart-620ac569-18ad-4589-badb-7a233c7aa51b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795356066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.3795356066
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.1056919178
Short name T734
Test name
Test status
Simulation time 15050161 ps
CPU time 0.57 seconds
Started Jul 20 04:44:05 PM PDT 24
Finished Jul 20 04:44:07 PM PDT 24
Peak memory 193968 kb
Host smart-855828bb-2fc0-4587-845c-dbb470fc427e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056919178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.1056919178
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2543521149
Short name T840
Test name
Test status
Simulation time 177551891 ps
CPU time 0.92 seconds
Started Jul 20 04:43:59 PM PDT 24
Finished Jul 20 04:44:01 PM PDT 24
Peak memory 196372 kb
Host smart-2cb1691c-a88b-4eb3-a038-14ead4ddfb8e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543521149 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2543521149
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3021451961
Short name T806
Test name
Test status
Simulation time 151366791 ps
CPU time 2.35 seconds
Started Jul 20 04:43:59 PM PDT 24
Finished Jul 20 04:44:02 PM PDT 24
Peak memory 198208 kb
Host smart-e58c0bbd-c972-4e26-a8ac-8daef3115629
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021451961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3021451961
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.4134474360
Short name T781
Test name
Test status
Simulation time 86668566 ps
CPU time 0.88 seconds
Started Jul 20 04:43:55 PM PDT 24
Finished Jul 20 04:43:58 PM PDT 24
Peak memory 198100 kb
Host smart-a62a67a3-e328-462c-a701-ab76494e2a58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134474360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.4134474360
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.233668254
Short name T754
Test name
Test status
Simulation time 36874959 ps
CPU time 0.66 seconds
Started Jul 20 04:44:07 PM PDT 24
Finished Jul 20 04:44:09 PM PDT 24
Peak memory 197200 kb
Host smart-b4479e19-003b-4ada-91db-23aec41a6560
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233668254 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.233668254
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2564566089
Short name T741
Test name
Test status
Simulation time 36356811 ps
CPU time 0.59 seconds
Started Jul 20 04:44:04 PM PDT 24
Finished Jul 20 04:44:05 PM PDT 24
Peak memory 194708 kb
Host smart-50b296e9-9314-4e75-8ec3-cbdf3a367654
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564566089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2564566089
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1185625892
Short name T786
Test name
Test status
Simulation time 23005572 ps
CPU time 0.62 seconds
Started Jul 20 04:44:05 PM PDT 24
Finished Jul 20 04:44:07 PM PDT 24
Peak memory 193896 kb
Host smart-08fad84e-9af4-4c67-b130-148230c49bb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185625892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1185625892
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.1805745005
Short name T789
Test name
Test status
Simulation time 45719182 ps
CPU time 0.66 seconds
Started Jul 20 04:44:04 PM PDT 24
Finished Jul 20 04:44:05 PM PDT 24
Peak memory 196008 kb
Host smart-010ecf20-ff7c-4f55-b83a-71ae792d6654
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805745005 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.1805745005
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.3776648247
Short name T763
Test name
Test status
Simulation time 79872342 ps
CPU time 1.88 seconds
Started Jul 20 04:44:05 PM PDT 24
Finished Jul 20 04:44:08 PM PDT 24
Peak memory 198268 kb
Host smart-384e1b95-50bf-43e3-bbdd-dd03c5ec3722
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776648247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.3776648247
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1781825649
Short name T50
Test name
Test status
Simulation time 155770926 ps
CPU time 0.86 seconds
Started Jul 20 04:44:05 PM PDT 24
Finished Jul 20 04:44:07 PM PDT 24
Peak memory 197756 kb
Host smart-c3e84b79-c198-4cde-9b93-82bf5ca2e5ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781825649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1781825649
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2444189223
Short name T803
Test name
Test status
Simulation time 94360195 ps
CPU time 1.12 seconds
Started Jul 20 04:44:06 PM PDT 24
Finished Jul 20 04:44:09 PM PDT 24
Peak memory 198432 kb
Host smart-bd0dc9ac-0445-48c1-948e-a45d2b879c1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444189223 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2444189223
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2522151636
Short name T116
Test name
Test status
Simulation time 43878878 ps
CPU time 0.58 seconds
Started Jul 20 04:44:05 PM PDT 24
Finished Jul 20 04:44:07 PM PDT 24
Peak memory 193508 kb
Host smart-1aa1391c-da16-40e3-b865-cb282588bd40
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522151636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2522151636
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.1615895922
Short name T837
Test name
Test status
Simulation time 45505872 ps
CPU time 0.63 seconds
Started Jul 20 04:44:05 PM PDT 24
Finished Jul 20 04:44:07 PM PDT 24
Peak memory 193992 kb
Host smart-3310b55e-4adb-45b1-9619-086402369d39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615895922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.1615895922
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.657843015
Short name T101
Test name
Test status
Simulation time 21114800 ps
CPU time 0.74 seconds
Started Jul 20 04:44:05 PM PDT 24
Finished Jul 20 04:44:07 PM PDT 24
Peak memory 196268 kb
Host smart-1c8f48a6-e2f3-4528-8471-b7c1b56e5c7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657843015 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.657843015
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1542725032
Short name T790
Test name
Test status
Simulation time 155448644 ps
CPU time 1.73 seconds
Started Jul 20 04:44:07 PM PDT 24
Finished Jul 20 04:44:10 PM PDT 24
Peak memory 198208 kb
Host smart-90092e97-56bd-4f6f-afcd-a83478467ec7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542725032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1542725032
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.3460894546
Short name T830
Test name
Test status
Simulation time 94480454 ps
CPU time 0.83 seconds
Started Jul 20 04:44:05 PM PDT 24
Finished Jul 20 04:44:07 PM PDT 24
Peak memory 197384 kb
Host smart-64963be1-49f7-4cb6-a134-58c604a9b269
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460894546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.3460894546
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.846956415
Short name T827
Test name
Test status
Simulation time 72378600 ps
CPU time 0.77 seconds
Started Jul 20 04:44:04 PM PDT 24
Finished Jul 20 04:44:05 PM PDT 24
Peak memory 198144 kb
Host smart-66fe406f-8897-4760-bf6f-4cd14c616dba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846956415 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.846956415
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1202840419
Short name T815
Test name
Test status
Simulation time 40977251 ps
CPU time 0.61 seconds
Started Jul 20 04:44:05 PM PDT 24
Finished Jul 20 04:44:07 PM PDT 24
Peak memory 195676 kb
Host smart-40b91ef6-e139-4952-9d7f-a0e268e08915
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202840419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1202840419
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.3616860879
Short name T761
Test name
Test status
Simulation time 16485786 ps
CPU time 0.6 seconds
Started Jul 20 04:44:15 PM PDT 24
Finished Jul 20 04:44:18 PM PDT 24
Peak memory 194556 kb
Host smart-77c87527-2b4d-4606-86df-c842247e82e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616860879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.3616860879
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.329447538
Short name T104
Test name
Test status
Simulation time 61827108 ps
CPU time 0.83 seconds
Started Jul 20 04:44:05 PM PDT 24
Finished Jul 20 04:44:08 PM PDT 24
Peak memory 196368 kb
Host smart-61e25e66-acc1-499e-9571-d52ec0f3d3b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329447538 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 8.gpio_same_csr_outstanding.329447538
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.847430649
Short name T795
Test name
Test status
Simulation time 119024720 ps
CPU time 2.18 seconds
Started Jul 20 04:44:03 PM PDT 24
Finished Jul 20 04:44:05 PM PDT 24
Peak memory 198316 kb
Host smart-93db238c-978d-40bb-a422-de4272981ad2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847430649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.847430649
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.1128013335
Short name T46
Test name
Test status
Simulation time 110369170 ps
CPU time 1.35 seconds
Started Jul 20 04:44:05 PM PDT 24
Finished Jul 20 04:44:08 PM PDT 24
Peak memory 198236 kb
Host smart-d451f65c-ea5c-4d4d-8d99-3894898308cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128013335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.1128013335
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1208523144
Short name T822
Test name
Test status
Simulation time 30065570 ps
CPU time 0.63 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:16 PM PDT 24
Peak memory 197196 kb
Host smart-9303fe6a-dd15-4224-8b08-b0b59f0d2491
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208523144 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1208523144
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1242587794
Short name T76
Test name
Test status
Simulation time 17585619 ps
CPU time 0.66 seconds
Started Jul 20 04:44:14 PM PDT 24
Finished Jul 20 04:44:17 PM PDT 24
Peak memory 195504 kb
Host smart-081fcb81-8d47-4b3a-8a9c-390bb47618c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242587794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1242587794
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.672932387
Short name T748
Test name
Test status
Simulation time 52351665 ps
CPU time 0.59 seconds
Started Jul 20 04:44:16 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 194884 kb
Host smart-654ae46b-0c4e-4c7b-b198-419663831997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672932387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.672932387
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3380133208
Short name T85
Test name
Test status
Simulation time 35823263 ps
CPU time 0.86 seconds
Started Jul 20 04:44:15 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 196096 kb
Host smart-d47827ea-9b72-4c2f-8a41-34fd711110f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380133208 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3380133208
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2205771236
Short name T819
Test name
Test status
Simulation time 40414426 ps
CPU time 2.06 seconds
Started Jul 20 04:44:11 PM PDT 24
Finished Jul 20 04:44:14 PM PDT 24
Peak memory 198272 kb
Host smart-4321040c-dd51-4c86-b406-a9d4ddce3ff1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205771236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2205771236
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.434149360
Short name T51
Test name
Test status
Simulation time 171481772 ps
CPU time 0.91 seconds
Started Jul 20 04:44:16 PM PDT 24
Finished Jul 20 04:44:19 PM PDT 24
Peak memory 197160 kb
Host smart-81588002-b79e-4b83-8d76-7b06d6bd0a67
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434149360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 9.gpio_tl_intg_err.434149360
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.573351200
Short name T386
Test name
Test status
Simulation time 11502017 ps
CPU time 0.54 seconds
Started Jul 20 04:33:37 PM PDT 24
Finished Jul 20 04:33:45 PM PDT 24
Peak memory 194108 kb
Host smart-1220acef-6040-4ebc-beaf-2b659db25421
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573351200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.573351200
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.3261790136
Short name T501
Test name
Test status
Simulation time 44731554 ps
CPU time 0.75 seconds
Started Jul 20 04:33:47 PM PDT 24
Finished Jul 20 04:33:50 PM PDT 24
Peak memory 194316 kb
Host smart-6d235ee4-4a4b-4f4e-b87f-63a2ca1ad78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261790136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.3261790136
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.331108424
Short name T617
Test name
Test status
Simulation time 478648158 ps
CPU time 5.55 seconds
Started Jul 20 04:33:40 PM PDT 24
Finished Jul 20 04:33:52 PM PDT 24
Peak memory 196684 kb
Host smart-9be242d2-75d2-4c64-9a7d-510af7cb36c4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331108424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stress
.331108424
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.1635218206
Short name T503
Test name
Test status
Simulation time 50831302 ps
CPU time 0.83 seconds
Started Jul 20 04:33:32 PM PDT 24
Finished Jul 20 04:33:41 PM PDT 24
Peak memory 196168 kb
Host smart-164d5dad-f73c-40f4-80b6-beb8c479dbc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635218206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.1635218206
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.3019331910
Short name T610
Test name
Test status
Simulation time 183228204 ps
CPU time 1.28 seconds
Started Jul 20 04:33:43 PM PDT 24
Finished Jul 20 04:33:50 PM PDT 24
Peak memory 197360 kb
Host smart-3f1e5882-8c14-4f7f-bccb-bfe93be03233
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019331910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.3019331910
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3172796819
Short name T121
Test name
Test status
Simulation time 72513971 ps
CPU time 2.7 seconds
Started Jul 20 04:33:40 PM PDT 24
Finished Jul 20 04:33:50 PM PDT 24
Peak memory 197928 kb
Host smart-c347658f-bd95-4c2c-a585-a9ed63f26a99
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172796819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3172796819
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1608852187
Short name T352
Test name
Test status
Simulation time 444723740 ps
CPU time 2.66 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:33:40 PM PDT 24
Peak memory 197160 kb
Host smart-6997a8b1-6056-4131-b598-320a81d48c42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608852187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1608852187
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.50110313
Short name T510
Test name
Test status
Simulation time 175848706 ps
CPU time 1.03 seconds
Started Jul 20 04:33:39 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 196088 kb
Host smart-963e9df0-eed1-41f8-a210-2f42125c6a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50110313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.50110313
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1140719543
Short name T74
Test name
Test status
Simulation time 70759993 ps
CPU time 0.79 seconds
Started Jul 20 04:33:40 PM PDT 24
Finished Jul 20 04:33:48 PM PDT 24
Peak memory 197304 kb
Host smart-4d61a1ab-e9a7-4be3-8e18-7d491c6d08a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140719543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1140719543
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.1671321018
Short name T52
Test name
Test status
Simulation time 500305366 ps
CPU time 0.95 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:33:38 PM PDT 24
Peak memory 215128 kb
Host smart-de058908-3a80-4045-a66d-5bb2c71c3f74
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671321018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.1671321018
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.1144275660
Short name T394
Test name
Test status
Simulation time 74402090 ps
CPU time 1.24 seconds
Started Jul 20 04:33:28 PM PDT 24
Finished Jul 20 04:33:37 PM PDT 24
Peak memory 196420 kb
Host smart-a08211f3-4303-45d2-9c63-7867468d4244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144275660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1144275660
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2995594448
Short name T613
Test name
Test status
Simulation time 87424933 ps
CPU time 0.96 seconds
Started Jul 20 04:33:37 PM PDT 24
Finished Jul 20 04:33:46 PM PDT 24
Peak memory 195820 kb
Host smart-f76d627d-87fb-4895-9b1d-1ce914b44254
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995594448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2995594448
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2338951359
Short name T417
Test name
Test status
Simulation time 27263158240 ps
CPU time 154.9 seconds
Started Jul 20 04:33:27 PM PDT 24
Finished Jul 20 04:36:10 PM PDT 24
Peak memory 198280 kb
Host smart-19524f06-0290-41ca-9aa3-cdb72d8e26bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338951359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2338951359
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3289765464
Short name T57
Test name
Test status
Simulation time 278129634919 ps
CPU time 931.89 seconds
Started Jul 20 04:33:28 PM PDT 24
Finished Jul 20 04:49:07 PM PDT 24
Peak memory 198336 kb
Host smart-4cd36491-dbc0-46da-8a3b-c7bdf777d9d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3289765464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3289765464
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3257942876
Short name T240
Test name
Test status
Simulation time 12506042 ps
CPU time 0.56 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 04:33:40 PM PDT 24
Peak memory 194224 kb
Host smart-7d2d5724-41ab-43c3-86d4-1d6f4be2165e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257942876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3257942876
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3723586973
Short name T545
Test name
Test status
Simulation time 59556767 ps
CPU time 0.87 seconds
Started Jul 20 04:33:33 PM PDT 24
Finished Jul 20 04:33:43 PM PDT 24
Peak memory 196548 kb
Host smart-84a7ea19-a8fd-4d86-ab1e-79212e08b4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723586973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3723586973
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.4065393091
Short name T603
Test name
Test status
Simulation time 881918039 ps
CPU time 21.77 seconds
Started Jul 20 04:33:40 PM PDT 24
Finished Jul 20 04:34:09 PM PDT 24
Peak memory 198040 kb
Host smart-6f6f466b-5156-471f-a0a8-bd81705a1071
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065393091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.4065393091
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.419789119
Short name T683
Test name
Test status
Simulation time 77416829 ps
CPU time 0.59 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 04:33:34 PM PDT 24
Peak memory 194500 kb
Host smart-9a456f81-9e36-47aa-b64b-acafe9b93cd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419789119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.419789119
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3050929714
Short name T674
Test name
Test status
Simulation time 55662108 ps
CPU time 0.69 seconds
Started Jul 20 04:33:42 PM PDT 24
Finished Jul 20 04:33:49 PM PDT 24
Peak memory 195096 kb
Host smart-fa3d060e-1961-4618-ba84-e4dbace1e434
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050929714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3050929714
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2028609114
Short name T384
Test name
Test status
Simulation time 43903918 ps
CPU time 1.81 seconds
Started Jul 20 04:33:35 PM PDT 24
Finished Jul 20 04:33:45 PM PDT 24
Peak memory 198072 kb
Host smart-78a22a6d-2da3-465f-8343-2e5854f59ea2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028609114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2028609114
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1905834898
Short name T343
Test name
Test status
Simulation time 144974135 ps
CPU time 1.54 seconds
Started Jul 20 04:33:32 PM PDT 24
Finished Jul 20 04:33:41 PM PDT 24
Peak memory 196952 kb
Host smart-1dc17758-cb1f-4cc2-8db8-bd18bd0c903f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905834898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1905834898
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3479984933
Short name T698
Test name
Test status
Simulation time 21114710 ps
CPU time 0.79 seconds
Started Jul 20 04:33:38 PM PDT 24
Finished Jul 20 04:33:46 PM PDT 24
Peak memory 196568 kb
Host smart-c94b9598-6557-404d-8943-19289f19b6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479984933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3479984933
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1903572932
Short name T24
Test name
Test status
Simulation time 26097937 ps
CPU time 0.7 seconds
Started Jul 20 04:33:38 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 195692 kb
Host smart-c1514995-5ff0-4228-9682-2487e13be96b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903572932 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1903572932
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.675253327
Short name T249
Test name
Test status
Simulation time 74050714 ps
CPU time 1.11 seconds
Started Jul 20 04:33:34 PM PDT 24
Finished Jul 20 04:33:44 PM PDT 24
Peak memory 196692 kb
Host smart-b1f4994c-547d-45d0-b624-b9b1fe36ce94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675253327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.675253327
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.1484765546
Short name T53
Test name
Test status
Simulation time 207509944 ps
CPU time 0.84 seconds
Started Jul 20 04:33:32 PM PDT 24
Finished Jul 20 04:33:41 PM PDT 24
Peak memory 215100 kb
Host smart-22ce2a43-907f-4a37-a91f-dd4a2552b821
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484765546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.1484765546
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.3612801152
Short name T318
Test name
Test status
Simulation time 21227584 ps
CPU time 0.69 seconds
Started Jul 20 04:33:42 PM PDT 24
Finished Jul 20 04:33:49 PM PDT 24
Peak memory 194876 kb
Host smart-754e3212-6a23-4a0f-96aa-00be2ec56341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612801152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3612801152
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.145735239
Short name T574
Test name
Test status
Simulation time 85728548 ps
CPU time 0.9 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:33:39 PM PDT 24
Peak memory 196484 kb
Host smart-b29d833d-67c1-443f-8f80-17959034b75c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145735239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.145735239
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1879719593
Short name T209
Test name
Test status
Simulation time 6908439564 ps
CPU time 185.16 seconds
Started Jul 20 04:33:43 PM PDT 24
Finished Jul 20 04:36:53 PM PDT 24
Peak memory 198188 kb
Host smart-4ac5d5fc-a6d8-43ed-b40b-05cb67fce303
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879719593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1879719593
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1184603752
Short name T447
Test name
Test status
Simulation time 12627449 ps
CPU time 0.61 seconds
Started Jul 20 04:34:29 PM PDT 24
Finished Jul 20 04:34:32 PM PDT 24
Peak memory 194808 kb
Host smart-6672451d-9efc-4167-b87b-091bd4339778
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184603752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1184603752
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3719503692
Short name T224
Test name
Test status
Simulation time 29159887 ps
CPU time 0.65 seconds
Started Jul 20 04:34:24 PM PDT 24
Finished Jul 20 04:34:26 PM PDT 24
Peak memory 194012 kb
Host smart-5aa519b9-7dd7-4c5f-bce1-915dcb755e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719503692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3719503692
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.4163491340
Short name T367
Test name
Test status
Simulation time 1403796961 ps
CPU time 12.02 seconds
Started Jul 20 04:34:24 PM PDT 24
Finished Jul 20 04:34:38 PM PDT 24
Peak memory 196992 kb
Host smart-f40b0056-0647-4c61-ba56-4f352776625a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163491340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.4163491340
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.531244969
Short name T615
Test name
Test status
Simulation time 39366479 ps
CPU time 0.58 seconds
Started Jul 20 04:34:26 PM PDT 24
Finished Jul 20 04:34:28 PM PDT 24
Peak memory 194180 kb
Host smart-9a90ec59-55bf-4c26-b953-8e7095c20cf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531244969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.531244969
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.3636540555
Short name T125
Test name
Test status
Simulation time 154630470 ps
CPU time 1.06 seconds
Started Jul 20 04:34:25 PM PDT 24
Finished Jul 20 04:34:28 PM PDT 24
Peak memory 196988 kb
Host smart-a67a929f-79ed-4310-bedf-619a3a4f70b2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636540555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.3636540555
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1455534633
Short name T685
Test name
Test status
Simulation time 51140685 ps
CPU time 1.92 seconds
Started Jul 20 04:34:23 PM PDT 24
Finished Jul 20 04:34:27 PM PDT 24
Peak memory 198072 kb
Host smart-9b484308-a936-46d2-af91-c7522cc4fdb2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455534633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1455534633
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.699519838
Short name T589
Test name
Test status
Simulation time 91295301 ps
CPU time 2.59 seconds
Started Jul 20 04:34:26 PM PDT 24
Finished Jul 20 04:34:30 PM PDT 24
Peak memory 197236 kb
Host smart-7803992b-d6f8-4c20-bab4-b2976a1c7bf2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699519838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger.
699519838
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.1909364315
Short name T702
Test name
Test status
Simulation time 108057042 ps
CPU time 1.06 seconds
Started Jul 20 04:34:27 PM PDT 24
Finished Jul 20 04:34:30 PM PDT 24
Peak memory 196148 kb
Host smart-76f467b2-3d5f-464b-a4be-b211eecf289a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909364315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.1909364315
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3489979025
Short name T313
Test name
Test status
Simulation time 197555899 ps
CPU time 1 seconds
Started Jul 20 04:34:27 PM PDT 24
Finished Jul 20 04:34:30 PM PDT 24
Peak memory 196140 kb
Host smart-d7f00b73-a5b9-4a2c-9f93-f7e6ab3a6f39
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489979025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3489979025
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1100533554
Short name T420
Test name
Test status
Simulation time 1135477350 ps
CPU time 6.49 seconds
Started Jul 20 04:34:28 PM PDT 24
Finished Jul 20 04:34:36 PM PDT 24
Peak memory 198120 kb
Host smart-7a175dec-4351-4291-9be4-c64d39c29fd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100533554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1100533554
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.1090681473
Short name T170
Test name
Test status
Simulation time 420471522 ps
CPU time 1.58 seconds
Started Jul 20 04:34:25 PM PDT 24
Finished Jul 20 04:34:28 PM PDT 24
Peak memory 196936 kb
Host smart-2b9fe00b-fb34-4de3-80cb-179aab7a4ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090681473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.1090681473
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.4091165088
Short name T111
Test name
Test status
Simulation time 95595333 ps
CPU time 1.01 seconds
Started Jul 20 04:34:22 PM PDT 24
Finished Jul 20 04:34:24 PM PDT 24
Peak memory 195624 kb
Host smart-9f0e7fcd-b315-468e-9d86-46f913116563
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091165088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.4091165088
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1350348834
Short name T393
Test name
Test status
Simulation time 7829501828 ps
CPU time 187 seconds
Started Jul 20 04:34:31 PM PDT 24
Finished Jul 20 04:37:40 PM PDT 24
Peak memory 198204 kb
Host smart-7cb406b4-96eb-4860-bc06-0d5912b026f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350348834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1350348834
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_alert_test.3586431020
Short name T587
Test name
Test status
Simulation time 43365457 ps
CPU time 0.57 seconds
Started Jul 20 04:34:33 PM PDT 24
Finished Jul 20 04:34:36 PM PDT 24
Peak memory 194044 kb
Host smart-eaea00f1-577c-4f1f-998f-835d57c94d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586431020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.3586431020
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2629526930
Short name T72
Test name
Test status
Simulation time 52058433 ps
CPU time 0.67 seconds
Started Jul 20 04:34:26 PM PDT 24
Finished Jul 20 04:34:28 PM PDT 24
Peak memory 194240 kb
Host smart-fbd67c26-fc66-4dd1-bcc8-63fc29168ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629526930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2629526930
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2181493307
Short name T342
Test name
Test status
Simulation time 319266969 ps
CPU time 16.76 seconds
Started Jul 20 04:34:24 PM PDT 24
Finished Jul 20 04:34:42 PM PDT 24
Peak memory 197028 kb
Host smart-829ea4bd-7e10-4226-a7e4-266ec7e46c38
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181493307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2181493307
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3353248847
Short name T267
Test name
Test status
Simulation time 354343451 ps
CPU time 0.88 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:35 PM PDT 24
Peak memory 195724 kb
Host smart-3fa69de3-58ea-4458-910a-03d5b973a011
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353248847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3353248847
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.584043590
Short name T505
Test name
Test status
Simulation time 137075092 ps
CPU time 1.08 seconds
Started Jul 20 04:34:29 PM PDT 24
Finished Jul 20 04:34:32 PM PDT 24
Peak memory 196664 kb
Host smart-37957263-65a8-49ee-a9ef-723d9c01ad22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584043590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.584043590
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.536006019
Short name T241
Test name
Test status
Simulation time 28195273 ps
CPU time 1.04 seconds
Started Jul 20 04:34:29 PM PDT 24
Finished Jul 20 04:34:32 PM PDT 24
Peak memory 196436 kb
Host smart-f544335d-cf38-4545-85c9-6f473c72ec7b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536006019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.536006019
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1153113537
Short name T544
Test name
Test status
Simulation time 743105353 ps
CPU time 1.4 seconds
Started Jul 20 04:34:24 PM PDT 24
Finished Jul 20 04:34:27 PM PDT 24
Peak memory 196816 kb
Host smart-d5783ada-222f-42d3-b450-36c2867f3f36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153113537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1153113537
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2009298819
Short name T598
Test name
Test status
Simulation time 75522716 ps
CPU time 0.67 seconds
Started Jul 20 04:34:25 PM PDT 24
Finished Jul 20 04:34:28 PM PDT 24
Peak memory 194424 kb
Host smart-7af8c609-022d-4ad6-858f-0930e6ed89be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009298819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2009298819
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.1455463584
Short name T580
Test name
Test status
Simulation time 21080940 ps
CPU time 0.68 seconds
Started Jul 20 04:34:23 PM PDT 24
Finished Jul 20 04:34:25 PM PDT 24
Peak memory 194364 kb
Host smart-23cb7b5e-29e9-4986-be0b-8514584fe489
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455463584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.1455463584
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3858230950
Short name T301
Test name
Test status
Simulation time 160651506 ps
CPU time 1.96 seconds
Started Jul 20 04:34:31 PM PDT 24
Finished Jul 20 04:34:35 PM PDT 24
Peak memory 198020 kb
Host smart-32649e86-1990-4d3d-bdf9-6443e5d1c899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858230950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3858230950
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3628780759
Short name T55
Test name
Test status
Simulation time 64014869 ps
CPU time 1.1 seconds
Started Jul 20 04:34:26 PM PDT 24
Finished Jul 20 04:34:29 PM PDT 24
Peak memory 196592 kb
Host smart-fa6ff501-e680-4da3-82ac-8a3844d1a271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628780759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3628780759
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3482619134
Short name T597
Test name
Test status
Simulation time 287333467 ps
CPU time 1.21 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:36 PM PDT 24
Peak memory 195660 kb
Host smart-ba224beb-dae5-4345-b960-90c64e1b091d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482619134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3482619134
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1435072553
Short name T28
Test name
Test status
Simulation time 2338761545 ps
CPU time 46.68 seconds
Started Jul 20 04:34:30 PM PDT 24
Finished Jul 20 04:35:19 PM PDT 24
Peak memory 198304 kb
Host smart-d4523d0b-23eb-4b31-aed6-06132fa66e75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435072553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1435072553
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.4129283204
Short name T456
Test name
Test status
Simulation time 238051466703 ps
CPU time 1258.68 seconds
Started Jul 20 04:34:35 PM PDT 24
Finished Jul 20 04:55:37 PM PDT 24
Peak memory 198248 kb
Host smart-af184cf4-23eb-451d-9609-d935cf9063a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4129283204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.4129283204
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1846021596
Short name T650
Test name
Test status
Simulation time 42061935 ps
CPU time 0.56 seconds
Started Jul 20 04:34:30 PM PDT 24
Finished Jul 20 04:34:32 PM PDT 24
Peak memory 194120 kb
Host smart-7f1f9a6f-aaed-4737-9200-2618a02a2506
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846021596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1846021596
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3113412288
Short name T192
Test name
Test status
Simulation time 105136029 ps
CPU time 0.72 seconds
Started Jul 20 04:34:34 PM PDT 24
Finished Jul 20 04:34:38 PM PDT 24
Peak memory 195408 kb
Host smart-ba4e26a5-000b-4207-b6d3-27032ddaa09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113412288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3113412288
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1095749861
Short name T213
Test name
Test status
Simulation time 612429135 ps
CPU time 17.42 seconds
Started Jul 20 04:34:35 PM PDT 24
Finished Jul 20 04:34:56 PM PDT 24
Peak memory 195660 kb
Host smart-32ec2977-da0f-47e4-bf28-863c78761d35
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095749861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1095749861
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.227942348
Short name T19
Test name
Test status
Simulation time 43103802 ps
CPU time 0.74 seconds
Started Jul 20 04:34:37 PM PDT 24
Finished Jul 20 04:34:41 PM PDT 24
Peak memory 194688 kb
Host smart-87f1d5c0-6351-4d37-8d95-928ff6b70f6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227942348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.227942348
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.1896329672
Short name T200
Test name
Test status
Simulation time 161044073 ps
CPU time 1.24 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:35 PM PDT 24
Peak memory 196908 kb
Host smart-76ccfa6e-afe0-4274-aa33-8e3251884ebe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896329672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.1896329672
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.175774943
Short name T319
Test name
Test status
Simulation time 137096262 ps
CPU time 3.15 seconds
Started Jul 20 04:34:31 PM PDT 24
Finished Jul 20 04:34:37 PM PDT 24
Peak memory 198160 kb
Host smart-b93ea655-7dc7-4b26-91fb-a39b54d599a2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175774943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.175774943
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.2254244789
Short name T180
Test name
Test status
Simulation time 41304440 ps
CPU time 1.23 seconds
Started Jul 20 04:34:31 PM PDT 24
Finished Jul 20 04:34:33 PM PDT 24
Peak memory 196612 kb
Host smart-fd82eafc-8ff4-4774-87a3-4bc04409bd2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254244789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.2254244789
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.4010020844
Short name T572
Test name
Test status
Simulation time 34008358 ps
CPU time 1.19 seconds
Started Jul 20 04:34:37 PM PDT 24
Finished Jul 20 04:34:41 PM PDT 24
Peak memory 198168 kb
Host smart-375fd2cb-84fd-4d3d-b484-6b7f3a995c76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010020844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.4010020844
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2122859578
Short name T659
Test name
Test status
Simulation time 50934362 ps
CPU time 1.24 seconds
Started Jul 20 04:34:34 PM PDT 24
Finished Jul 20 04:34:38 PM PDT 24
Peak memory 197036 kb
Host smart-ab1df512-ca61-4981-afc5-f35a84083dab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122859578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2122859578
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1392831337
Short name T563
Test name
Test status
Simulation time 70411325 ps
CPU time 3.27 seconds
Started Jul 20 04:34:31 PM PDT 24
Finished Jul 20 04:34:36 PM PDT 24
Peak memory 198056 kb
Host smart-d1b0c8f7-8c5c-4e30-a0c6-724c316da010
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392831337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1392831337
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3590706147
Short name T152
Test name
Test status
Simulation time 58257647 ps
CPU time 0.99 seconds
Started Jul 20 04:34:34 PM PDT 24
Finished Jul 20 04:34:38 PM PDT 24
Peak memory 195844 kb
Host smart-d029ceca-3707-4b9a-9a36-bd6d92c354f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590706147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3590706147
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3999696975
Short name T479
Test name
Test status
Simulation time 60349976 ps
CPU time 1.08 seconds
Started Jul 20 04:34:31 PM PDT 24
Finished Jul 20 04:34:34 PM PDT 24
Peak memory 195900 kb
Host smart-62d774a1-df5e-4623-a6e3-9117c14ac2a9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999696975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3999696975
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1677539213
Short name T139
Test name
Test status
Simulation time 14246226753 ps
CPU time 103.28 seconds
Started Jul 20 04:34:35 PM PDT 24
Finished Jul 20 04:36:21 PM PDT 24
Peak memory 198256 kb
Host smart-49b20533-b243-4dd2-b700-0e0805f374fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677539213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1677539213
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1177926532
Short name T588
Test name
Test status
Simulation time 492021986541 ps
CPU time 2059.74 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 05:08:54 PM PDT 24
Peak memory 198332 kb
Host smart-690a898f-ebdf-43a7-ab48-e89ebbdd0a19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1177926532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1177926532
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.4187777873
Short name T190
Test name
Test status
Simulation time 39951734 ps
CPU time 0.88 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:35 PM PDT 24
Peak memory 197124 kb
Host smart-b10303f9-d2bc-403d-80b1-e5b45d8a0a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187777873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.4187777873
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1367420150
Short name T330
Test name
Test status
Simulation time 1357277145 ps
CPU time 17.42 seconds
Started Jul 20 04:34:33 PM PDT 24
Finished Jul 20 04:34:53 PM PDT 24
Peak memory 197200 kb
Host smart-7b7aea45-383f-4aee-9a6e-0bd58e01dc47
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367420150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1367420150
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1028104018
Short name T432
Test name
Test status
Simulation time 83306648 ps
CPU time 1.01 seconds
Started Jul 20 04:34:37 PM PDT 24
Finished Jul 20 04:34:41 PM PDT 24
Peak memory 196800 kb
Host smart-15db0ac1-98bb-4bf8-b892-fbfd1f79a08a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028104018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1028104018
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.3245904485
Short name T266
Test name
Test status
Simulation time 28501490 ps
CPU time 0.7 seconds
Started Jul 20 04:34:36 PM PDT 24
Finished Jul 20 04:34:40 PM PDT 24
Peak memory 195244 kb
Host smart-56b06b01-18d2-4e53-abdb-4cdd51e644ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245904485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.3245904485
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.1137983417
Short name T369
Test name
Test status
Simulation time 83299849 ps
CPU time 3.06 seconds
Started Jul 20 04:34:31 PM PDT 24
Finished Jul 20 04:34:36 PM PDT 24
Peak memory 198200 kb
Host smart-dbaa5958-feee-4ab5-82c6-4f9bf2076c01
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137983417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.1137983417
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3408342713
Short name T526
Test name
Test status
Simulation time 107563703 ps
CPU time 1.65 seconds
Started Jul 20 04:34:37 PM PDT 24
Finished Jul 20 04:34:41 PM PDT 24
Peak memory 196188 kb
Host smart-e5d81ca2-b332-43d5-9e7d-284bd1c77371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408342713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3408342713
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1781977667
Short name T221
Test name
Test status
Simulation time 208910058 ps
CPU time 0.67 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:35 PM PDT 24
Peak memory 195136 kb
Host smart-be58678f-de92-4088-8991-5b08edf38b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781977667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1781977667
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.737720142
Short name T509
Test name
Test status
Simulation time 38536277 ps
CPU time 1.25 seconds
Started Jul 20 04:34:34 PM PDT 24
Finished Jul 20 04:34:38 PM PDT 24
Peak memory 196952 kb
Host smart-82409def-b159-4ce9-9c9f-ab25ea1e27ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737720142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.737720142
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3188728328
Short name T282
Test name
Test status
Simulation time 1097094591 ps
CPU time 3.26 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:38 PM PDT 24
Peak memory 198116 kb
Host smart-f5958b44-aacb-479e-9141-ef745c708f40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188728328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3188728328
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2445131252
Short name T146
Test name
Test status
Simulation time 44371417 ps
CPU time 1.35 seconds
Started Jul 20 04:34:30 PM PDT 24
Finished Jul 20 04:34:33 PM PDT 24
Peak memory 196600 kb
Host smart-07d08eef-2b5e-4fe5-870a-6abb9e2e59f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445131252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2445131252
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.4101644465
Short name T292
Test name
Test status
Simulation time 60502370 ps
CPU time 1.09 seconds
Started Jul 20 04:34:40 PM PDT 24
Finished Jul 20 04:34:44 PM PDT 24
Peak memory 195784 kb
Host smart-7fa72933-f1ad-4f3c-9b23-2e290e35d0c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101644465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.4101644465
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1603551511
Short name T412
Test name
Test status
Simulation time 9982097292 ps
CPU time 70.18 seconds
Started Jul 20 04:34:30 PM PDT 24
Finished Jul 20 04:35:41 PM PDT 24
Peak memory 198304 kb
Host smart-e28eea25-1945-4751-bbce-bf6d2aecb4cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603551511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1603551511
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2292574787
Short name T239
Test name
Test status
Simulation time 12168203 ps
CPU time 0.57 seconds
Started Jul 20 04:34:34 PM PDT 24
Finished Jul 20 04:34:38 PM PDT 24
Peak memory 194116 kb
Host smart-d92a9495-6a36-45f5-bc28-37e89f2907c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292574787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2292574787
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.124839731
Short name T123
Test name
Test status
Simulation time 57987084 ps
CPU time 0.62 seconds
Started Jul 20 04:34:37 PM PDT 24
Finished Jul 20 04:34:40 PM PDT 24
Peak memory 194736 kb
Host smart-6ad2ea35-a6a9-48b3-9c9d-af4f89c17fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124839731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.124839731
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.2656600321
Short name T387
Test name
Test status
Simulation time 68253018 ps
CPU time 3.2 seconds
Started Jul 20 04:34:35 PM PDT 24
Finished Jul 20 04:34:41 PM PDT 24
Peak memory 195532 kb
Host smart-9eb59593-1f3c-4aa2-8d45-edfe764d3b56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656600321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.2656600321
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.778041829
Short name T165
Test name
Test status
Simulation time 196590639 ps
CPU time 0.85 seconds
Started Jul 20 04:34:34 PM PDT 24
Finished Jul 20 04:34:38 PM PDT 24
Peak memory 196004 kb
Host smart-8e900df9-c6e7-4d39-a847-9aa8d8f1eb1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778041829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.778041829
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3359366778
Short name T681
Test name
Test status
Simulation time 80179803 ps
CPU time 0.83 seconds
Started Jul 20 04:34:40 PM PDT 24
Finished Jul 20 04:34:44 PM PDT 24
Peak memory 195468 kb
Host smart-cfae9673-2091-4706-9c4c-4d8e3526130b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359366778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3359366778
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2850563293
Short name T300
Test name
Test status
Simulation time 49359351 ps
CPU time 1.98 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:36 PM PDT 24
Peak memory 198164 kb
Host smart-299aebf7-b08f-4e39-a724-8d27d6469d0e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850563293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2850563293
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.261690972
Short name T373
Test name
Test status
Simulation time 100909768 ps
CPU time 2.18 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:37 PM PDT 24
Peak memory 195900 kb
Host smart-c7743790-9ec2-4371-9086-4cded423ae96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261690972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger.
261690972
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2275272085
Short name T276
Test name
Test status
Simulation time 195096737 ps
CPU time 1.11 seconds
Started Jul 20 04:34:33 PM PDT 24
Finished Jul 20 04:34:37 PM PDT 24
Peak memory 196212 kb
Host smart-9feec9e7-0ba4-4876-a6db-8ef98b865dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275272085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2275272085
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1179134620
Short name T403
Test name
Test status
Simulation time 57116867 ps
CPU time 1.09 seconds
Started Jul 20 04:34:34 PM PDT 24
Finished Jul 20 04:34:39 PM PDT 24
Peak memory 196928 kb
Host smart-dbb20bdc-339d-4103-9656-9b348f31641f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179134620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1179134620
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3565377795
Short name T169
Test name
Test status
Simulation time 1471149701 ps
CPU time 4.12 seconds
Started Jul 20 04:34:31 PM PDT 24
Finished Jul 20 04:34:37 PM PDT 24
Peak memory 198128 kb
Host smart-9352d2f6-415d-4320-ad67-cd426ad9d8a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565377795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3565377795
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.3293153461
Short name T582
Test name
Test status
Simulation time 98902068 ps
CPU time 0.99 seconds
Started Jul 20 04:34:36 PM PDT 24
Finished Jul 20 04:34:40 PM PDT 24
Peak memory 196616 kb
Host smart-b585bc21-0d70-47a4-b35d-ac71beefa703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293153461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.3293153461
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.924506935
Short name T195
Test name
Test status
Simulation time 103914269 ps
CPU time 1.38 seconds
Started Jul 20 04:34:31 PM PDT 24
Finished Jul 20 04:34:34 PM PDT 24
Peak memory 197000 kb
Host smart-1045bb58-f7a4-49da-adea-7ed06128f345
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924506935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.924506935
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.796042358
Short name T16
Test name
Test status
Simulation time 1025581368 ps
CPU time 15.63 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:50 PM PDT 24
Peak memory 198168 kb
Host smart-4728e6b4-81f2-4219-afae-071a3b295905
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796042358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.g
pio_stress_all.796042358
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.1754524827
Short name T395
Test name
Test status
Simulation time 13385127 ps
CPU time 0.55 seconds
Started Jul 20 04:34:36 PM PDT 24
Finished Jul 20 04:34:39 PM PDT 24
Peak memory 193628 kb
Host smart-7d820cbf-076a-4408-b52f-95484d7c9470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754524827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.1754524827
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2211980486
Short name T309
Test name
Test status
Simulation time 86698461 ps
CPU time 0.81 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:35 PM PDT 24
Peak memory 195336 kb
Host smart-9fd1a899-f2e9-4c26-ba4f-53d725bd8e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211980486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2211980486
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2837742918
Short name T667
Test name
Test status
Simulation time 2125392759 ps
CPU time 25.57 seconds
Started Jul 20 04:34:31 PM PDT 24
Finished Jul 20 04:34:58 PM PDT 24
Peak memory 196972 kb
Host smart-b49296c0-403c-434b-b916-d7e6f1ad052f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837742918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2837742918
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3076445895
Short name T153
Test name
Test status
Simulation time 289225155 ps
CPU time 0.98 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:35 PM PDT 24
Peak memory 196772 kb
Host smart-7038e079-8996-46c9-87bc-05f0c73bd3be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076445895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3076445895
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.41488294
Short name T600
Test name
Test status
Simulation time 49480386 ps
CPU time 1.26 seconds
Started Jul 20 04:34:30 PM PDT 24
Finished Jul 20 04:34:33 PM PDT 24
Peak memory 198204 kb
Host smart-0993de3a-ce45-432a-9d02-416b852a874f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41488294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.41488294
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.3224170838
Short name T207
Test name
Test status
Simulation time 109898884 ps
CPU time 1.28 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:35 PM PDT 24
Peak memory 196700 kb
Host smart-5909a71b-51ea-4021-b0bf-d3f8d1ea78ea
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224170838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.3224170838
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.2629944089
Short name T295
Test name
Test status
Simulation time 306000481 ps
CPU time 1.72 seconds
Started Jul 20 04:34:36 PM PDT 24
Finished Jul 20 04:34:41 PM PDT 24
Peak memory 196648 kb
Host smart-17da9635-cead-433c-92eb-554a4a10b050
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629944089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.2629944089
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.2421969991
Short name T323
Test name
Test status
Simulation time 81286254 ps
CPU time 1.03 seconds
Started Jul 20 04:34:31 PM PDT 24
Finished Jul 20 04:34:35 PM PDT 24
Peak memory 196168 kb
Host smart-b9395ea9-6997-422e-90b5-af177b402308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421969991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.2421969991
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3192246410
Short name T336
Test name
Test status
Simulation time 40611255 ps
CPU time 0.89 seconds
Started Jul 20 04:34:34 PM PDT 24
Finished Jul 20 04:34:38 PM PDT 24
Peak memory 196100 kb
Host smart-9b3ba1a9-e617-498f-8f21-a440cbda160a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192246410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3192246410
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.376746349
Short name T18
Test name
Test status
Simulation time 530139267 ps
CPU time 5.92 seconds
Started Jul 20 04:34:33 PM PDT 24
Finished Jul 20 04:34:42 PM PDT 24
Peak memory 198156 kb
Host smart-31b90ef5-d1c5-4423-b10a-6831cf1fd367
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376746349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.376746349
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.4121481461
Short name T573
Test name
Test status
Simulation time 93030006 ps
CPU time 1.02 seconds
Started Jul 20 04:34:34 PM PDT 24
Finished Jul 20 04:34:38 PM PDT 24
Peak memory 195756 kb
Host smart-5a8572d4-41b5-40a4-a286-138d8f1cf032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121481461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.4121481461
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.3649478036
Short name T658
Test name
Test status
Simulation time 306269564 ps
CPU time 0.9 seconds
Started Jul 20 04:34:33 PM PDT 24
Finished Jul 20 04:34:37 PM PDT 24
Peak memory 196988 kb
Host smart-a949af2a-23ed-4578-91f8-8f6a0629b28c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649478036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.3649478036
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.1634599191
Short name T431
Test name
Test status
Simulation time 3621198185 ps
CPU time 19.32 seconds
Started Jul 20 04:34:37 PM PDT 24
Finished Jul 20 04:34:59 PM PDT 24
Peak memory 198220 kb
Host smart-fe9101b9-0e64-477f-81d9-f095844ed14f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634599191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.1634599191
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1037195228
Short name T358
Test name
Test status
Simulation time 40267731 ps
CPU time 0.6 seconds
Started Jul 20 04:34:42 PM PDT 24
Finished Jul 20 04:34:45 PM PDT 24
Peak memory 194984 kb
Host smart-0360e38f-4633-4e47-baf4-35a988ec1187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037195228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1037195228
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.996415961
Short name T464
Test name
Test status
Simulation time 29392373 ps
CPU time 0.94 seconds
Started Jul 20 04:34:40 PM PDT 24
Finished Jul 20 04:34:44 PM PDT 24
Peak memory 196620 kb
Host smart-564ef1c7-eb79-4845-a4a3-05713da34b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996415961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.996415961
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1845874262
Short name T552
Test name
Test status
Simulation time 254867329 ps
CPU time 6.28 seconds
Started Jul 20 04:34:39 PM PDT 24
Finished Jul 20 04:34:48 PM PDT 24
Peak memory 196972 kb
Host smart-e30b5600-146f-4380-862e-d6332f687301
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845874262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1845874262
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2616507418
Short name T338
Test name
Test status
Simulation time 60891132 ps
CPU time 1.06 seconds
Started Jul 20 04:34:39 PM PDT 24
Finished Jul 20 04:34:43 PM PDT 24
Peak memory 198072 kb
Host smart-3bf74bc7-40fc-451d-acb6-000a7a21dca5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616507418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2616507418
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.511653735
Short name T663
Test name
Test status
Simulation time 87334203 ps
CPU time 1.4 seconds
Started Jul 20 04:34:39 PM PDT 24
Finished Jul 20 04:34:43 PM PDT 24
Peak memory 197080 kb
Host smart-8c0bfcbd-c894-4e29-8ea6-5d2130723d05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511653735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.511653735
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.3781864679
Short name T677
Test name
Test status
Simulation time 51730215 ps
CPU time 1.96 seconds
Started Jul 20 04:34:32 PM PDT 24
Finished Jul 20 04:34:36 PM PDT 24
Peak memory 198216 kb
Host smart-b79dd259-f567-49ac-a72a-b9deed9338f5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781864679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.3781864679
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3428833712
Short name T340
Test name
Test status
Simulation time 57524624 ps
CPU time 1.36 seconds
Started Jul 20 04:34:39 PM PDT 24
Finished Jul 20 04:34:43 PM PDT 24
Peak memory 196880 kb
Host smart-2524c9ba-b55a-42cd-b212-e99b8b5fa095
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428833712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3428833712
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.4155490110
Short name T532
Test name
Test status
Simulation time 97333046 ps
CPU time 1.06 seconds
Started Jul 20 04:34:36 PM PDT 24
Finished Jul 20 04:34:40 PM PDT 24
Peak memory 196628 kb
Host smart-6f91d1fb-4fc2-45a7-ba28-51262e446c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155490110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.4155490110
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3332421083
Short name T371
Test name
Test status
Simulation time 32638409 ps
CPU time 0.79 seconds
Started Jul 20 04:34:35 PM PDT 24
Finished Jul 20 04:34:39 PM PDT 24
Peak memory 195644 kb
Host smart-f5ab6503-80f6-4833-9279-bc0f4edda08d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332421083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3332421083
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.1668226157
Short name T626
Test name
Test status
Simulation time 271097315 ps
CPU time 4.39 seconds
Started Jul 20 04:34:38 PM PDT 24
Finished Jul 20 04:34:45 PM PDT 24
Peak memory 198148 kb
Host smart-22d7cb19-c5b8-4359-b358-9b1ba0bbf897
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668226157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.1668226157
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.617901477
Short name T621
Test name
Test status
Simulation time 519712248 ps
CPU time 0.95 seconds
Started Jul 20 04:34:37 PM PDT 24
Finished Jul 20 04:34:41 PM PDT 24
Peak memory 195652 kb
Host smart-bab1f85f-7eb9-4f7e-9715-cdc57ead67c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617901477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.617901477
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.576159076
Short name T136
Test name
Test status
Simulation time 244672973 ps
CPU time 1.14 seconds
Started Jul 20 04:34:37 PM PDT 24
Finished Jul 20 04:34:41 PM PDT 24
Peak memory 196556 kb
Host smart-b0db1863-5990-4c30-bdf4-7b3292e535aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576159076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.576159076
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1864744369
Short name T204
Test name
Test status
Simulation time 11725520145 ps
CPU time 157.49 seconds
Started Jul 20 04:34:40 PM PDT 24
Finished Jul 20 04:37:21 PM PDT 24
Peak memory 198168 kb
Host smart-e5ec252a-c7db-4465-a901-21653509fd62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864744369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1864744369
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.3544773989
Short name T43
Test name
Test status
Simulation time 39910274 ps
CPU time 0.57 seconds
Started Jul 20 04:34:39 PM PDT 24
Finished Jul 20 04:34:42 PM PDT 24
Peak memory 194128 kb
Host smart-8eae61fc-c65e-4782-87bf-20953106742a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544773989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.3544773989
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3865102813
Short name T718
Test name
Test status
Simulation time 23676130 ps
CPU time 0.74 seconds
Started Jul 20 04:34:39 PM PDT 24
Finished Jul 20 04:34:42 PM PDT 24
Peak memory 194320 kb
Host smart-fd7cf213-8693-4653-a564-6a8a77b2f06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865102813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3865102813
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2191240840
Short name T411
Test name
Test status
Simulation time 1441990538 ps
CPU time 19.02 seconds
Started Jul 20 04:34:39 PM PDT 24
Finished Jul 20 04:35:01 PM PDT 24
Peak memory 197080 kb
Host smart-718bb16c-dee3-49d6-969f-df778948e364
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191240840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2191240840
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.422169369
Short name T29
Test name
Test status
Simulation time 105276811 ps
CPU time 1.04 seconds
Started Jul 20 04:34:39 PM PDT 24
Finished Jul 20 04:34:42 PM PDT 24
Peak memory 196600 kb
Host smart-5fb8524b-1ae1-4f2d-bf82-d7a25bf97d69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422169369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.422169369
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2590723620
Short name T697
Test name
Test status
Simulation time 818138201 ps
CPU time 1.48 seconds
Started Jul 20 04:34:41 PM PDT 24
Finished Jul 20 04:34:46 PM PDT 24
Peak memory 198156 kb
Host smart-2a456f96-a380-46e0-b42a-9c95cbb29c62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590723620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2590723620
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.1166905443
Short name T515
Test name
Test status
Simulation time 30557921 ps
CPU time 1.26 seconds
Started Jul 20 04:34:44 PM PDT 24
Finished Jul 20 04:34:46 PM PDT 24
Peak memory 196648 kb
Host smart-1e6bedf1-aa28-462e-bc5d-4132a9144e67
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166905443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.1166905443
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.3967022213
Short name T383
Test name
Test status
Simulation time 108109881 ps
CPU time 2.69 seconds
Started Jul 20 04:34:40 PM PDT 24
Finished Jul 20 04:34:46 PM PDT 24
Peak memory 197320 kb
Host smart-fcf4d212-a4d5-4cee-8073-5aaa81298855
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967022213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.3967022213
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3592022180
Short name T233
Test name
Test status
Simulation time 68736253 ps
CPU time 1.03 seconds
Started Jul 20 04:34:40 PM PDT 24
Finished Jul 20 04:34:44 PM PDT 24
Peak memory 196184 kb
Host smart-460d9c36-fe91-4481-a8b3-c090a8985566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592022180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3592022180
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2734823350
Short name T512
Test name
Test status
Simulation time 123122285 ps
CPU time 1.15 seconds
Started Jul 20 04:34:41 PM PDT 24
Finished Jul 20 04:34:46 PM PDT 24
Peak memory 197340 kb
Host smart-2733f849-03e6-43c1-9839-5b2136cefbdc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734823350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2734823350
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.3869074209
Short name T461
Test name
Test status
Simulation time 181326931 ps
CPU time 2.31 seconds
Started Jul 20 04:34:40 PM PDT 24
Finished Jul 20 04:34:45 PM PDT 24
Peak memory 198036 kb
Host smart-51aea48e-28de-43bf-9916-5ad8f2e8e637
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869074209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.3869074209
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.536752737
Short name T156
Test name
Test status
Simulation time 165849452 ps
CPU time 0.9 seconds
Started Jul 20 04:34:38 PM PDT 24
Finished Jul 20 04:34:42 PM PDT 24
Peak memory 196488 kb
Host smart-b25b45d6-9e48-4b2a-89fe-577cbc450dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536752737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.536752737
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3309895509
Short name T491
Test name
Test status
Simulation time 44836000 ps
CPU time 1.25 seconds
Started Jul 20 04:34:41 PM PDT 24
Finished Jul 20 04:34:45 PM PDT 24
Peak memory 196864 kb
Host smart-c0d16e87-d46b-4913-b445-99c4a53616f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309895509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3309895509
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2497124979
Short name T466
Test name
Test status
Simulation time 3089316854 ps
CPU time 69.4 seconds
Started Jul 20 04:34:40 PM PDT 24
Finished Jul 20 04:35:53 PM PDT 24
Peak memory 198308 kb
Host smart-34a0d4a3-52e5-4a35-8425-6a9be9a40487
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497124979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2497124979
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.1732143112
Short name T20
Test name
Test status
Simulation time 32486713 ps
CPU time 0.57 seconds
Started Jul 20 04:34:46 PM PDT 24
Finished Jul 20 04:34:48 PM PDT 24
Peak memory 195044 kb
Host smart-40a309c8-78aa-4048-9572-ad65cc17da02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732143112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.1732143112
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.4245140551
Short name T571
Test name
Test status
Simulation time 28113018 ps
CPU time 0.63 seconds
Started Jul 20 04:34:39 PM PDT 24
Finished Jul 20 04:34:42 PM PDT 24
Peak memory 194128 kb
Host smart-bce3d3b0-8c3c-41c1-b166-73aa22dc4032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245140551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.4245140551
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1907292573
Short name T517
Test name
Test status
Simulation time 3814428037 ps
CPU time 23.98 seconds
Started Jul 20 04:34:37 PM PDT 24
Finished Jul 20 04:35:04 PM PDT 24
Peak memory 196884 kb
Host smart-cfe5a897-e4f7-43dc-910d-0969cff9d18f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907292573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1907292573
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.4240860155
Short name T10
Test name
Test status
Simulation time 407700835 ps
CPU time 1.07 seconds
Started Jul 20 04:34:49 PM PDT 24
Finished Jul 20 04:34:50 PM PDT 24
Peak memory 196728 kb
Host smart-ccec9660-3908-4ad3-bcd6-17d2ffff3d35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240860155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.4240860155
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.4106489457
Short name T719
Test name
Test status
Simulation time 54148351 ps
CPU time 0.7 seconds
Started Jul 20 04:34:43 PM PDT 24
Finished Jul 20 04:34:46 PM PDT 24
Peak memory 194424 kb
Host smart-0dc14f99-1330-4ca9-83ab-e2bcc390e999
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106489457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.4106489457
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1511043439
Short name T185
Test name
Test status
Simulation time 234222968 ps
CPU time 2.18 seconds
Started Jul 20 04:34:38 PM PDT 24
Finished Jul 20 04:34:43 PM PDT 24
Peak memory 198252 kb
Host smart-415cf8b6-9503-468c-b93d-941fbf9f044f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511043439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1511043439
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3611353781
Short name T199
Test name
Test status
Simulation time 87105161 ps
CPU time 0.94 seconds
Started Jul 20 04:34:40 PM PDT 24
Finished Jul 20 04:34:44 PM PDT 24
Peak memory 195548 kb
Host smart-b13bffcf-3889-499c-afd2-ab9f8f8efc4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611353781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3611353781
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.1745618966
Short name T264
Test name
Test status
Simulation time 38419547 ps
CPU time 0.96 seconds
Started Jul 20 04:34:41 PM PDT 24
Finished Jul 20 04:34:45 PM PDT 24
Peak memory 196044 kb
Host smart-8a0f0fab-27e4-481e-b72c-158d5e37b9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745618966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.1745618966
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1961909032
Short name T640
Test name
Test status
Simulation time 24430326 ps
CPU time 0.86 seconds
Started Jul 20 04:34:42 PM PDT 24
Finished Jul 20 04:34:45 PM PDT 24
Peak memory 195996 kb
Host smart-9bba6db7-ea9b-4a30-aa19-aa6feb74985a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961909032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1961909032
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1649513382
Short name T595
Test name
Test status
Simulation time 1021360463 ps
CPU time 4.22 seconds
Started Jul 20 04:34:43 PM PDT 24
Finished Jul 20 04:34:49 PM PDT 24
Peak memory 198072 kb
Host smart-70661c21-50ea-4b02-851f-2c9e9762f51d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649513382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1649513382
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3145181979
Short name T474
Test name
Test status
Simulation time 256190445 ps
CPU time 1.29 seconds
Started Jul 20 04:34:39 PM PDT 24
Finished Jul 20 04:34:43 PM PDT 24
Peak memory 196596 kb
Host smart-e58c0ad1-2817-48d4-b5c2-56c6c4c91853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145181979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3145181979
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.302539512
Short name T223
Test name
Test status
Simulation time 73456740 ps
CPU time 1.23 seconds
Started Jul 20 04:34:40 PM PDT 24
Finished Jul 20 04:34:45 PM PDT 24
Peak memory 195860 kb
Host smart-457c7f45-6ab0-4647-85ac-c067b87d869f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302539512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.302539512
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.173691938
Short name T374
Test name
Test status
Simulation time 9702449996 ps
CPU time 64.01 seconds
Started Jul 20 04:34:50 PM PDT 24
Finished Jul 20 04:35:55 PM PDT 24
Peak memory 198224 kb
Host smart-ffaf5e8a-e2b8-4ddd-836f-d970e4fa1934
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173691938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.g
pio_stress_all.173691938
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2291655010
Short name T389
Test name
Test status
Simulation time 42817992 ps
CPU time 0.63 seconds
Started Jul 20 04:34:53 PM PDT 24
Finished Jul 20 04:34:54 PM PDT 24
Peak memory 194088 kb
Host smart-4e979f80-9a4f-451c-9583-af06ed2115c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291655010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2291655010
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1997273076
Short name T205
Test name
Test status
Simulation time 27738587 ps
CPU time 0.65 seconds
Started Jul 20 04:34:54 PM PDT 24
Finished Jul 20 04:34:55 PM PDT 24
Peak memory 194032 kb
Host smart-e110c933-54b1-4b1d-8019-bf983af4ae57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997273076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1997273076
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.3680968653
Short name T296
Test name
Test status
Simulation time 396655059 ps
CPU time 13.42 seconds
Started Jul 20 04:34:53 PM PDT 24
Finished Jul 20 04:35:07 PM PDT 24
Peak memory 197068 kb
Host smart-dcb83090-694a-480c-a251-c90022b281ec
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680968653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.3680968653
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.241809281
Short name T177
Test name
Test status
Simulation time 141072428 ps
CPU time 0.7 seconds
Started Jul 20 04:34:48 PM PDT 24
Finished Jul 20 04:34:49 PM PDT 24
Peak memory 195472 kb
Host smart-e0ff4f6e-5bc1-470b-b865-61907ca6b040
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241809281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.241809281
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1046085739
Short name T311
Test name
Test status
Simulation time 176638786 ps
CPU time 1.36 seconds
Started Jul 20 04:34:48 PM PDT 24
Finished Jul 20 04:34:50 PM PDT 24
Peak memory 198160 kb
Host smart-ec6fefd5-110f-4345-b8d4-11c7d006e793
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046085739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1046085739
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2416289729
Short name T643
Test name
Test status
Simulation time 50693059 ps
CPU time 2.16 seconds
Started Jul 20 04:34:48 PM PDT 24
Finished Jul 20 04:34:51 PM PDT 24
Peak memory 198048 kb
Host smart-823f79e1-66d7-44e6-8509-942d71b1b271
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416289729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2416289729
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.4178202583
Short name T382
Test name
Test status
Simulation time 427502801 ps
CPU time 3.04 seconds
Started Jul 20 04:34:47 PM PDT 24
Finished Jul 20 04:34:50 PM PDT 24
Peak memory 198212 kb
Host smart-3a0b6c56-fe53-4f91-887d-d93e9db23ac4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178202583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.4178202583
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.2045897869
Short name T647
Test name
Test status
Simulation time 55905436 ps
CPU time 1.23 seconds
Started Jul 20 04:34:48 PM PDT 24
Finished Jul 20 04:34:50 PM PDT 24
Peak memory 197236 kb
Host smart-8e45b029-a819-4f37-b365-e853280ee8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045897869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.2045897869
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3727357984
Short name T523
Test name
Test status
Simulation time 85590924 ps
CPU time 0.75 seconds
Started Jul 20 04:34:54 PM PDT 24
Finished Jul 20 04:34:55 PM PDT 24
Peak memory 195504 kb
Host smart-44e0eea9-4631-43dc-8355-71e62bcd16c3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727357984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3727357984
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.1753385096
Short name T686
Test name
Test status
Simulation time 172137226 ps
CPU time 3.98 seconds
Started Jul 20 04:34:47 PM PDT 24
Finished Jul 20 04:34:51 PM PDT 24
Peak memory 198132 kb
Host smart-39e6060a-912a-40ec-83aa-47dfeaf1aa00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753385096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.1753385096
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1637130795
Short name T458
Test name
Test status
Simulation time 116865822 ps
CPU time 1.04 seconds
Started Jul 20 04:34:49 PM PDT 24
Finished Jul 20 04:34:51 PM PDT 24
Peak memory 196616 kb
Host smart-32fb2474-60b3-4efc-a26e-9c5b3546c703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637130795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1637130795
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.4294699128
Short name T357
Test name
Test status
Simulation time 36715892 ps
CPU time 0.77 seconds
Started Jul 20 04:34:53 PM PDT 24
Finished Jul 20 04:34:55 PM PDT 24
Peak memory 195332 kb
Host smart-28aa3073-e1f4-4f17-bab1-a2ed04383125
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294699128 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.4294699128
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3984402999
Short name T122
Test name
Test status
Simulation time 8801468229 ps
CPU time 123.42 seconds
Started Jul 20 04:34:48 PM PDT 24
Finished Jul 20 04:36:52 PM PDT 24
Peak memory 198288 kb
Host smart-01a2c318-f860-4847-8197-46e53121a683
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984402999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3984402999
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.1339789829
Short name T67
Test name
Test status
Simulation time 45161182865 ps
CPU time 1110.97 seconds
Started Jul 20 04:34:49 PM PDT 24
Finished Jul 20 04:53:21 PM PDT 24
Peak memory 198324 kb
Host smart-2682e95e-cfab-4223-83fe-1f1a7cb22a91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1339789829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.1339789829
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2725015377
Short name T409
Test name
Test status
Simulation time 40823358 ps
CPU time 0.55 seconds
Started Jul 20 04:33:52 PM PDT 24
Finished Jul 20 04:33:53 PM PDT 24
Peak memory 194084 kb
Host smart-0b328dd0-15cc-47d9-8352-2c9aee3e02ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725015377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2725015377
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1267693368
Short name T560
Test name
Test status
Simulation time 93042312 ps
CPU time 0.7 seconds
Started Jul 20 04:33:41 PM PDT 24
Finished Jul 20 04:33:48 PM PDT 24
Peak memory 195400 kb
Host smart-b9e6b5b7-f699-4461-b355-e9b6e66ea033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267693368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1267693368
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1370566195
Short name T217
Test name
Test status
Simulation time 1924595030 ps
CPU time 11.81 seconds
Started Jul 20 04:33:41 PM PDT 24
Finished Jul 20 04:33:59 PM PDT 24
Peak memory 196412 kb
Host smart-1f7d4e5c-8f0e-4647-a8dd-1d99c0ba551b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370566195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1370566195
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2210219900
Short name T542
Test name
Test status
Simulation time 254173274 ps
CPU time 0.92 seconds
Started Jul 20 04:33:43 PM PDT 24
Finished Jul 20 04:33:49 PM PDT 24
Peak memory 197304 kb
Host smart-2f4123bc-6c54-4c01-b56d-9ce37186c97e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210219900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2210219900
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.416451567
Short name T638
Test name
Test status
Simulation time 1425373462 ps
CPU time 1.13 seconds
Started Jul 20 04:33:47 PM PDT 24
Finished Jul 20 04:33:50 PM PDT 24
Peak memory 196180 kb
Host smart-3f2e61ce-8556-4df2-9aa3-d37a651f051a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416451567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.416451567
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.2694093943
Short name T500
Test name
Test status
Simulation time 233982458 ps
CPU time 1.03 seconds
Started Jul 20 04:33:45 PM PDT 24
Finished Jul 20 04:33:50 PM PDT 24
Peak memory 196236 kb
Host smart-b772d40f-1585-42d5-9aa1-9614fbeba4a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694093943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.2694093943
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1821551590
Short name T362
Test name
Test status
Simulation time 312170032 ps
CPU time 1.63 seconds
Started Jul 20 04:33:44 PM PDT 24
Finished Jul 20 04:33:50 PM PDT 24
Peak memory 196232 kb
Host smart-69c8e5cf-e45a-4ec4-ae59-bdfb216dca36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821551590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1821551590
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3636310094
Short name T536
Test name
Test status
Simulation time 81008399 ps
CPU time 1.28 seconds
Started Jul 20 04:33:41 PM PDT 24
Finished Jul 20 04:33:48 PM PDT 24
Peak memory 197032 kb
Host smart-5a17431b-ae1f-45e5-b002-f9a4c1418fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636310094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3636310094
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.2225982047
Short name T242
Test name
Test status
Simulation time 48574466 ps
CPU time 1.12 seconds
Started Jul 20 04:33:34 PM PDT 24
Finished Jul 20 04:33:43 PM PDT 24
Peak memory 196088 kb
Host smart-cbc53c81-f373-4c27-b652-bbc6dcbf8c33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225982047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.2225982047
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1962811800
Short name T32
Test name
Test status
Simulation time 73301163 ps
CPU time 1.45 seconds
Started Jul 20 04:33:39 PM PDT 24
Finished Jul 20 04:33:48 PM PDT 24
Peak memory 198012 kb
Host smart-c7649eb3-4c11-4a3d-947a-b70b5b606bfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962811800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1962811800
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.1874622920
Short name T40
Test name
Test status
Simulation time 201359754 ps
CPU time 0.79 seconds
Started Jul 20 04:33:50 PM PDT 24
Finished Jul 20 04:33:52 PM PDT 24
Peak memory 214136 kb
Host smart-3bb69860-c183-4655-80de-fa6b3844aee7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874622920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.1874622920
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.525450067
Short name T525
Test name
Test status
Simulation time 136586417 ps
CPU time 1.08 seconds
Started Jul 20 04:33:39 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 195756 kb
Host smart-3284c1e9-7f77-4780-9817-ecbe17d10802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525450067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.525450067
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3296605949
Short name T112
Test name
Test status
Simulation time 289925458 ps
CPU time 0.88 seconds
Started Jul 20 04:33:41 PM PDT 24
Finished Jul 20 04:33:48 PM PDT 24
Peak memory 197060 kb
Host smart-03ecfd8b-a083-47b2-b076-b86ef943a4a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296605949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3296605949
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3124233892
Short name T144
Test name
Test status
Simulation time 3231046636 ps
CPU time 83.5 seconds
Started Jul 20 04:33:42 PM PDT 24
Finished Jul 20 04:35:11 PM PDT 24
Peak memory 198284 kb
Host smart-d94da399-6fe1-4ca4-8912-52c2c029a8ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124233892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3124233892
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1902203206
Short name T630
Test name
Test status
Simulation time 13045662 ps
CPU time 0.59 seconds
Started Jul 20 04:34:58 PM PDT 24
Finished Jul 20 04:35:01 PM PDT 24
Peak memory 194712 kb
Host smart-cb686a79-a65c-4196-9d3c-71f5e7922885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902203206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1902203206
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2871157400
Short name T388
Test name
Test status
Simulation time 116927052 ps
CPU time 0.91 seconds
Started Jul 20 04:34:57 PM PDT 24
Finished Jul 20 04:35:00 PM PDT 24
Peak memory 195792 kb
Host smart-d7c3e58b-653e-448e-ae19-95f9aff5a727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871157400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2871157400
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.60750604
Short name T202
Test name
Test status
Simulation time 312547934 ps
CPU time 7.96 seconds
Started Jul 20 04:34:57 PM PDT 24
Finished Jul 20 04:35:07 PM PDT 24
Peak memory 196692 kb
Host smart-30ca1444-340f-4baa-aada-41161b5a47e1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60750604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stress
.60750604
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1857043836
Short name T360
Test name
Test status
Simulation time 71730305 ps
CPU time 0.95 seconds
Started Jul 20 04:34:57 PM PDT 24
Finished Jul 20 04:35:00 PM PDT 24
Peak memory 198012 kb
Host smart-64ffbf7a-172d-488f-8b7b-ce37631996fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857043836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1857043836
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.717647044
Short name T498
Test name
Test status
Simulation time 74084994 ps
CPU time 1.13 seconds
Started Jul 20 04:34:58 PM PDT 24
Finished Jul 20 04:35:01 PM PDT 24
Peak memory 196168 kb
Host smart-83dc0dfb-b269-48ea-aa60-3019f05b1275
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717647044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.717647044
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3736690910
Short name T279
Test name
Test status
Simulation time 428217315 ps
CPU time 1.51 seconds
Started Jul 20 04:34:57 PM PDT 24
Finished Jul 20 04:35:01 PM PDT 24
Peak memory 198472 kb
Host smart-bdea48a4-2ec9-40d4-98f9-5512f400a452
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736690910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3736690910
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.4236370910
Short name T129
Test name
Test status
Simulation time 158722522 ps
CPU time 2.76 seconds
Started Jul 20 04:34:58 PM PDT 24
Finished Jul 20 04:35:03 PM PDT 24
Peak memory 197304 kb
Host smart-833ce1ac-86a9-451d-b8fc-a945304b28a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236370910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.4236370910
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3421576049
Short name T449
Test name
Test status
Simulation time 105311169 ps
CPU time 0.98 seconds
Started Jul 20 04:34:49 PM PDT 24
Finished Jul 20 04:34:51 PM PDT 24
Peak memory 195940 kb
Host smart-d3230c0c-4fa1-44ac-8f80-f3fa5c062723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421576049 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3421576049
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3125856504
Short name T434
Test name
Test status
Simulation time 95519054 ps
CPU time 0.77 seconds
Started Jul 20 04:34:46 PM PDT 24
Finished Jul 20 04:34:48 PM PDT 24
Peak memory 195584 kb
Host smart-8a509eb4-e911-4260-9ce6-99aa1bb0c9c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125856504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3125856504
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.947208733
Short name T586
Test name
Test status
Simulation time 1319249466 ps
CPU time 2.18 seconds
Started Jul 20 04:34:56 PM PDT 24
Finished Jul 20 04:34:59 PM PDT 24
Peak memory 198080 kb
Host smart-3d1fae4a-efae-4c85-8085-de381506a6c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947208733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.947208733
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.857282900
Short name T162
Test name
Test status
Simulation time 139580300 ps
CPU time 0.99 seconds
Started Jul 20 04:34:53 PM PDT 24
Finished Jul 20 04:34:54 PM PDT 24
Peak memory 195768 kb
Host smart-51333254-1bed-4ba4-a00c-fc2a8d6a8921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857282900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.857282900
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.461398992
Short name T128
Test name
Test status
Simulation time 124237874 ps
CPU time 1.17 seconds
Started Jul 20 04:34:52 PM PDT 24
Finished Jul 20 04:34:54 PM PDT 24
Peak memory 195896 kb
Host smart-9df1cc51-378e-4358-9d97-c36d0744e2b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461398992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.461398992
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.438643183
Short name T541
Test name
Test status
Simulation time 23091446622 ps
CPU time 129.01 seconds
Started Jul 20 04:34:57 PM PDT 24
Finished Jul 20 04:37:07 PM PDT 24
Peak memory 198196 kb
Host smart-c9ad5fde-438b-4547-b96c-52f4c779b70e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438643183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.g
pio_stress_all.438643183
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.1627301770
Short name T34
Test name
Test status
Simulation time 291591267545 ps
CPU time 1165.64 seconds
Started Jul 20 04:34:58 PM PDT 24
Finished Jul 20 04:54:26 PM PDT 24
Peak memory 198364 kb
Host smart-7fb5622f-199d-4ea7-a377-34d8a2ed46ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1627301770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.1627301770
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.442652550
Short name T419
Test name
Test status
Simulation time 12501225 ps
CPU time 0.59 seconds
Started Jul 20 04:34:56 PM PDT 24
Finished Jul 20 04:34:58 PM PDT 24
Peak memory 194308 kb
Host smart-5c1271f4-178e-48be-9909-d3ad4e32a243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442652550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.442652550
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.1957110054
Short name T540
Test name
Test status
Simulation time 16868828 ps
CPU time 0.68 seconds
Started Jul 20 04:34:59 PM PDT 24
Finished Jul 20 04:35:03 PM PDT 24
Peak memory 194724 kb
Host smart-2cca06c8-736e-4f21-a4ae-d991af75076c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957110054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.1957110054
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3972616244
Short name T140
Test name
Test status
Simulation time 1240217201 ps
CPU time 15.54 seconds
Started Jul 20 04:34:56 PM PDT 24
Finished Jul 20 04:35:12 PM PDT 24
Peak memory 195652 kb
Host smart-796ca964-09f0-45bb-ac84-8188baf4a67e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972616244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3972616244
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.350255534
Short name T305
Test name
Test status
Simulation time 36250272 ps
CPU time 0.76 seconds
Started Jul 20 04:34:57 PM PDT 24
Finished Jul 20 04:34:58 PM PDT 24
Peak memory 195548 kb
Host smart-a081e0af-bdda-4093-b125-789c8d946541
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350255534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.350255534
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2044952249
Short name T327
Test name
Test status
Simulation time 51004292 ps
CPU time 0.97 seconds
Started Jul 20 04:34:55 PM PDT 24
Finished Jul 20 04:34:57 PM PDT 24
Peak memory 196648 kb
Host smart-a14fb4e6-51d0-46ba-8c7c-e875acbe37e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044952249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2044952249
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.525434927
Short name T141
Test name
Test status
Simulation time 29067817 ps
CPU time 1.32 seconds
Started Jul 20 04:34:59 PM PDT 24
Finished Jul 20 04:35:03 PM PDT 24
Peak memory 196964 kb
Host smart-5f902d66-6c19-497b-86c7-d274d39a62c6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525434927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.525434927
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.3659673840
Short name T483
Test name
Test status
Simulation time 111651058 ps
CPU time 0.9 seconds
Started Jul 20 04:34:58 PM PDT 24
Finished Jul 20 04:35:01 PM PDT 24
Peak memory 195348 kb
Host smart-792dada9-edef-467e-9241-c51495d9787c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659673840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.3659673840
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.553480354
Short name T131
Test name
Test status
Simulation time 22016877 ps
CPU time 0.71 seconds
Started Jul 20 04:34:58 PM PDT 24
Finished Jul 20 04:35:01 PM PDT 24
Peak memory 195524 kb
Host smart-fb5717ab-2b86-4be5-9157-a8d6da6cfa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553480354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.553480354
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1798517185
Short name T174
Test name
Test status
Simulation time 82267177 ps
CPU time 1.15 seconds
Started Jul 20 04:34:54 PM PDT 24
Finished Jul 20 04:34:56 PM PDT 24
Peak memory 195968 kb
Host smart-f98cebca-0058-4584-b535-7f6d4d84b305
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798517185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1798517185
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.563294532
Short name T2
Test name
Test status
Simulation time 255643534 ps
CPU time 3.19 seconds
Started Jul 20 04:35:01 PM PDT 24
Finished Jul 20 04:35:06 PM PDT 24
Peak memory 198128 kb
Host smart-0cd45432-f182-4224-8b2d-63bd912c4b4c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563294532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.563294532
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3217434363
Short name T302
Test name
Test status
Simulation time 229341406 ps
CPU time 1.15 seconds
Started Jul 20 04:34:59 PM PDT 24
Finished Jul 20 04:35:02 PM PDT 24
Peak memory 195892 kb
Host smart-0425a41e-63c6-4021-930b-541495c2a791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217434363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3217434363
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3795336108
Short name T183
Test name
Test status
Simulation time 204538218 ps
CPU time 0.75 seconds
Started Jul 20 04:34:59 PM PDT 24
Finished Jul 20 04:35:02 PM PDT 24
Peak memory 195308 kb
Host smart-fd4afd49-7868-404c-bc90-ce3e63ca0377
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795336108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3795336108
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.1780435888
Short name T142
Test name
Test status
Simulation time 37901877131 ps
CPU time 132.49 seconds
Started Jul 20 04:34:58 PM PDT 24
Finished Jul 20 04:37:13 PM PDT 24
Peak memory 198228 kb
Host smart-677dc17a-17df-4966-bdea-395675f69190
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780435888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.1780435888
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.611339011
Short name T114
Test name
Test status
Simulation time 28986955 ps
CPU time 0.63 seconds
Started Jul 20 04:35:06 PM PDT 24
Finished Jul 20 04:35:07 PM PDT 24
Peak memory 194112 kb
Host smart-16f1f2ee-d56d-4c19-8ef5-2abb8a111261
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611339011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.611339011
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3996079588
Short name T21
Test name
Test status
Simulation time 64209510 ps
CPU time 0.57 seconds
Started Jul 20 04:34:57 PM PDT 24
Finished Jul 20 04:34:58 PM PDT 24
Peak memory 194640 kb
Host smart-67bf3b74-c1fd-4d83-8baf-66a75eb0f66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996079588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3996079588
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.292667410
Short name T528
Test name
Test status
Simulation time 2606566135 ps
CPU time 17.31 seconds
Started Jul 20 04:34:59 PM PDT 24
Finished Jul 20 04:35:19 PM PDT 24
Peak memory 197528 kb
Host smart-462c90ab-45d7-4f73-8d4c-a0c018346af7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292667410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.292667410
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.594968976
Short name T220
Test name
Test status
Simulation time 30497589 ps
CPU time 0.72 seconds
Started Jul 20 04:35:13 PM PDT 24
Finished Jul 20 04:35:15 PM PDT 24
Peak memory 194748 kb
Host smart-2fc51091-436a-4a73-bfab-c5aafcfda79b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594968976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.594968976
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3417307269
Short name T484
Test name
Test status
Simulation time 87751275 ps
CPU time 1.27 seconds
Started Jul 20 04:34:58 PM PDT 24
Finished Jul 20 04:35:01 PM PDT 24
Peak memory 197528 kb
Host smart-26564c4b-ced8-41e0-ac16-f63c40b2e2c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417307269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3417307269
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1894758163
Short name T243
Test name
Test status
Simulation time 79994143 ps
CPU time 1.04 seconds
Started Jul 20 04:34:56 PM PDT 24
Finished Jul 20 04:34:57 PM PDT 24
Peak memory 196404 kb
Host smart-fce38fdd-494c-486d-89f7-b3fb9ac1e659
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894758163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1894758163
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.1172968925
Short name T331
Test name
Test status
Simulation time 50037442 ps
CPU time 1 seconds
Started Jul 20 04:34:57 PM PDT 24
Finished Jul 20 04:35:00 PM PDT 24
Peak memory 196188 kb
Host smart-5a13b5f8-4c10-4bda-9401-b272a23626d7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172968925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.1172968925
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.3451243348
Short name T244
Test name
Test status
Simulation time 25712470 ps
CPU time 0.93 seconds
Started Jul 20 04:34:57 PM PDT 24
Finished Jul 20 04:35:00 PM PDT 24
Peak memory 196032 kb
Host smart-abee6b8c-ff90-4091-befc-f132022b5470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451243348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.3451243348
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.3987569710
Short name T126
Test name
Test status
Simulation time 23374080 ps
CPU time 0.83 seconds
Started Jul 20 04:34:58 PM PDT 24
Finished Jul 20 04:35:01 PM PDT 24
Peak memory 197504 kb
Host smart-f264c0dd-6e47-49d9-baf0-6e1566809645
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987569710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.3987569710
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.4216352120
Short name T5
Test name
Test status
Simulation time 780578628 ps
CPU time 5.07 seconds
Started Jul 20 04:34:58 PM PDT 24
Finished Jul 20 04:35:05 PM PDT 24
Peak memory 198056 kb
Host smart-cb61e655-402b-49fd-bd94-ae939f1f2007
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216352120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.4216352120
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.822776122
Short name T345
Test name
Test status
Simulation time 329319033 ps
CPU time 1.08 seconds
Started Jul 20 04:34:56 PM PDT 24
Finished Jul 20 04:34:58 PM PDT 24
Peak memory 195864 kb
Host smart-46b350a7-4a85-45fd-a2d5-1ff138bebd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822776122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.822776122
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.2096660906
Short name T655
Test name
Test status
Simulation time 38644322 ps
CPU time 1.12 seconds
Started Jul 20 04:34:59 PM PDT 24
Finished Jul 20 04:35:02 PM PDT 24
Peak memory 195660 kb
Host smart-b3a3be31-1ac3-4aab-a6fb-5b59f619a4cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096660906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.2096660906
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.4228917599
Short name T694
Test name
Test status
Simulation time 5835468163 ps
CPU time 132.1 seconds
Started Jul 20 04:35:12 PM PDT 24
Finished Jul 20 04:37:26 PM PDT 24
Peak memory 198184 kb
Host smart-cf867823-272e-4e19-b6ca-f3132d97712f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228917599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.4228917599
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1474852112
Short name T614
Test name
Test status
Simulation time 13444685 ps
CPU time 0.6 seconds
Started Jul 20 04:35:09 PM PDT 24
Finished Jul 20 04:35:11 PM PDT 24
Peak memory 194060 kb
Host smart-91cf0706-b51f-497c-b43a-53ecbafb41ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474852112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1474852112
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.2244509218
Short name T391
Test name
Test status
Simulation time 26582076 ps
CPU time 0.63 seconds
Started Jul 20 04:35:08 PM PDT 24
Finished Jul 20 04:35:10 PM PDT 24
Peak memory 194368 kb
Host smart-8a14d41c-0886-4c1d-9ed6-364968218720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244509218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.2244509218
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.2715114468
Short name T438
Test name
Test status
Simulation time 144488839 ps
CPU time 3.71 seconds
Started Jul 20 04:35:05 PM PDT 24
Finished Jul 20 04:35:10 PM PDT 24
Peak memory 196524 kb
Host smart-529b8e14-70fa-492f-a737-4303ce762b53
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715114468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.2715114468
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.9109999
Short name T9
Test name
Test status
Simulation time 215538144 ps
CPU time 0.92 seconds
Started Jul 20 04:35:11 PM PDT 24
Finished Jul 20 04:35:14 PM PDT 24
Peak memory 196840 kb
Host smart-72bf9601-8923-460f-9ce1-cca6b9221013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9109999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.9109999
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1188278485
Short name T160
Test name
Test status
Simulation time 153203210 ps
CPU time 1.17 seconds
Started Jul 20 04:35:11 PM PDT 24
Finished Jul 20 04:35:15 PM PDT 24
Peak memory 197060 kb
Host smart-9b51632c-77ff-4ca8-8506-a1b422e3fb8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188278485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1188278485
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3680126244
Short name T415
Test name
Test status
Simulation time 179055265 ps
CPU time 1.45 seconds
Started Jul 20 04:35:12 PM PDT 24
Finished Jul 20 04:35:15 PM PDT 24
Peak memory 196976 kb
Host smart-2ad1db34-996d-4244-9e4c-f69d1ffb1799
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680126244 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3680126244
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.2697764500
Short name T222
Test name
Test status
Simulation time 157459762 ps
CPU time 3.33 seconds
Started Jul 20 04:35:10 PM PDT 24
Finished Jul 20 04:35:15 PM PDT 24
Peak memory 197264 kb
Host smart-005a0e06-539a-47f6-b7f6-fbd5f9c05730
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697764500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.2697764500
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1174984082
Short name T215
Test name
Test status
Simulation time 60790034 ps
CPU time 0.79 seconds
Started Jul 20 04:35:10 PM PDT 24
Finished Jul 20 04:35:13 PM PDT 24
Peak memory 195684 kb
Host smart-59e9635f-f048-4e3e-96e9-2cb2d42ce2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174984082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1174984082
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1076205301
Short name T534
Test name
Test status
Simulation time 55918180 ps
CPU time 1.03 seconds
Started Jul 20 04:35:08 PM PDT 24
Finished Jul 20 04:35:10 PM PDT 24
Peak memory 196768 kb
Host smart-4e4fae88-1caa-442e-b8f0-9ad73a925c83
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076205301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1076205301
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.748085831
Short name T680
Test name
Test status
Simulation time 220913628 ps
CPU time 5.78 seconds
Started Jul 20 04:35:08 PM PDT 24
Finished Jul 20 04:35:15 PM PDT 24
Peak memory 198168 kb
Host smart-66a46388-1ef1-44f2-8b2d-6b7e256a87d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748085831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.748085831
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3639965134
Short name T151
Test name
Test status
Simulation time 23387379 ps
CPU time 0.8 seconds
Started Jul 20 04:35:07 PM PDT 24
Finished Jul 20 04:35:08 PM PDT 24
Peak memory 195884 kb
Host smart-f7961cbd-20b9-4175-9c9b-0e367d770910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639965134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3639965134
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.3601378165
Short name T443
Test name
Test status
Simulation time 63146814 ps
CPU time 1.17 seconds
Started Jul 20 04:35:06 PM PDT 24
Finished Jul 20 04:35:08 PM PDT 24
Peak memory 195936 kb
Host smart-9edf397f-4aa9-4ddb-911a-75ac7f972da7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601378165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.3601378165
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.734272456
Short name T8
Test name
Test status
Simulation time 45518874421 ps
CPU time 98.64 seconds
Started Jul 20 04:35:11 PM PDT 24
Finished Jul 20 04:36:52 PM PDT 24
Peak memory 198192 kb
Host smart-e93facf8-3d78-4276-9f4f-1aca95c17584
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734272456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.734272456
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.2403785446
Short name T291
Test name
Test status
Simulation time 20262227 ps
CPU time 0.57 seconds
Started Jul 20 04:35:09 PM PDT 24
Finished Jul 20 04:35:11 PM PDT 24
Peak memory 194036 kb
Host smart-44b4acd1-3718-4178-abba-5393446a781f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403785446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.2403785446
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.558866550
Short name T705
Test name
Test status
Simulation time 132436394 ps
CPU time 0.75 seconds
Started Jul 20 04:35:08 PM PDT 24
Finished Jul 20 04:35:10 PM PDT 24
Peak memory 194224 kb
Host smart-9918dc52-9aa5-41bb-a436-77b6be1b089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558866550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.558866550
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.3470300898
Short name T26
Test name
Test status
Simulation time 165428952 ps
CPU time 4.78 seconds
Started Jul 20 04:35:11 PM PDT 24
Finished Jul 20 04:35:18 PM PDT 24
Peak memory 196124 kb
Host smart-1b7edb69-cc95-40c3-8e68-210bea2b6fc1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470300898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.3470300898
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.4249570438
Short name T445
Test name
Test status
Simulation time 64959153 ps
CPU time 0.61 seconds
Started Jul 20 04:35:10 PM PDT 24
Finished Jul 20 04:35:12 PM PDT 24
Peak memory 193972 kb
Host smart-b39e4509-5e35-4789-8c15-6d3ec64a2278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249570438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.4249570438
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1721069239
Short name T703
Test name
Test status
Simulation time 27043145 ps
CPU time 0.84 seconds
Started Jul 20 04:35:10 PM PDT 24
Finished Jul 20 04:35:13 PM PDT 24
Peak memory 196596 kb
Host smart-548bf636-f027-47a0-9ec7-d6e004433314
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721069239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1721069239
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3386972173
Short name T567
Test name
Test status
Simulation time 352572901 ps
CPU time 2.66 seconds
Started Jul 20 04:35:07 PM PDT 24
Finished Jul 20 04:35:11 PM PDT 24
Peak memory 198304 kb
Host smart-16812ca3-b3cb-42af-97b0-6397a5c0d2d2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386972173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3386972173
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.363336695
Short name T469
Test name
Test status
Simulation time 460541139 ps
CPU time 2.49 seconds
Started Jul 20 04:35:08 PM PDT 24
Finished Jul 20 04:35:12 PM PDT 24
Peak memory 197108 kb
Host smart-cd61f816-8099-493c-afe0-c44a95c60cd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363336695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
363336695
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.3289864546
Short name T519
Test name
Test status
Simulation time 205358901 ps
CPU time 1.16 seconds
Started Jul 20 04:35:07 PM PDT 24
Finished Jul 20 04:35:09 PM PDT 24
Peak memory 197136 kb
Host smart-65136ac0-5d2d-4fc3-92bb-05a4f1e9c014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289864546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.3289864546
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.512138499
Short name T546
Test name
Test status
Simulation time 41528721 ps
CPU time 0.67 seconds
Started Jul 20 04:35:07 PM PDT 24
Finished Jul 20 04:35:09 PM PDT 24
Peak memory 195180 kb
Host smart-bf0f5209-4f7e-423d-b3fc-9b0434ceb4ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512138499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.512138499
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.2228841204
Short name T408
Test name
Test status
Simulation time 374614059 ps
CPU time 4.83 seconds
Started Jul 20 04:35:11 PM PDT 24
Finished Jul 20 04:35:18 PM PDT 24
Peak memory 198104 kb
Host smart-5ceba7c4-37b8-4a79-91e0-1202583d1306
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228841204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.2228841204
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2588711060
Short name T499
Test name
Test status
Simulation time 69911717 ps
CPU time 0.77 seconds
Started Jul 20 04:35:11 PM PDT 24
Finished Jul 20 04:35:14 PM PDT 24
Peak memory 195424 kb
Host smart-c10f29e7-7eaf-4b88-a9d1-dcfcb299fa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588711060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2588711060
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.560221123
Short name T277
Test name
Test status
Simulation time 68865083 ps
CPU time 1.2 seconds
Started Jul 20 04:35:08 PM PDT 24
Finished Jul 20 04:35:11 PM PDT 24
Peak memory 195712 kb
Host smart-0b2b1aed-121c-43c7-ae94-8f05a3624620
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560221123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.560221123
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.4279534440
Short name T189
Test name
Test status
Simulation time 43359133742 ps
CPU time 218.88 seconds
Started Jul 20 04:35:10 PM PDT 24
Finished Jul 20 04:38:51 PM PDT 24
Peak memory 198216 kb
Host smart-f20be5fb-1ec5-41bf-afa2-b600952b24d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279534440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.4279534440
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1507846618
Short name T485
Test name
Test status
Simulation time 45382518 ps
CPU time 0.58 seconds
Started Jul 20 04:35:09 PM PDT 24
Finished Jul 20 04:35:11 PM PDT 24
Peak memory 194984 kb
Host smart-6aa78f96-102c-42ed-bc63-cbf51413884e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507846618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1507846618
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.3751119746
Short name T312
Test name
Test status
Simulation time 95165754 ps
CPU time 0.86 seconds
Started Jul 20 04:35:09 PM PDT 24
Finished Jul 20 04:35:12 PM PDT 24
Peak memory 196520 kb
Host smart-b916ac96-e359-46ef-a6e7-44a70fddb636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751119746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.3751119746
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1500525079
Short name T692
Test name
Test status
Simulation time 1349364064 ps
CPU time 23.33 seconds
Started Jul 20 04:35:08 PM PDT 24
Finished Jul 20 04:35:32 PM PDT 24
Peak memory 198112 kb
Host smart-bf76aa4c-35f8-4758-8126-7de1e737077e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500525079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1500525079
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.680689203
Short name T601
Test name
Test status
Simulation time 427057821 ps
CPU time 1.16 seconds
Started Jul 20 04:35:07 PM PDT 24
Finished Jul 20 04:35:09 PM PDT 24
Peak memory 198048 kb
Host smart-9d4bce35-5734-4a25-9b44-02be3431b2b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680689203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.680689203
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2068181040
Short name T317
Test name
Test status
Simulation time 39436391 ps
CPU time 0.94 seconds
Started Jul 20 04:35:08 PM PDT 24
Finished Jul 20 04:35:11 PM PDT 24
Peak memory 196472 kb
Host smart-95bddec9-573d-4af8-b6b4-eb47ee1b3c63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068181040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2068181040
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3961380552
Short name T496
Test name
Test status
Simulation time 115710556 ps
CPU time 2.23 seconds
Started Jul 20 04:35:10 PM PDT 24
Finished Jul 20 04:35:14 PM PDT 24
Peak memory 198120 kb
Host smart-2e8fcd1a-ae7e-4385-b157-bf0b7e1bafdf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961380552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3961380552
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.509624087
Short name T641
Test name
Test status
Simulation time 113509684 ps
CPU time 2.29 seconds
Started Jul 20 04:35:10 PM PDT 24
Finished Jul 20 04:35:15 PM PDT 24
Peak memory 198140 kb
Host smart-9a7f1a7f-e79f-45ef-b379-bbd013de682a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509624087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger.
509624087
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.4294247722
Short name T69
Test name
Test status
Simulation time 165126853 ps
CPU time 1.26 seconds
Started Jul 20 04:35:07 PM PDT 24
Finished Jul 20 04:35:10 PM PDT 24
Peak memory 197040 kb
Host smart-9dfa2342-1db6-47ad-9a87-d648ec2c95a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294247722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.4294247722
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1437348323
Short name T557
Test name
Test status
Simulation time 105307143 ps
CPU time 1.08 seconds
Started Jul 20 04:35:11 PM PDT 24
Finished Jul 20 04:35:14 PM PDT 24
Peak memory 195948 kb
Host smart-94710172-23da-412a-9a57-31e3f750affa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437348323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1437348323
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.1376488776
Short name T133
Test name
Test status
Simulation time 30709434 ps
CPU time 1.41 seconds
Started Jul 20 04:35:11 PM PDT 24
Finished Jul 20 04:35:14 PM PDT 24
Peak memory 198048 kb
Host smart-8e3c9cbf-354d-4912-94f8-ee1f668eb944
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376488776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.1376488776
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.3052321373
Short name T226
Test name
Test status
Simulation time 300133382 ps
CPU time 0.8 seconds
Started Jul 20 04:35:08 PM PDT 24
Finished Jul 20 04:35:09 PM PDT 24
Peak memory 195216 kb
Host smart-6d2e1804-9f0f-44dd-bc88-5810f36e8d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052321373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.3052321373
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.4271915340
Short name T579
Test name
Test status
Simulation time 122469919 ps
CPU time 1.11 seconds
Started Jul 20 04:35:09 PM PDT 24
Finished Jul 20 04:35:11 PM PDT 24
Peak memory 195664 kb
Host smart-d2e470ee-c1fc-44f9-ab94-1f15ae9a3aae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271915340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.4271915340
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2289988269
Short name T439
Test name
Test status
Simulation time 8345447353 ps
CPU time 237.36 seconds
Started Jul 20 04:35:07 PM PDT 24
Finished Jul 20 04:39:05 PM PDT 24
Peak memory 198248 kb
Host smart-2086fd4d-80d0-4d07-94d1-e13af082c745
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289988269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2289988269
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.2711107818
Short name T105
Test name
Test status
Simulation time 64710138713 ps
CPU time 1573.65 seconds
Started Jul 20 04:35:09 PM PDT 24
Finished Jul 20 05:01:24 PM PDT 24
Peak memory 198292 kb
Host smart-a95411c8-452d-4386-8120-b4a005e49f04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2711107818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.2711107818
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2992930392
Short name T425
Test name
Test status
Simulation time 28371076 ps
CPU time 0.58 seconds
Started Jul 20 04:35:22 PM PDT 24
Finished Jul 20 04:35:24 PM PDT 24
Peak memory 194800 kb
Host smart-b33767db-6158-4474-8d2d-4e3bed37c621
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992930392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2992930392
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.1697373296
Short name T135
Test name
Test status
Simulation time 26733593 ps
CPU time 0.77 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:26 PM PDT 24
Peak memory 195348 kb
Host smart-2301e615-39ad-43ec-8215-471a033a7881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697373296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.1697373296
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.2491079146
Short name T639
Test name
Test status
Simulation time 150490221 ps
CPU time 5.19 seconds
Started Jul 20 04:35:18 PM PDT 24
Finished Jul 20 04:35:26 PM PDT 24
Peak memory 197040 kb
Host smart-1168bba3-1124-4a4f-aae6-baf3507924b1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491079146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.2491079146
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.56949188
Short name T175
Test name
Test status
Simulation time 279230760 ps
CPU time 0.68 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:26 PM PDT 24
Peak memory 195344 kb
Host smart-95662176-8ddd-4946-856c-6ad666fb5832
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56949188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.56949188
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.211487933
Short name T551
Test name
Test status
Simulation time 53454071 ps
CPU time 1.01 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:28 PM PDT 24
Peak memory 196168 kb
Host smart-50a49380-7260-43bf-9e51-68ea46b1d005
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211487933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.211487933
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3573968506
Short name T361
Test name
Test status
Simulation time 181935524 ps
CPU time 3.54 seconds
Started Jul 20 04:35:19 PM PDT 24
Finished Jul 20 04:35:24 PM PDT 24
Peak memory 198212 kb
Host smart-677a5813-a5a6-4524-90e9-46be68f3dbc2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573968506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3573968506
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.2037537946
Short name T406
Test name
Test status
Simulation time 442983097 ps
CPU time 2.99 seconds
Started Jul 20 04:35:15 PM PDT 24
Finished Jul 20 04:35:19 PM PDT 24
Peak memory 198200 kb
Host smart-c317331f-cbd2-4a42-9295-0d38f71af453
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037537946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.2037537946
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2538659439
Short name T506
Test name
Test status
Simulation time 26090769 ps
CPU time 0.98 seconds
Started Jul 20 04:35:15 PM PDT 24
Finished Jul 20 04:35:16 PM PDT 24
Peak memory 196828 kb
Host smart-e42b9fae-a899-45a8-8121-d2eb27951e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538659439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2538659439
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2267141621
Short name T208
Test name
Test status
Simulation time 97378456 ps
CPU time 0.71 seconds
Started Jul 20 04:35:19 PM PDT 24
Finished Jul 20 04:35:22 PM PDT 24
Peak memory 195532 kb
Host smart-3e3981c7-e335-435b-8c6d-20e3c3b2867c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267141621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2267141621
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.3297247492
Short name T661
Test name
Test status
Simulation time 272081789 ps
CPU time 1.26 seconds
Started Jul 20 04:35:16 PM PDT 24
Finished Jul 20 04:35:19 PM PDT 24
Peak memory 198068 kb
Host smart-584dafb4-49e1-4c01-bfa6-e3a22f5e4e4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297247492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.3297247492
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.3092198473
Short name T426
Test name
Test status
Simulation time 153681570 ps
CPU time 0.91 seconds
Started Jul 20 04:35:11 PM PDT 24
Finished Jul 20 04:35:14 PM PDT 24
Peak memory 196436 kb
Host smart-cea22a4f-a489-4675-aef6-2d3949dcd7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092198473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.3092198473
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.3845770178
Short name T270
Test name
Test status
Simulation time 159869840 ps
CPU time 1.16 seconds
Started Jul 20 04:35:11 PM PDT 24
Finished Jul 20 04:35:14 PM PDT 24
Peak memory 195980 kb
Host smart-41573c2d-14f1-485a-9085-327dd98719b2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845770178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.3845770178
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1582048312
Short name T4
Test name
Test status
Simulation time 12818444745 ps
CPU time 134.29 seconds
Started Jul 20 04:35:22 PM PDT 24
Finished Jul 20 04:37:38 PM PDT 24
Peak memory 198032 kb
Host smart-69f32b01-237f-4e72-bd42-6effca56b255
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582048312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1582048312
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.741391526
Short name T376
Test name
Test status
Simulation time 175172361460 ps
CPU time 297.45 seconds
Started Jul 20 04:35:17 PM PDT 24
Finished Jul 20 04:40:15 PM PDT 24
Peak memory 198260 kb
Host smart-18f8a143-ef11-4031-b156-ff7ed4ebd3ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=741391526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.741391526
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.1364962765
Short name T550
Test name
Test status
Simulation time 12923726 ps
CPU time 0.57 seconds
Started Jul 20 04:35:20 PM PDT 24
Finished Jul 20 04:35:23 PM PDT 24
Peak memory 194076 kb
Host smart-99a59ac8-4486-4606-9ff9-a02a6d4a3e08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364962765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.1364962765
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.123352868
Short name T490
Test name
Test status
Simulation time 72200064 ps
CPU time 0.74 seconds
Started Jul 20 04:35:18 PM PDT 24
Finished Jul 20 04:35:21 PM PDT 24
Peak memory 195284 kb
Host smart-249679e1-fa2f-411c-bf51-616f79180c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123352868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.123352868
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.66445446
Short name T254
Test name
Test status
Simulation time 504797570 ps
CPU time 7.62 seconds
Started Jul 20 04:35:18 PM PDT 24
Finished Jul 20 04:35:28 PM PDT 24
Peak memory 197148 kb
Host smart-d500c220-33cc-4806-bbf3-101af4a20433
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66445446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stress
.66445446
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3169188611
Short name T166
Test name
Test status
Simulation time 35047053 ps
CPU time 0.76 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:26 PM PDT 24
Peak memory 195900 kb
Host smart-09ec60a9-0bc8-42f5-8a71-61dc5c086f5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169188611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3169188611
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1633262904
Short name T271
Test name
Test status
Simulation time 50459289 ps
CPU time 1.38 seconds
Started Jul 20 04:35:17 PM PDT 24
Finished Jul 20 04:35:20 PM PDT 24
Peak memory 198184 kb
Host smart-418c3d63-c9ca-4a69-8ffe-959c4d599a1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633262904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1633262904
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1954212505
Short name T482
Test name
Test status
Simulation time 66150825 ps
CPU time 2.53 seconds
Started Jul 20 04:35:16 PM PDT 24
Finished Jul 20 04:35:20 PM PDT 24
Peak memory 197956 kb
Host smart-e75060ed-e10b-45f1-9312-3c0e50b99f5c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954212505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1954212505
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.3486351748
Short name T676
Test name
Test status
Simulation time 288308004 ps
CPU time 1.51 seconds
Started Jul 20 04:35:18 PM PDT 24
Finished Jul 20 04:35:21 PM PDT 24
Peak memory 195944 kb
Host smart-8be60adc-769f-4d83-9c75-f570aeb382d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486351748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.3486351748
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2278211335
Short name T73
Test name
Test status
Simulation time 94204716 ps
CPU time 0.96 seconds
Started Jul 20 04:35:15 PM PDT 24
Finished Jul 20 04:35:17 PM PDT 24
Peak memory 196380 kb
Host smart-c7014038-66cb-4070-85f2-66b086d16fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278211335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2278211335
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.3104154249
Short name T637
Test name
Test status
Simulation time 32196880 ps
CPU time 0.91 seconds
Started Jul 20 04:35:18 PM PDT 24
Finished Jul 20 04:35:21 PM PDT 24
Peak memory 195840 kb
Host smart-175d9293-a119-4598-9018-3786cddd27c1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104154249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.3104154249
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2206054570
Short name T508
Test name
Test status
Simulation time 305879049 ps
CPU time 4.99 seconds
Started Jul 20 04:35:23 PM PDT 24
Finished Jul 20 04:35:30 PM PDT 24
Peak memory 198164 kb
Host smart-d304768e-8b1b-4480-b865-310631e5a749
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206054570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2206054570
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.3733585212
Short name T366
Test name
Test status
Simulation time 157857303 ps
CPU time 1.2 seconds
Started Jul 20 04:35:19 PM PDT 24
Finished Jul 20 04:35:22 PM PDT 24
Peak memory 198040 kb
Host smart-0552c4db-5319-458b-8b67-8d0ba4fb1279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733585212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.3733585212
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.1645122643
Short name T179
Test name
Test status
Simulation time 119341188 ps
CPU time 1.03 seconds
Started Jul 20 04:35:17 PM PDT 24
Finished Jul 20 04:35:19 PM PDT 24
Peak memory 196552 kb
Host smart-4e0f7858-8225-46b2-ba7a-f95c15004f3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645122643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.1645122643
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.780896380
Short name T435
Test name
Test status
Simulation time 30491734027 ps
CPU time 195.62 seconds
Started Jul 20 04:35:17 PM PDT 24
Finished Jul 20 04:38:34 PM PDT 24
Peak memory 198172 kb
Host smart-dfd16a6d-b2e5-4e07-925d-ea95bf64ec5c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780896380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.780896380
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.616570498
Short name T645
Test name
Test status
Simulation time 441654456558 ps
CPU time 1230.11 seconds
Started Jul 20 04:35:19 PM PDT 24
Finished Jul 20 04:55:51 PM PDT 24
Peak memory 198400 kb
Host smart-1f75db07-a2d3-4fcb-b879-03a5ccdb3283
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=616570498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.616570498
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3817348288
Short name T533
Test name
Test status
Simulation time 31500419 ps
CPU time 0.55 seconds
Started Jul 20 04:35:17 PM PDT 24
Finished Jul 20 04:35:19 PM PDT 24
Peak memory 194808 kb
Host smart-2a2b84a7-2ba1-4af5-89ce-4edcc4759149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817348288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3817348288
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.2673673562
Short name T375
Test name
Test status
Simulation time 115207315 ps
CPU time 0.76 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:26 PM PDT 24
Peak memory 195344 kb
Host smart-cd53e1b8-9143-44c4-a3f4-fdc1182bb140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673673562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.2673673562
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.767748670
Short name T407
Test name
Test status
Simulation time 808447586 ps
CPU time 21.75 seconds
Started Jul 20 04:35:16 PM PDT 24
Finished Jul 20 04:35:39 PM PDT 24
Peak memory 196328 kb
Host smart-d02eb169-5f4a-4572-bb0c-32725ea00826
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767748670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stres
s.767748670
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.1365985014
Short name T646
Test name
Test status
Simulation time 98134554 ps
CPU time 0.62 seconds
Started Jul 20 04:35:20 PM PDT 24
Finished Jul 20 04:35:23 PM PDT 24
Peak memory 194640 kb
Host smart-5f4698a9-8cc3-4de7-b1ae-d0a96407a1c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365985014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1365985014
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2831659215
Short name T287
Test name
Test status
Simulation time 27606976 ps
CPU time 0.74 seconds
Started Jul 20 04:35:22 PM PDT 24
Finished Jul 20 04:35:25 PM PDT 24
Peak memory 196180 kb
Host smart-7374e75f-937b-43d4-b728-9b6fd9fb9752
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831659215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2831659215
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.116509362
Short name T691
Test name
Test status
Simulation time 91917743 ps
CPU time 3.71 seconds
Started Jul 20 04:35:16 PM PDT 24
Finished Jul 20 04:35:21 PM PDT 24
Peak memory 198104 kb
Host smart-51bdc7d1-72f8-4d5b-8c41-93f17654ee66
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116509362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.116509362
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1830790421
Short name T216
Test name
Test status
Simulation time 402177621 ps
CPU time 3.06 seconds
Started Jul 20 04:35:18 PM PDT 24
Finished Jul 20 04:35:23 PM PDT 24
Peak memory 196964 kb
Host smart-faff2765-f311-4332-ba46-30bd749a98ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830790421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1830790421
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3091216725
Short name T310
Test name
Test status
Simulation time 38676003 ps
CPU time 0.66 seconds
Started Jul 20 04:35:21 PM PDT 24
Finished Jul 20 04:35:24 PM PDT 24
Peak memory 195120 kb
Host smart-aff86a9a-703b-426d-a99a-382765f2975b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091216725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3091216725
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1681219091
Short name T211
Test name
Test status
Simulation time 39970846 ps
CPU time 0.87 seconds
Started Jul 20 04:35:25 PM PDT 24
Finished Jul 20 04:35:28 PM PDT 24
Peak memory 196008 kb
Host smart-e224fe27-a32d-422e-b84c-e70e0680133b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681219091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1681219091
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3688034715
Short name T6
Test name
Test status
Simulation time 306805466 ps
CPU time 3.72 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:30 PM PDT 24
Peak memory 197672 kb
Host smart-71c411c9-61f5-4be6-ad31-14a6c2f66f65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688034715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3688034715
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.458432650
Short name T583
Test name
Test status
Simulation time 91205673 ps
CPU time 0.97 seconds
Started Jul 20 04:35:19 PM PDT 24
Finished Jul 20 04:35:22 PM PDT 24
Peak memory 196432 kb
Host smart-1018df12-a24a-4c4a-9eb7-a9b1a8d54ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458432650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.458432650
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.375585041
Short name T608
Test name
Test status
Simulation time 28811502 ps
CPU time 0.94 seconds
Started Jul 20 04:35:14 PM PDT 24
Finished Jul 20 04:35:16 PM PDT 24
Peak memory 196088 kb
Host smart-9e2bd64a-18d7-475d-8261-1fa5b4aa6e2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375585041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.375585041
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.3748407229
Short name T516
Test name
Test status
Simulation time 34248993617 ps
CPU time 109.95 seconds
Started Jul 20 04:35:16 PM PDT 24
Finished Jul 20 04:37:07 PM PDT 24
Peak memory 198248 kb
Host smart-ee186c9b-5ad5-4778-927e-43e7608fb0a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748407229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.3748407229
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3778460851
Short name T210
Test name
Test status
Simulation time 14129595 ps
CPU time 0.56 seconds
Started Jul 20 04:35:19 PM PDT 24
Finished Jul 20 04:35:22 PM PDT 24
Peak memory 194272 kb
Host smart-1cd33718-ff53-4cae-84c1-8889361ff44e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778460851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3778460851
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2990268230
Short name T672
Test name
Test status
Simulation time 15685049 ps
CPU time 0.62 seconds
Started Jul 20 04:35:16 PM PDT 24
Finished Jul 20 04:35:18 PM PDT 24
Peak memory 194816 kb
Host smart-1bf3fee7-80d1-4047-ae0d-5b87e17c42b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990268230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2990268230
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.948627321
Short name T539
Test name
Test status
Simulation time 549982719 ps
CPU time 3.11 seconds
Started Jul 20 04:35:19 PM PDT 24
Finished Jul 20 04:35:24 PM PDT 24
Peak memory 195836 kb
Host smart-ff4ed59a-cbf4-4955-91db-cc83ad9ccbe6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948627321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.948627321
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.3634484774
Short name T684
Test name
Test status
Simulation time 59560337 ps
CPU time 0.87 seconds
Started Jul 20 04:35:16 PM PDT 24
Finished Jul 20 04:35:18 PM PDT 24
Peak memory 196796 kb
Host smart-89eecd49-e4e5-4687-bc3f-5615c3b8b0c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634484774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.3634484774
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1278732477
Short name T15
Test name
Test status
Simulation time 201385209 ps
CPU time 1.38 seconds
Started Jul 20 04:35:14 PM PDT 24
Finished Jul 20 04:35:16 PM PDT 24
Peak memory 198192 kb
Host smart-f3cda0a5-869a-4e1a-8161-569ff2c6d781
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278732477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1278732477
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1210912331
Short name T699
Test name
Test status
Simulation time 147688247 ps
CPU time 3.52 seconds
Started Jul 20 04:35:18 PM PDT 24
Finished Jul 20 04:35:23 PM PDT 24
Peak memory 198144 kb
Host smart-b196e91a-bbbf-4d3f-8585-e5054f58a1fd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210912331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1210912331
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1849737699
Short name T127
Test name
Test status
Simulation time 575756223 ps
CPU time 3.17 seconds
Started Jul 20 04:35:16 PM PDT 24
Finished Jul 20 04:35:20 PM PDT 24
Peak memory 195936 kb
Host smart-1219ee93-199d-4b5c-adcf-5c0d76a66a0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849737699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1849737699
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1064544215
Short name T687
Test name
Test status
Simulation time 127918495 ps
CPU time 1.15 seconds
Started Jul 20 04:35:20 PM PDT 24
Finished Jul 20 04:35:23 PM PDT 24
Peak memory 197172 kb
Host smart-b6e121de-36b4-42e2-8b38-cd047fd86e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064544215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1064544215
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.905128390
Short name T229
Test name
Test status
Simulation time 101798286 ps
CPU time 0.61 seconds
Started Jul 20 04:35:19 PM PDT 24
Finished Jul 20 04:35:22 PM PDT 24
Peak memory 194456 kb
Host smart-255b6a31-d310-48a5-85c9-65d8395e4511
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905128390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullup
_pulldown.905128390
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1582668449
Short name T547
Test name
Test status
Simulation time 391456429 ps
CPU time 6.37 seconds
Started Jul 20 04:35:20 PM PDT 24
Finished Jul 20 04:35:29 PM PDT 24
Peak memory 198040 kb
Host smart-d831f4fe-54b6-4403-9cef-5fe3f5c6aaeb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582668449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1582668449
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2026047025
Short name T171
Test name
Test status
Simulation time 41811303 ps
CPU time 0.76 seconds
Started Jul 20 04:35:17 PM PDT 24
Finished Jul 20 04:35:19 PM PDT 24
Peak memory 195292 kb
Host smart-a9d67961-b8ec-436a-a774-5dc467fbdcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026047025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2026047025
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1282897370
Short name T212
Test name
Test status
Simulation time 295864787 ps
CPU time 1.34 seconds
Started Jul 20 04:35:19 PM PDT 24
Finished Jul 20 04:35:23 PM PDT 24
Peak memory 196804 kb
Host smart-fe72e8df-e384-44fe-8732-cb86cd659d3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282897370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1282897370
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.3390871780
Short name T230
Test name
Test status
Simulation time 2781103409 ps
CPU time 75.99 seconds
Started Jul 20 04:35:16 PM PDT 24
Finished Jul 20 04:36:33 PM PDT 24
Peak memory 198212 kb
Host smart-1e3a4cf8-7e57-4087-a150-9892a43a41fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390871780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.3390871780
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.3616302891
Short name T113
Test name
Test status
Simulation time 68115511 ps
CPU time 0.55 seconds
Started Jul 20 04:33:53 PM PDT 24
Finished Jul 20 04:33:54 PM PDT 24
Peak memory 194780 kb
Host smart-7bfa878b-c7ad-4180-bc7a-e9eb17aa8a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616302891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.3616302891
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1690881570
Short name T695
Test name
Test status
Simulation time 106153032 ps
CPU time 0.86 seconds
Started Jul 20 04:33:51 PM PDT 24
Finished Jul 20 04:33:52 PM PDT 24
Peak memory 196640 kb
Host smart-b86a4dce-0925-4cfd-8dd9-647d9759754e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690881570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1690881570
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.2027051399
Short name T25
Test name
Test status
Simulation time 413676435 ps
CPU time 11.16 seconds
Started Jul 20 04:33:47 PM PDT 24
Finished Jul 20 04:34:01 PM PDT 24
Peak memory 195652 kb
Host smart-68decbb7-7d5d-43d7-b8c6-5a237d81ba8c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027051399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.2027051399
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.4077295480
Short name T594
Test name
Test status
Simulation time 107338879 ps
CPU time 1.02 seconds
Started Jul 20 04:33:51 PM PDT 24
Finished Jul 20 04:33:52 PM PDT 24
Peak memory 196692 kb
Host smart-f58dfc97-c95c-4ccb-9783-90b6b8ad2f5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077295480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.4077295480
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.279571658
Short name T448
Test name
Test status
Simulation time 26194450 ps
CPU time 0.85 seconds
Started Jul 20 04:33:44 PM PDT 24
Finished Jul 20 04:33:49 PM PDT 24
Peak memory 196692 kb
Host smart-cb455488-5d48-4121-bbec-fb4483146b20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279571658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.279571658
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.2208543240
Short name T710
Test name
Test status
Simulation time 33007542 ps
CPU time 1.32 seconds
Started Jul 20 04:33:46 PM PDT 24
Finished Jul 20 04:33:50 PM PDT 24
Peak memory 196884 kb
Host smart-68cb0e27-320b-49d5-a116-d4f8c5de45d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208543240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.2208543240
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1341401473
Short name T460
Test name
Test status
Simulation time 677413499 ps
CPU time 3.07 seconds
Started Jul 20 04:33:51 PM PDT 24
Finished Jul 20 04:33:55 PM PDT 24
Peak memory 195940 kb
Host smart-919c7ed6-9d59-409c-a87e-810ddd336751
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341401473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1341401473
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2937167225
Short name T554
Test name
Test status
Simulation time 103117385 ps
CPU time 0.82 seconds
Started Jul 20 04:33:49 PM PDT 24
Finished Jul 20 04:33:51 PM PDT 24
Peak memory 197312 kb
Host smart-deff6b00-10b6-47cf-9759-c889119c7412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937167225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2937167225
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.2763935577
Short name T107
Test name
Test status
Simulation time 55229043 ps
CPU time 1.12 seconds
Started Jul 20 04:33:55 PM PDT 24
Finished Jul 20 04:33:56 PM PDT 24
Peak memory 196164 kb
Host smart-788169ad-0bf3-4132-8789-245888eaba22
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763935577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.2763935577
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3776852823
Short name T656
Test name
Test status
Simulation time 517521012 ps
CPU time 5.32 seconds
Started Jul 20 04:33:46 PM PDT 24
Finished Jul 20 04:33:55 PM PDT 24
Peak memory 198108 kb
Host smart-ec80108d-20d5-466e-b782-7030e9cd3eed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776852823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3776852823
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_smoke.2910087844
Short name T653
Test name
Test status
Simulation time 31619704 ps
CPU time 0.8 seconds
Started Jul 20 04:33:48 PM PDT 24
Finished Jul 20 04:33:50 PM PDT 24
Peak memory 196132 kb
Host smart-c9997800-e6af-4dff-9450-b0ae0b89c533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910087844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2910087844
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.3434747305
Short name T472
Test name
Test status
Simulation time 93692276 ps
CPU time 0.83 seconds
Started Jul 20 04:33:51 PM PDT 24
Finished Jul 20 04:33:52 PM PDT 24
Peak memory 196364 kb
Host smart-f2700a99-1183-4efb-a143-f0336509556b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434747305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.3434747305
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2011990563
Short name T504
Test name
Test status
Simulation time 12674933096 ps
CPU time 86.25 seconds
Started Jul 20 04:33:57 PM PDT 24
Finished Jul 20 04:35:24 PM PDT 24
Peak memory 198260 kb
Host smart-6b6835d4-2581-4c61-8c29-eeee59231e02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011990563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2011990563
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.130510309
Short name T570
Test name
Test status
Simulation time 295724912305 ps
CPU time 1419.46 seconds
Started Jul 20 04:33:55 PM PDT 24
Finished Jul 20 04:57:35 PM PDT 24
Peak memory 198384 kb
Host smart-d5b917fc-f250-4bda-b864-76de7006b72f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=130510309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.130510309
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2126452446
Short name T657
Test name
Test status
Simulation time 35746630 ps
CPU time 0.55 seconds
Started Jul 20 04:35:21 PM PDT 24
Finished Jul 20 04:35:24 PM PDT 24
Peak memory 194296 kb
Host smart-12c2be36-2f0c-41c0-839b-6750a24a3243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126452446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2126452446
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1294117169
Short name T535
Test name
Test status
Simulation time 108758246 ps
CPU time 0.84 seconds
Started Jul 20 04:35:16 PM PDT 24
Finished Jul 20 04:35:18 PM PDT 24
Peak memory 197268 kb
Host smart-8eff9dab-ce99-42bf-8eb8-ada26c120b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294117169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1294117169
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3412198845
Short name T492
Test name
Test status
Simulation time 1330069937 ps
CPU time 8.34 seconds
Started Jul 20 04:35:22 PM PDT 24
Finished Jul 20 04:35:32 PM PDT 24
Peak memory 196828 kb
Host smart-79c44322-b5d3-483a-b8b6-5339802d3bd0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412198845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3412198845
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2502385662
Short name T285
Test name
Test status
Simulation time 100724519 ps
CPU time 0.87 seconds
Started Jul 20 04:35:22 PM PDT 24
Finished Jul 20 04:35:25 PM PDT 24
Peak memory 197756 kb
Host smart-c9a9ff58-4d3b-4258-91e2-b76ba5497a1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502385662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2502385662
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2127257774
Short name T530
Test name
Test status
Simulation time 63939866 ps
CPU time 1.12 seconds
Started Jul 20 04:35:17 PM PDT 24
Finished Jul 20 04:35:19 PM PDT 24
Peak memory 197012 kb
Host smart-56e1d529-b252-4ca3-89de-d4420ddbbe2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127257774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2127257774
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3178037802
Short name T235
Test name
Test status
Simulation time 75892457 ps
CPU time 2.77 seconds
Started Jul 20 04:35:25 PM PDT 24
Finished Jul 20 04:35:31 PM PDT 24
Peak memory 198076 kb
Host smart-81dadd97-b2b3-45ff-a7fd-b5a41771dd93
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178037802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3178037802
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1615067881
Short name T176
Test name
Test status
Simulation time 760644416 ps
CPU time 2.46 seconds
Started Jul 20 04:35:20 PM PDT 24
Finished Jul 20 04:35:25 PM PDT 24
Peak memory 196656 kb
Host smart-b95c1436-1e29-4ebf-ba3d-cd88c6bea13e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615067881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1615067881
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.2770991258
Short name T347
Test name
Test status
Simulation time 14069989 ps
CPU time 0.66 seconds
Started Jul 20 04:35:17 PM PDT 24
Finished Jul 20 04:35:20 PM PDT 24
Peak memory 195044 kb
Host smart-8120fa97-f7c7-403c-936e-1b12d7ac1024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770991258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.2770991258
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2013271226
Short name T225
Test name
Test status
Simulation time 196517487 ps
CPU time 0.98 seconds
Started Jul 20 04:35:19 PM PDT 24
Finished Jul 20 04:35:22 PM PDT 24
Peak memory 196104 kb
Host smart-fc9261f8-a082-4b4e-89bd-4e8fae0bb8ea
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013271226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2013271226
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.1466435719
Short name T513
Test name
Test status
Simulation time 43856105 ps
CPU time 1.97 seconds
Started Jul 20 04:35:19 PM PDT 24
Finished Jul 20 04:35:23 PM PDT 24
Peak memory 198084 kb
Host smart-ea47a47c-db1d-4a32-8c1e-92c00b858fcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466435719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.1466435719
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1199852943
Short name T561
Test name
Test status
Simulation time 140563394 ps
CPU time 0.88 seconds
Started Jul 20 04:35:18 PM PDT 24
Finished Jul 20 04:35:21 PM PDT 24
Peak memory 195540 kb
Host smart-c235dc70-c20c-4dbb-942d-722df750ef02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199852943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1199852943
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.598235100
Short name T168
Test name
Test status
Simulation time 161992077 ps
CPU time 1.06 seconds
Started Jul 20 04:35:15 PM PDT 24
Finished Jul 20 04:35:17 PM PDT 24
Peak memory 196616 kb
Host smart-841271b1-8239-4618-a7f2-17e63f95ef14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598235100 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.598235100
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1003730208
Short name T164
Test name
Test status
Simulation time 6381353358 ps
CPU time 90.88 seconds
Started Jul 20 04:35:22 PM PDT 24
Finished Jul 20 04:36:54 PM PDT 24
Peak memory 198280 kb
Host smart-cb7d4faa-525f-4f71-9c72-18369a84300b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003730208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1003730208
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.1738068372
Short name T481
Test name
Test status
Simulation time 25999700 ps
CPU time 0.57 seconds
Started Jul 20 04:35:34 PM PDT 24
Finished Jul 20 04:35:37 PM PDT 24
Peak memory 194356 kb
Host smart-a548a111-3a71-4919-a31d-dfdeadbbe5ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738068372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.1738068372
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.3920900828
Short name T634
Test name
Test status
Simulation time 67515226 ps
CPU time 0.77 seconds
Started Jul 20 04:35:22 PM PDT 24
Finished Jul 20 04:35:24 PM PDT 24
Peak memory 195244 kb
Host smart-2fcef0a8-b76a-4d10-bc86-ed6aba3792b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920900828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.3920900828
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.3687136288
Short name T632
Test name
Test status
Simulation time 227088777 ps
CPU time 5.83 seconds
Started Jul 20 04:35:26 PM PDT 24
Finished Jul 20 04:35:34 PM PDT 24
Peak memory 196928 kb
Host smart-a23bd852-a5be-4dbd-b6cc-339f020334de
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687136288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.3687136288
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2949909955
Short name T60
Test name
Test status
Simulation time 292284208 ps
CPU time 0.99 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:27 PM PDT 24
Peak memory 196640 kb
Host smart-8dcca4dc-0095-4d42-98db-baeb09384815
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949909955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2949909955
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.1135875929
Short name T272
Test name
Test status
Simulation time 69990150 ps
CPU time 1.09 seconds
Started Jul 20 04:35:28 PM PDT 24
Finished Jul 20 04:35:31 PM PDT 24
Peak memory 195660 kb
Host smart-b7a3d67e-676b-4d68-9437-7b0152c6116b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135875929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.1135875929
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.2326223566
Short name T322
Test name
Test status
Simulation time 73996698 ps
CPU time 2.8 seconds
Started Jul 20 04:35:30 PM PDT 24
Finished Jul 20 04:35:34 PM PDT 24
Peak memory 196364 kb
Host smart-b97654af-6b72-478f-b9a3-35c39348b1d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326223566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.2326223566
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.321483000
Short name T251
Test name
Test status
Simulation time 659229115 ps
CPU time 3.15 seconds
Started Jul 20 04:35:25 PM PDT 24
Finished Jul 20 04:35:30 PM PDT 24
Peak memory 198132 kb
Host smart-09d4b08e-1389-4330-a516-bcced75e6c57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321483000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
321483000
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3866413852
Short name T320
Test name
Test status
Simulation time 57683699 ps
CPU time 1.24 seconds
Started Jul 20 04:35:21 PM PDT 24
Finished Jul 20 04:35:25 PM PDT 24
Peak memory 196628 kb
Host smart-8404e686-34b5-489a-9206-418a1f1c8d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866413852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3866413852
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.3447180108
Short name T478
Test name
Test status
Simulation time 31214966 ps
CPU time 1.02 seconds
Started Jul 20 04:35:22 PM PDT 24
Finished Jul 20 04:35:25 PM PDT 24
Peak memory 195968 kb
Host smart-a71adc58-45d7-49c9-af65-86a847618780
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447180108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.3447180108
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.791116271
Short name T605
Test name
Test status
Simulation time 240186304 ps
CPU time 5.45 seconds
Started Jul 20 04:35:25 PM PDT 24
Finished Jul 20 04:35:33 PM PDT 24
Peak memory 198100 kb
Host smart-bfde3b94-b5cc-4bc4-ad20-8587bcf32ee6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791116271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ran
dom_long_reg_writes_reg_reads.791116271
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3605190185
Short name T335
Test name
Test status
Simulation time 183605267 ps
CPU time 1.21 seconds
Started Jul 20 04:35:22 PM PDT 24
Finished Jul 20 04:35:24 PM PDT 24
Peak memory 195940 kb
Host smart-935afb41-548a-4f88-9c3d-50c48643b3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605190185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3605190185
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2544994898
Short name T108
Test name
Test status
Simulation time 403726383 ps
CPU time 1.12 seconds
Started Jul 20 04:35:19 PM PDT 24
Finished Jul 20 04:35:23 PM PDT 24
Peak memory 195720 kb
Host smart-71aacaa2-58dd-4057-92f6-ac33e799657e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544994898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2544994898
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2699509567
Short name T380
Test name
Test status
Simulation time 11163967081 ps
CPU time 174.78 seconds
Started Jul 20 04:35:27 PM PDT 24
Finished Jul 20 04:38:24 PM PDT 24
Peak memory 198344 kb
Host smart-25907f62-b058-44aa-8c92-039a14d3d7f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2699509567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2699509567
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.809077269
Short name T316
Test name
Test status
Simulation time 100408189 ps
CPU time 0.59 seconds
Started Jul 20 04:35:26 PM PDT 24
Finished Jul 20 04:35:29 PM PDT 24
Peak memory 194344 kb
Host smart-c93ee510-20f0-4c58-9e95-970dd698450b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809077269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.809077269
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1833619256
Short name T701
Test name
Test status
Simulation time 15691200 ps
CPU time 0.61 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:26 PM PDT 24
Peak memory 193932 kb
Host smart-3adb4fec-4dc4-4958-b344-1938e204d03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833619256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1833619256
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3069613151
Short name T569
Test name
Test status
Simulation time 1299315387 ps
CPU time 11.34 seconds
Started Jul 20 04:35:30 PM PDT 24
Finished Jul 20 04:35:43 PM PDT 24
Peak memory 195684 kb
Host smart-19196aed-6195-43ff-a12f-de2c51349ea3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069613151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3069613151
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3824225936
Short name T328
Test name
Test status
Simulation time 35281585 ps
CPU time 0.71 seconds
Started Jul 20 04:35:30 PM PDT 24
Finished Jul 20 04:35:33 PM PDT 24
Peak memory 194808 kb
Host smart-1435a46a-b2cb-475e-b5cc-02fbbbdcafd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824225936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3824225936
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2645576550
Short name T71
Test name
Test status
Simulation time 84576470 ps
CPU time 1.04 seconds
Started Jul 20 04:35:23 PM PDT 24
Finished Jul 20 04:35:26 PM PDT 24
Peak memory 195872 kb
Host smart-a89d719d-1fdf-484d-8f70-1d890e239222
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645576550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2645576550
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.21845534
Short name T298
Test name
Test status
Simulation time 187945299 ps
CPU time 1.43 seconds
Started Jul 20 04:35:35 PM PDT 24
Finished Jul 20 04:35:39 PM PDT 24
Peak memory 196588 kb
Host smart-1102e115-dab7-4105-98a0-2beae19adf9f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21845534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 32.gpio_intr_with_filter_rand_intr_event.21845534
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.300354315
Short name T609
Test name
Test status
Simulation time 193867520 ps
CPU time 2.13 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:35:38 PM PDT 24
Peak memory 198188 kb
Host smart-13338c92-1f7d-4fa2-851c-4a87f0d8499a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300354315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger.
300354315
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.2762479883
Short name T359
Test name
Test status
Simulation time 63674890 ps
CPU time 1.11 seconds
Started Jul 20 04:35:25 PM PDT 24
Finished Jul 20 04:35:29 PM PDT 24
Peak memory 197148 kb
Host smart-d6410b80-eeae-48b8-9390-0bd0e2f880bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762479883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.2762479883
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.2565086675
Short name T178
Test name
Test status
Simulation time 33305812 ps
CPU time 1.16 seconds
Started Jul 20 04:35:28 PM PDT 24
Finished Jul 20 04:35:31 PM PDT 24
Peak memory 197108 kb
Host smart-f6184467-826f-4a38-96e0-1b706f804209
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565086675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.2565086675
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1887559669
Short name T591
Test name
Test status
Simulation time 713514562 ps
CPU time 5.36 seconds
Started Jul 20 04:35:27 PM PDT 24
Finished Jul 20 04:35:34 PM PDT 24
Peak memory 198116 kb
Host smart-b46dfa04-32b2-4805-9e87-ff76218b815d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887559669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1887559669
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.3303517421
Short name T159
Test name
Test status
Simulation time 170801186 ps
CPU time 1.26 seconds
Started Jul 20 04:35:35 PM PDT 24
Finished Jul 20 04:35:38 PM PDT 24
Peak memory 196796 kb
Host smart-7deb7fe9-04ad-46b0-a730-cf879849c4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303517421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.3303517421
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3210814069
Short name T356
Test name
Test status
Simulation time 205190461 ps
CPU time 1.05 seconds
Started Jul 20 04:35:25 PM PDT 24
Finished Jul 20 04:35:29 PM PDT 24
Peak memory 195716 kb
Host smart-b672b51d-5bfb-447f-a603-844bce24d1c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210814069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3210814069
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.4154073910
Short name T341
Test name
Test status
Simulation time 90710040865 ps
CPU time 109.74 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:37:25 PM PDT 24
Peak memory 197420 kb
Host smart-4bc0d5c6-2f45-4b03-a031-5c6eb747a93c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154073910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.4154073910
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1339132281
Short name T568
Test name
Test status
Simulation time 39105950 ps
CPU time 0.57 seconds
Started Jul 20 04:35:25 PM PDT 24
Finished Jul 20 04:35:28 PM PDT 24
Peak memory 194844 kb
Host smart-3cafa9aa-b7eb-49bb-807a-d4c17bdca3a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339132281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1339132281
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3876017656
Short name T355
Test name
Test status
Simulation time 42048237 ps
CPU time 0.68 seconds
Started Jul 20 04:35:35 PM PDT 24
Finished Jul 20 04:35:38 PM PDT 24
Peak memory 194904 kb
Host smart-09dbec0b-f07b-4992-b7a3-9e168ba86001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876017656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3876017656
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3402404444
Short name T593
Test name
Test status
Simulation time 1899369850 ps
CPU time 23.07 seconds
Started Jul 20 04:35:26 PM PDT 24
Finished Jul 20 04:35:52 PM PDT 24
Peak memory 198076 kb
Host smart-02c14e11-55ba-4af5-aa0f-eafec0e8b4e5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402404444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3402404444
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.140294463
Short name T470
Test name
Test status
Simulation time 246877795 ps
CPU time 1.06 seconds
Started Jul 20 04:35:25 PM PDT 24
Finished Jul 20 04:35:29 PM PDT 24
Peak memory 196780 kb
Host smart-a51e2d30-ef74-4244-bb67-b90b3afa0994
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140294463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.140294463
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2289556649
Short name T652
Test name
Test status
Simulation time 103596909 ps
CPU time 1.45 seconds
Started Jul 20 04:35:26 PM PDT 24
Finished Jul 20 04:35:30 PM PDT 24
Peak memory 198108 kb
Host smart-1a567cb3-7fb2-428e-9d99-30d9f01e7975
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289556649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2289556649
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.2336163
Short name T59
Test name
Test status
Simulation time 51039331 ps
CPU time 1.9 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:28 PM PDT 24
Peak memory 195980 kb
Host smart-d2a1da1a-807d-4da1-8883-28b3718a0966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.2336163
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.4224062082
Short name T187
Test name
Test status
Simulation time 75142759 ps
CPU time 1.03 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:28 PM PDT 24
Peak memory 196600 kb
Host smart-ed6039ae-9608-4c72-a295-181add477a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224062082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.4224062082
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.1312123920
Short name T75
Test name
Test status
Simulation time 109882902 ps
CPU time 0.81 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:35:36 PM PDT 24
Peak memory 196656 kb
Host smart-acdd84b5-3c22-4aa6-9df1-b9a9693a8a19
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312123920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.1312123920
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.1870657092
Short name T143
Test name
Test status
Simulation time 89172424 ps
CPU time 4.01 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:35:40 PM PDT 24
Peak memory 198104 kb
Host smart-5b283f44-8b99-419f-951e-632ce470b798
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870657092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.1870657092
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3056120222
Short name T487
Test name
Test status
Simulation time 375240717 ps
CPU time 0.99 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:27 PM PDT 24
Peak memory 196036 kb
Host smart-851c877a-1f13-44e6-a94e-45262abfd5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056120222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3056120222
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.804674577
Short name T599
Test name
Test status
Simulation time 760405057 ps
CPU time 1.4 seconds
Started Jul 20 04:35:25 PM PDT 24
Finished Jul 20 04:35:29 PM PDT 24
Peak memory 198160 kb
Host smart-5306bca1-2f86-4a65-ad9a-89a67fbf4e44
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804674577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.804674577
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1136851351
Short name T218
Test name
Test status
Simulation time 10293766587 ps
CPU time 153.28 seconds
Started Jul 20 04:35:26 PM PDT 24
Finished Jul 20 04:38:02 PM PDT 24
Peak memory 198296 kb
Host smart-930c3fe8-5862-449f-841a-067a597f5eb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136851351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1136851351
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.586674703
Short name T418
Test name
Test status
Simulation time 46969222 ps
CPU time 0.59 seconds
Started Jul 20 04:35:26 PM PDT 24
Finished Jul 20 04:35:29 PM PDT 24
Peak memory 195000 kb
Host smart-bc957e21-90cd-46f2-ac6d-96ab1e93d2e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586674703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.586674703
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.2722885748
Short name T529
Test name
Test status
Simulation time 15454015 ps
CPU time 0.62 seconds
Started Jul 20 04:35:29 PM PDT 24
Finished Jul 20 04:35:31 PM PDT 24
Peak memory 193992 kb
Host smart-3239379d-f9a8-4f9e-b518-ee46c5c3e76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722885748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.2722885748
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3483854131
Short name T467
Test name
Test status
Simulation time 577486264 ps
CPU time 21.82 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:35:58 PM PDT 24
Peak memory 198164 kb
Host smart-1ead65d6-3d4b-445a-bbf4-d4bbdcb8fa64
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483854131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3483854131
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2930142297
Short name T332
Test name
Test status
Simulation time 242996227 ps
CPU time 0.86 seconds
Started Jul 20 04:35:30 PM PDT 24
Finished Jul 20 04:35:32 PM PDT 24
Peak memory 196076 kb
Host smart-52cfa18f-230e-4a9c-9e60-ec5023ae679d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930142297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2930142297
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.3066399494
Short name T716
Test name
Test status
Simulation time 219007639 ps
CPU time 1.07 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:26 PM PDT 24
Peak memory 196700 kb
Host smart-b466c875-5693-4f34-8336-570d30921dfb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066399494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.3066399494
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1311500490
Short name T581
Test name
Test status
Simulation time 196200162 ps
CPU time 2.21 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:35:38 PM PDT 24
Peak memory 198036 kb
Host smart-af6aea0c-a732-4742-b3d7-2fe4c5ad116e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311500490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1311500490
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2508578882
Short name T402
Test name
Test status
Simulation time 171287256 ps
CPU time 2.57 seconds
Started Jul 20 04:35:27 PM PDT 24
Finished Jul 20 04:35:31 PM PDT 24
Peak memory 197328 kb
Host smart-9d6a4457-bf60-4757-a6bb-c06cb360bb3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508578882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2508578882
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.4038571176
Short name T548
Test name
Test status
Simulation time 53143157 ps
CPU time 0.63 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:27 PM PDT 24
Peak memory 194352 kb
Host smart-87c9e725-16df-4248-be73-988adc792aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038571176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.4038571176
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3507352588
Short name T255
Test name
Test status
Simulation time 68677432 ps
CPU time 1.36 seconds
Started Jul 20 04:35:30 PM PDT 24
Finished Jul 20 04:35:33 PM PDT 24
Peak memory 198164 kb
Host smart-41494fa8-deae-45b6-bbc8-180d82e390d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507352588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3507352588
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2165467749
Short name T611
Test name
Test status
Simulation time 1418119228 ps
CPU time 6.74 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:33 PM PDT 24
Peak memory 198136 kb
Host smart-02ebaf33-81a3-4355-8122-543b355bd2d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165467749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2165467749
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.385291868
Short name T17
Test name
Test status
Simulation time 317786184 ps
CPU time 1.23 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:35:37 PM PDT 24
Peak memory 197996 kb
Host smart-bcc47428-0de6-4304-b0b9-d02eee6aca1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385291868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.385291868
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.3481791641
Short name T706
Test name
Test status
Simulation time 179822331 ps
CPU time 0.98 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:35:36 PM PDT 24
Peak memory 195436 kb
Host smart-c0bf0be2-11b0-4b74-96fc-5f196c08db12
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481791641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.3481791641
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.1345326991
Short name T440
Test name
Test status
Simulation time 1659282066 ps
CPU time 18.47 seconds
Started Jul 20 04:35:30 PM PDT 24
Finished Jul 20 04:35:50 PM PDT 24
Peak memory 198164 kb
Host smart-5c351ef6-7936-476b-8772-ee89776c4cf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345326991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.1345326991
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2544274046
Short name T670
Test name
Test status
Simulation time 529428254420 ps
CPU time 1243.26 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:56:18 PM PDT 24
Peak memory 198372 kb
Host smart-d981249a-29f4-472c-8e39-e3dc17903986
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2544274046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.2544274046
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3292213754
Short name T58
Test name
Test status
Simulation time 14989085 ps
CPU time 0.55 seconds
Started Jul 20 04:35:41 PM PDT 24
Finished Jul 20 04:35:43 PM PDT 24
Peak memory 194056 kb
Host smart-cf3ff0e1-e0d5-4e1d-b1a3-552bd6b830eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292213754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3292213754
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.825618849
Short name T585
Test name
Test status
Simulation time 181443185 ps
CPU time 0.94 seconds
Started Jul 20 04:35:26 PM PDT 24
Finished Jul 20 04:35:29 PM PDT 24
Peak memory 196732 kb
Host smart-b10a5e55-3afc-4471-99c8-ae0276077f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825618849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.825618849
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.312109779
Short name T13
Test name
Test status
Simulation time 5080325824 ps
CPU time 12.68 seconds
Started Jul 20 04:35:28 PM PDT 24
Finished Jul 20 04:35:43 PM PDT 24
Peak memory 197816 kb
Host smart-3e5d63f9-977a-41d9-b8dc-e572c9848bce
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312109779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stres
s.312109779
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.1304443041
Short name T471
Test name
Test status
Simulation time 97292881 ps
CPU time 0.78 seconds
Started Jul 20 04:35:32 PM PDT 24
Finished Jul 20 04:35:34 PM PDT 24
Peak memory 195920 kb
Host smart-07335fd2-8086-4447-b6ea-59a08b986a73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304443041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.1304443041
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1238997171
Short name T188
Test name
Test status
Simulation time 37517304 ps
CPU time 1.07 seconds
Started Jul 20 04:35:30 PM PDT 24
Finished Jul 20 04:35:33 PM PDT 24
Peak memory 196312 kb
Host smart-cadef161-c802-4d9f-97ce-7951cbc276dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238997171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1238997171
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.2284726326
Short name T537
Test name
Test status
Simulation time 108570676 ps
CPU time 1.44 seconds
Started Jul 20 04:35:25 PM PDT 24
Finished Jul 20 04:35:28 PM PDT 24
Peak memory 197032 kb
Host smart-57e52b3a-643e-40b4-833c-1538d6cc7eec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284726326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.2284726326
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.88442839
Short name T324
Test name
Test status
Simulation time 182815553 ps
CPU time 1.56 seconds
Started Jul 20 04:35:28 PM PDT 24
Finished Jul 20 04:35:31 PM PDT 24
Peak memory 196256 kb
Host smart-201a195f-3be8-4d5f-86ac-5a390eb02014
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88442839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger.88442839
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.1135968595
Short name T281
Test name
Test status
Simulation time 81099196 ps
CPU time 0.72 seconds
Started Jul 20 04:35:24 PM PDT 24
Finished Jul 20 04:35:26 PM PDT 24
Peak memory 195420 kb
Host smart-d6dc3801-aa49-4cc0-9d31-65696a1941b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135968595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.1135968595
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.84213492
Short name T23
Test name
Test status
Simulation time 239297976 ps
CPU time 1.18 seconds
Started Jul 20 04:35:30 PM PDT 24
Finished Jul 20 04:35:33 PM PDT 24
Peak memory 197192 kb
Host smart-1e7f0081-c769-4032-bad7-3cffaea90322
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84213492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup_
pulldown.84213492
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1238190050
Short name T437
Test name
Test status
Simulation time 164008959 ps
CPU time 2.14 seconds
Started Jul 20 04:35:28 PM PDT 24
Finished Jul 20 04:35:32 PM PDT 24
Peak memory 198068 kb
Host smart-70d9faf0-a75c-4f58-914a-c56494ab0134
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238190050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1238190050
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1349158104
Short name T562
Test name
Test status
Simulation time 567044191 ps
CPU time 1.08 seconds
Started Jul 20 04:35:26 PM PDT 24
Finished Jul 20 04:35:29 PM PDT 24
Peak memory 195684 kb
Host smart-15931618-1f5d-405a-a976-101e1d03cd44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349158104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1349158104
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2415437147
Short name T268
Test name
Test status
Simulation time 37161533 ps
CPU time 1.15 seconds
Started Jul 20 04:35:29 PM PDT 24
Finished Jul 20 04:35:32 PM PDT 24
Peak memory 196308 kb
Host smart-b523b1b8-176b-4175-81df-427c3d9c3fb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415437147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2415437147
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.4211928670
Short name T252
Test name
Test status
Simulation time 22496267770 ps
CPU time 147.71 seconds
Started Jul 20 04:35:37 PM PDT 24
Finished Jul 20 04:38:06 PM PDT 24
Peak memory 198268 kb
Host smart-8052d495-9ad6-4fde-b18f-f7d641c6abb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211928670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.4211928670
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.4141331090
Short name T325
Test name
Test status
Simulation time 79503253 ps
CPU time 0.59 seconds
Started Jul 20 04:35:35 PM PDT 24
Finished Jul 20 04:35:38 PM PDT 24
Peak memory 195004 kb
Host smart-369c82ee-d247-47c9-be52-c53823c59013
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141331090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.4141331090
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3208020065
Short name T712
Test name
Test status
Simulation time 45182322 ps
CPU time 0.72 seconds
Started Jul 20 04:35:41 PM PDT 24
Finished Jul 20 04:35:43 PM PDT 24
Peak memory 195252 kb
Host smart-ff32349e-10c6-4fe7-8402-f3b3165139b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208020065 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3208020065
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2131302243
Short name T377
Test name
Test status
Simulation time 828720214 ps
CPU time 25.65 seconds
Started Jul 20 04:35:40 PM PDT 24
Finished Jul 20 04:36:07 PM PDT 24
Peak memory 196340 kb
Host smart-a5513b26-3a59-49f7-8454-266afa31fa6f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131302243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2131302243
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3637482022
Short name T720
Test name
Test status
Simulation time 64228101 ps
CPU time 0.84 seconds
Started Jul 20 04:35:38 PM PDT 24
Finished Jul 20 04:35:39 PM PDT 24
Peak memory 196536 kb
Host smart-8db00ff1-f4f8-4a2a-9d9e-6c810a21e69d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637482022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3637482022
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1508286886
Short name T349
Test name
Test status
Simulation time 98937750 ps
CPU time 1.31 seconds
Started Jul 20 04:35:37 PM PDT 24
Finished Jul 20 04:35:39 PM PDT 24
Peak memory 196992 kb
Host smart-82842a40-df70-472b-8d5e-3e984a2b5a6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508286886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1508286886
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.1039940631
Short name T120
Test name
Test status
Simulation time 42422708 ps
CPU time 1.68 seconds
Started Jul 20 04:35:36 PM PDT 24
Finished Jul 20 04:35:39 PM PDT 24
Peak memory 196428 kb
Host smart-d839873c-eecd-476c-9ef3-a63760cc0026
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039940631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.1039940631
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.4008231592
Short name T696
Test name
Test status
Simulation time 105133609 ps
CPU time 2.46 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:35:39 PM PDT 24
Peak memory 196696 kb
Host smart-a89d9957-566e-422e-8490-bc1d86e58ff2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008231592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.4008231592
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3204094321
Short name T265
Test name
Test status
Simulation time 24024574 ps
CPU time 0.69 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:35:36 PM PDT 24
Peak memory 195392 kb
Host smart-fc1539de-2e0d-4472-abc1-11488cba950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204094321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3204094321
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1766419630
Short name T137
Test name
Test status
Simulation time 27947055 ps
CPU time 0.84 seconds
Started Jul 20 04:35:32 PM PDT 24
Finished Jul 20 04:35:35 PM PDT 24
Peak memory 195660 kb
Host smart-361b717e-31bd-4f7a-8a24-cf51dc421180
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766419630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1766419630
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3114302412
Short name T575
Test name
Test status
Simulation time 112097564 ps
CPU time 1.28 seconds
Started Jul 20 04:35:35 PM PDT 24
Finished Jul 20 04:35:38 PM PDT 24
Peak memory 198088 kb
Host smart-653f3d50-26b3-4205-9a0a-16281385bbec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114302412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3114302412
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.2710015954
Short name T606
Test name
Test status
Simulation time 126530219 ps
CPU time 1.19 seconds
Started Jul 20 04:35:40 PM PDT 24
Finished Jul 20 04:35:42 PM PDT 24
Peak memory 198120 kb
Host smart-ccc1aa61-ae5a-4626-85dd-bf8db2ba2eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710015954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.2710015954
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.3571480193
Short name T12
Test name
Test status
Simulation time 50026584 ps
CPU time 0.86 seconds
Started Jul 20 04:35:38 PM PDT 24
Finished Jul 20 04:35:40 PM PDT 24
Peak memory 196236 kb
Host smart-6074d326-9730-4d12-a893-c960a7cf3b14
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571480193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.3571480193
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.4188911356
Short name T465
Test name
Test status
Simulation time 16269192091 ps
CPU time 178.45 seconds
Started Jul 20 04:35:34 PM PDT 24
Finished Jul 20 04:38:35 PM PDT 24
Peak memory 198236 kb
Host smart-9ea4e7bc-51a2-4589-aad7-6ede6ee5ab55
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188911356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.4188911356
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3987252971
Short name T193
Test name
Test status
Simulation time 16401950 ps
CPU time 0.62 seconds
Started Jul 20 04:35:32 PM PDT 24
Finished Jul 20 04:35:35 PM PDT 24
Peak memory 194328 kb
Host smart-37046af2-5f97-4d48-94ed-1d7230155ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987252971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3987252971
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2080289456
Short name T454
Test name
Test status
Simulation time 84912717 ps
CPU time 0.71 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:35:36 PM PDT 24
Peak memory 194232 kb
Host smart-13fc17e8-a82b-45dd-bb08-844cf896a3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080289456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2080289456
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.382516178
Short name T693
Test name
Test status
Simulation time 2044932849 ps
CPU time 25.45 seconds
Started Jul 20 04:35:36 PM PDT 24
Finished Jul 20 04:36:03 PM PDT 24
Peak memory 196840 kb
Host smart-98fa14fd-64ae-4e52-a676-eae17f274afd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382516178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.382516178
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1922899321
Short name T246
Test name
Test status
Simulation time 474480465 ps
CPU time 1.13 seconds
Started Jul 20 04:35:34 PM PDT 24
Finished Jul 20 04:35:38 PM PDT 24
Peak memory 196768 kb
Host smart-b4a683e6-f13b-4ecb-bb18-5a391c17b1b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922899321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1922899321
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.297003593
Short name T157
Test name
Test status
Simulation time 102875750 ps
CPU time 0.91 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:35:36 PM PDT 24
Peak memory 196956 kb
Host smart-7f064916-10d3-4a26-b442-c05bebd01cff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297003593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.297003593
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.375446226
Short name T364
Test name
Test status
Simulation time 287439699 ps
CPU time 2.82 seconds
Started Jul 20 04:35:36 PM PDT 24
Finished Jul 20 04:35:40 PM PDT 24
Peak memory 198104 kb
Host smart-46e309e0-0582-4d8c-9c27-196580c5c9a6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375446226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.375446226
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.1568899124
Short name T673
Test name
Test status
Simulation time 167927975 ps
CPU time 2.8 seconds
Started Jul 20 04:35:40 PM PDT 24
Finished Jul 20 04:35:44 PM PDT 24
Peak memory 198136 kb
Host smart-f0bc5df3-47b0-4abf-8719-bfaa3a0ee6de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568899124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.1568899124
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3477538881
Short name T172
Test name
Test status
Simulation time 247702322 ps
CPU time 1.03 seconds
Started Jul 20 04:35:32 PM PDT 24
Finished Jul 20 04:35:36 PM PDT 24
Peak memory 195944 kb
Host smart-3a9d15fe-92f2-453c-9acd-3a221493097d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477538881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3477538881
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.2242941411
Short name T269
Test name
Test status
Simulation time 18551589 ps
CPU time 0.67 seconds
Started Jul 20 04:35:35 PM PDT 24
Finished Jul 20 04:35:38 PM PDT 24
Peak memory 195028 kb
Host smart-8b557e19-2c36-41cf-8255-3ae1ba862871
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242941411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.2242941411
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.4124273090
Short name T1
Test name
Test status
Simulation time 497734838 ps
CPU time 1.73 seconds
Started Jul 20 04:35:41 PM PDT 24
Finished Jul 20 04:35:44 PM PDT 24
Peak memory 197900 kb
Host smart-87eff571-14a2-416a-90e9-d41c90c1a99c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124273090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.4124273090
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.1740624495
Short name T455
Test name
Test status
Simulation time 333854173 ps
CPU time 1.37 seconds
Started Jul 20 04:35:34 PM PDT 24
Finished Jul 20 04:35:38 PM PDT 24
Peak memory 197036 kb
Host smart-92f4fa89-fa9d-4ec2-bd0b-bb3df3df1e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740624495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.1740624495
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3963934290
Short name T524
Test name
Test status
Simulation time 205839701 ps
CPU time 1.1 seconds
Started Jul 20 04:35:32 PM PDT 24
Finished Jul 20 04:35:36 PM PDT 24
Peak memory 196624 kb
Host smart-85d59fff-6f7b-4f66-b8e6-e0aa516c10cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963934290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3963934290
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.145666125
Short name T678
Test name
Test status
Simulation time 7697015017 ps
CPU time 41.67 seconds
Started Jul 20 04:35:38 PM PDT 24
Finished Jul 20 04:36:20 PM PDT 24
Peak memory 198116 kb
Host smart-691bff07-52da-40d4-8e2a-a93ba95835ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145666125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.145666125
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.970665147
Short name T662
Test name
Test status
Simulation time 87475799125 ps
CPU time 882.32 seconds
Started Jul 20 04:35:38 PM PDT 24
Finished Jul 20 04:50:21 PM PDT 24
Peak memory 198340 kb
Host smart-9235f023-29f1-4309-98b4-8dfbc51c62ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=970665147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.970665147
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1064309226
Short name T378
Test name
Test status
Simulation time 15747647 ps
CPU time 0.59 seconds
Started Jul 20 04:35:42 PM PDT 24
Finished Jul 20 04:35:45 PM PDT 24
Peak memory 194180 kb
Host smart-ea1a2a7a-0735-455e-8ce5-8aea85908699
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064309226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1064309226
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.4100050035
Short name T624
Test name
Test status
Simulation time 122500687 ps
CPU time 0.71 seconds
Started Jul 20 04:35:34 PM PDT 24
Finished Jul 20 04:35:38 PM PDT 24
Peak memory 194124 kb
Host smart-27720c2c-11fb-4233-821b-d1ebbcf5f322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100050035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.4100050035
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1082013994
Short name T620
Test name
Test status
Simulation time 636862249 ps
CPU time 23.1 seconds
Started Jul 20 04:35:40 PM PDT 24
Finished Jul 20 04:36:04 PM PDT 24
Peak memory 196976 kb
Host smart-0c984f6b-1460-479b-9d9f-be81cbba7ffa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082013994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1082013994
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3545770021
Short name T410
Test name
Test status
Simulation time 186837388 ps
CPU time 1 seconds
Started Jul 20 04:35:42 PM PDT 24
Finished Jul 20 04:35:44 PM PDT 24
Peak memory 196784 kb
Host smart-9dbff260-274d-4f33-b5e8-87e907602cd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545770021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3545770021
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1046392109
Short name T688
Test name
Test status
Simulation time 17182475 ps
CPU time 0.64 seconds
Started Jul 20 04:35:42 PM PDT 24
Finished Jul 20 04:35:44 PM PDT 24
Peak memory 194260 kb
Host smart-28c871a0-6a0c-46b7-ae50-266baa15d273
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046392109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1046392109
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1538079399
Short name T616
Test name
Test status
Simulation time 42139334 ps
CPU time 1.71 seconds
Started Jul 20 04:35:41 PM PDT 24
Finished Jul 20 04:35:43 PM PDT 24
Peak memory 198160 kb
Host smart-e4677a53-fb57-4417-bbff-20298ea5e35c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538079399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1538079399
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3152981042
Short name T385
Test name
Test status
Simulation time 108621307 ps
CPU time 2.32 seconds
Started Jul 20 04:35:41 PM PDT 24
Finished Jul 20 04:35:44 PM PDT 24
Peak memory 198396 kb
Host smart-c34c8f4b-142e-4ba9-a7e0-7bdde306c301
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152981042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3152981042
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.1332214195
Short name T451
Test name
Test status
Simulation time 147395242 ps
CPU time 0.71 seconds
Started Jul 20 04:35:33 PM PDT 24
Finished Jul 20 04:35:36 PM PDT 24
Peak memory 195436 kb
Host smart-93adb20e-8c7b-479d-a53c-adb637f6b989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332214195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.1332214195
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1297100006
Short name T497
Test name
Test status
Simulation time 201670482 ps
CPU time 1.16 seconds
Started Jul 20 04:35:31 PM PDT 24
Finished Jul 20 04:35:33 PM PDT 24
Peak memory 196212 kb
Host smart-14e69ad9-8768-4df4-ba2c-5db3d3189242
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297100006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1297100006
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2358923053
Short name T289
Test name
Test status
Simulation time 548118500 ps
CPU time 4.59 seconds
Started Jul 20 04:35:44 PM PDT 24
Finished Jul 20 04:35:50 PM PDT 24
Peak memory 198148 kb
Host smart-68e8165e-1e78-4c92-a355-e3246b15da15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358923053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2358923053
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2738254652
Short name T344
Test name
Test status
Simulation time 115031924 ps
CPU time 1.04 seconds
Started Jul 20 04:35:31 PM PDT 24
Finished Jul 20 04:35:34 PM PDT 24
Peak memory 196668 kb
Host smart-87dee315-3c72-4115-b34e-48f89a4bb5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738254652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2738254652
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.1489764881
Short name T138
Test name
Test status
Simulation time 47721441 ps
CPU time 0.99 seconds
Started Jul 20 04:35:34 PM PDT 24
Finished Jul 20 04:35:38 PM PDT 24
Peak memory 196344 kb
Host smart-9f1ab5b3-c5cb-408b-a63e-bb756d4fe08c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489764881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.1489764881
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.1790437908
Short name T370
Test name
Test status
Simulation time 27988253435 ps
CPU time 169.49 seconds
Started Jul 20 04:35:42 PM PDT 24
Finished Jul 20 04:38:32 PM PDT 24
Peak memory 198248 kb
Host smart-cf6b1c08-4218-47a5-8ffc-4b1db5da9d6e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790437908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.1790437908
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.2481869252
Short name T64
Test name
Test status
Simulation time 162702691510 ps
CPU time 408.07 seconds
Started Jul 20 04:35:39 PM PDT 24
Finished Jul 20 04:42:28 PM PDT 24
Peak memory 198292 kb
Host smart-302f2e8d-2687-4499-9120-f143abf946d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2481869252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.2481869252
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1458541837
Short name T278
Test name
Test status
Simulation time 44627451 ps
CPU time 0.56 seconds
Started Jul 20 04:35:40 PM PDT 24
Finished Jul 20 04:35:41 PM PDT 24
Peak memory 194816 kb
Host smart-77ac7d29-d95e-4aea-8f10-1239267d2271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458541837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1458541837
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2613764856
Short name T396
Test name
Test status
Simulation time 575422503 ps
CPU time 0.91 seconds
Started Jul 20 04:35:43 PM PDT 24
Finished Jul 20 04:35:46 PM PDT 24
Peak memory 197152 kb
Host smart-489f014a-dc18-47af-855a-4c92ba50ddc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613764856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2613764856
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1905886831
Short name T390
Test name
Test status
Simulation time 663742001 ps
CPU time 24.1 seconds
Started Jul 20 04:35:41 PM PDT 24
Finished Jul 20 04:36:06 PM PDT 24
Peak memory 196872 kb
Host smart-6eb6b444-d2a1-498c-866b-fd1e26be249e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905886831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1905886831
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1996035899
Short name T428
Test name
Test status
Simulation time 57227595 ps
CPU time 0.66 seconds
Started Jul 20 04:35:44 PM PDT 24
Finished Jul 20 04:35:46 PM PDT 24
Peak memory 194844 kb
Host smart-9f9d0b36-09f3-4960-9cd2-883370e1bf52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996035899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1996035899
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1402491292
Short name T627
Test name
Test status
Simulation time 276251998 ps
CPU time 1.23 seconds
Started Jul 20 04:35:43 PM PDT 24
Finished Jul 20 04:35:46 PM PDT 24
Peak memory 196040 kb
Host smart-c7045ecd-8b08-43bb-97d8-dccd74060264
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402491292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1402491292
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.3889545910
Short name T147
Test name
Test status
Simulation time 349626972 ps
CPU time 3.58 seconds
Started Jul 20 04:35:41 PM PDT 24
Finished Jul 20 04:35:46 PM PDT 24
Peak memory 198072 kb
Host smart-d609860f-efcb-41c7-8bf5-843e917129dc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889545910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.3889545910
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2851192198
Short name T446
Test name
Test status
Simulation time 195212710 ps
CPU time 1.39 seconds
Started Jul 20 04:35:43 PM PDT 24
Finished Jul 20 04:35:46 PM PDT 24
Peak memory 196148 kb
Host smart-fc819d1e-6f5a-4f80-b00b-a6e6f5f34350
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851192198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2851192198
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.3556381856
Short name T488
Test name
Test status
Simulation time 125874357 ps
CPU time 0.89 seconds
Started Jul 20 04:35:42 PM PDT 24
Finished Jul 20 04:35:44 PM PDT 24
Peak memory 195604 kb
Host smart-e090db57-78e9-4e4c-bae1-42ccdfee7b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556381856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.3556381856
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2324594095
Short name T635
Test name
Test status
Simulation time 133618864 ps
CPU time 0.92 seconds
Started Jul 20 04:35:40 PM PDT 24
Finished Jul 20 04:35:41 PM PDT 24
Peak memory 195972 kb
Host smart-360fb51f-f7d1-4e4d-a185-86459427da9b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324594095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2324594095
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.1206987697
Short name T495
Test name
Test status
Simulation time 240917370 ps
CPU time 5.23 seconds
Started Jul 20 04:35:42 PM PDT 24
Finished Jul 20 04:35:49 PM PDT 24
Peak memory 198056 kb
Host smart-d42c0c21-b3bb-4107-9c2b-b46de65e0228
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206987697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.1206987697
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.985258141
Short name T253
Test name
Test status
Simulation time 59267882 ps
CPU time 0.68 seconds
Started Jul 20 04:35:43 PM PDT 24
Finished Jul 20 04:35:45 PM PDT 24
Peak memory 194240 kb
Host smart-dd14edc5-15c9-4171-a174-ee15b895f54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985258141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.985258141
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.304332618
Short name T237
Test name
Test status
Simulation time 240960655 ps
CPU time 1.33 seconds
Started Jul 20 04:35:42 PM PDT 24
Finished Jul 20 04:35:44 PM PDT 24
Peak memory 195892 kb
Host smart-d4fc6a67-8fb0-4684-a377-7a7d89680817
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304332618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.304332618
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.567775757
Short name T250
Test name
Test status
Simulation time 10967413677 ps
CPU time 73.1 seconds
Started Jul 20 04:35:43 PM PDT 24
Finished Jul 20 04:36:58 PM PDT 24
Peak memory 198200 kb
Host smart-0ae78107-98a9-43de-96bb-153f2f2add12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567775757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.567775757
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.1741039565
Short name T427
Test name
Test status
Simulation time 251168016 ps
CPU time 0.56 seconds
Started Jul 20 04:34:03 PM PDT 24
Finished Jul 20 04:34:04 PM PDT 24
Peak memory 194280 kb
Host smart-03134ec7-342e-44a2-a9d6-0824748d6f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741039565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.1741039565
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.413522095
Short name T602
Test name
Test status
Simulation time 23635455 ps
CPU time 0.7 seconds
Started Jul 20 04:33:56 PM PDT 24
Finished Jul 20 04:33:57 PM PDT 24
Peak memory 194280 kb
Host smart-8fc38b1d-b32f-42af-a3de-5a552fb046cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413522095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.413522095
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.2995248870
Short name T372
Test name
Test status
Simulation time 478296504 ps
CPU time 23.79 seconds
Started Jul 20 04:34:05 PM PDT 24
Finished Jul 20 04:34:29 PM PDT 24
Peak memory 196348 kb
Host smart-1b604a1e-33fb-4d7f-9d9e-d115596ddd41
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995248870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.2995248870
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2962514809
Short name T422
Test name
Test status
Simulation time 308277432 ps
CPU time 0.93 seconds
Started Jul 20 04:34:05 PM PDT 24
Finished Jul 20 04:34:07 PM PDT 24
Peak memory 198044 kb
Host smart-d2966985-6300-4ccf-a192-3ec71791bee4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962514809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2962514809
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3282837119
Short name T494
Test name
Test status
Simulation time 22513111 ps
CPU time 0.66 seconds
Started Jul 20 04:34:05 PM PDT 24
Finished Jul 20 04:34:06 PM PDT 24
Peak memory 194396 kb
Host smart-447ba4b4-9477-44f8-bad1-7b2f8b8bf7fc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282837119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3282837119
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1458607873
Short name T228
Test name
Test status
Simulation time 757539700 ps
CPU time 2.76 seconds
Started Jul 20 04:34:07 PM PDT 24
Finished Jul 20 04:34:10 PM PDT 24
Peak memory 198160 kb
Host smart-70ecd699-77ef-4208-a9c9-7c6f16bdf5e6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458607873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1458607873
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3867422834
Short name T538
Test name
Test status
Simulation time 125360332 ps
CPU time 2.46 seconds
Started Jul 20 04:34:03 PM PDT 24
Finished Jul 20 04:34:06 PM PDT 24
Peak memory 198280 kb
Host smart-c9f50085-7d09-4cdf-bd9a-a8de31617044
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867422834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3867422834
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.796425535
Short name T604
Test name
Test status
Simulation time 150279426 ps
CPU time 0.95 seconds
Started Jul 20 04:33:54 PM PDT 24
Finished Jul 20 04:33:56 PM PDT 24
Peak memory 196812 kb
Host smart-33166d0b-6bcc-4d7f-81ce-42013e1b1829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796425535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.796425535
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.876911914
Short name T708
Test name
Test status
Simulation time 30994027 ps
CPU time 0.63 seconds
Started Jul 20 04:33:55 PM PDT 24
Finished Jul 20 04:33:56 PM PDT 24
Peak memory 195000 kb
Host smart-1779c78d-9bc1-42b9-bf19-439fe1bd94ce
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876911914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.876911914
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1819506195
Short name T184
Test name
Test status
Simulation time 2019888855 ps
CPU time 4.23 seconds
Started Jul 20 04:34:05 PM PDT 24
Finished Jul 20 04:34:10 PM PDT 24
Peak memory 197996 kb
Host smart-b5fdac7c-37ff-45de-9d2f-43e12f418875
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819506195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1819506195
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2288969166
Short name T39
Test name
Test status
Simulation time 62636600 ps
CPU time 0.83 seconds
Started Jul 20 04:34:04 PM PDT 24
Finished Jul 20 04:34:05 PM PDT 24
Peak memory 214880 kb
Host smart-23a99835-d9b8-47ee-90ee-9d657643b276
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288969166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2288969166
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1372994316
Short name T398
Test name
Test status
Simulation time 135815056 ps
CPU time 1.14 seconds
Started Jul 20 04:33:54 PM PDT 24
Finished Jul 20 04:33:56 PM PDT 24
Peak memory 198156 kb
Host smart-8c3df8db-0bf3-499d-bc5d-33ed59014e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372994316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1372994316
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2079168938
Short name T459
Test name
Test status
Simulation time 314344207 ps
CPU time 1.2 seconds
Started Jul 20 04:33:59 PM PDT 24
Finished Jul 20 04:34:01 PM PDT 24
Peak memory 196924 kb
Host smart-df85b3e5-5778-472c-9b23-2f9aca09695d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079168938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2079168938
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2227581507
Short name T203
Test name
Test status
Simulation time 5484919701 ps
CPU time 137.22 seconds
Started Jul 20 04:34:02 PM PDT 24
Finished Jul 20 04:36:20 PM PDT 24
Peak memory 198284 kb
Host smart-6590fbd1-039c-4027-868a-f8ebaf153204
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227581507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2227581507
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3727575148
Short name T65
Test name
Test status
Simulation time 92356419734 ps
CPU time 835.51 seconds
Started Jul 20 04:34:04 PM PDT 24
Finished Jul 20 04:48:00 PM PDT 24
Peak memory 198400 kb
Host smart-ecf14e55-7e74-4726-8ed9-5c0b416ae9a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3727575148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3727575148
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.831477604
Short name T280
Test name
Test status
Simulation time 28996021 ps
CPU time 0.56 seconds
Started Jul 20 04:35:51 PM PDT 24
Finished Jul 20 04:35:52 PM PDT 24
Peak memory 194064 kb
Host smart-a952f391-ad3e-4219-a557-ecaaf952ff74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831477604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.831477604
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1874143226
Short name T132
Test name
Test status
Simulation time 18655984 ps
CPU time 0.66 seconds
Started Jul 20 04:35:43 PM PDT 24
Finished Jul 20 04:35:46 PM PDT 24
Peak memory 194648 kb
Host smart-b19a2e55-22c0-4d7e-a949-1cb0b47a7e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874143226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1874143226
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.1611192538
Short name T334
Test name
Test status
Simulation time 188373553 ps
CPU time 10.13 seconds
Started Jul 20 04:35:40 PM PDT 24
Finished Jul 20 04:35:51 PM PDT 24
Peak memory 197124 kb
Host smart-55827a09-aef3-4ddc-8663-46106d751036
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611192538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.1611192538
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2412543817
Short name T194
Test name
Test status
Simulation time 46616933 ps
CPU time 0.8 seconds
Started Jul 20 04:35:43 PM PDT 24
Finished Jul 20 04:35:45 PM PDT 24
Peak memory 196084 kb
Host smart-ba353945-c5ab-4813-a1c4-eae58572b829
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412543817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2412543817
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2896607691
Short name T293
Test name
Test status
Simulation time 1153333026 ps
CPU time 1.27 seconds
Started Jul 20 04:35:42 PM PDT 24
Finished Jul 20 04:35:44 PM PDT 24
Peak memory 196204 kb
Host smart-d1b8fdf5-455d-4ede-8908-1694bd5a3360
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896607691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2896607691
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.2756798228
Short name T514
Test name
Test status
Simulation time 91544303 ps
CPU time 3.17 seconds
Started Jul 20 04:35:47 PM PDT 24
Finished Jul 20 04:35:51 PM PDT 24
Peak memory 198144 kb
Host smart-ebca7c70-1df2-4879-b16e-d3748e6bcbd9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756798228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.2756798228
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.3332367094
Short name T654
Test name
Test status
Simulation time 1246555432 ps
CPU time 3.08 seconds
Started Jul 20 04:35:41 PM PDT 24
Finished Jul 20 04:35:46 PM PDT 24
Peak memory 198196 kb
Host smart-ed060bfe-4e9c-4682-9592-5e34bcf8d685
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332367094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.3332367094
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3128130201
Short name T689
Test name
Test status
Simulation time 70206462 ps
CPU time 0.87 seconds
Started Jul 20 04:35:44 PM PDT 24
Finished Jul 20 04:35:46 PM PDT 24
Peak memory 197436 kb
Host smart-0d23ab93-bf44-4974-9c25-64933d8102c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128130201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3128130201
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3785649408
Short name T247
Test name
Test status
Simulation time 28043740 ps
CPU time 1.02 seconds
Started Jul 20 04:35:44 PM PDT 24
Finished Jul 20 04:35:46 PM PDT 24
Peak memory 196100 kb
Host smart-391263bf-a0df-4e99-9a12-05946607456e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785649408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3785649408
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2907747738
Short name T476
Test name
Test status
Simulation time 265077992 ps
CPU time 2.01 seconds
Started Jul 20 04:35:42 PM PDT 24
Finished Jul 20 04:35:46 PM PDT 24
Peak memory 198168 kb
Host smart-c51bfbe4-f9b5-40c4-8090-4cdf712d185f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907747738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2907747738
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3406904864
Short name T577
Test name
Test status
Simulation time 81430001 ps
CPU time 1.31 seconds
Started Jul 20 04:35:45 PM PDT 24
Finished Jul 20 04:35:47 PM PDT 24
Peak memory 195928 kb
Host smart-3585e012-f0f2-4b38-af5e-bee108aa37dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406904864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3406904864
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3596542064
Short name T690
Test name
Test status
Simulation time 158474876 ps
CPU time 0.96 seconds
Started Jul 20 04:35:43 PM PDT 24
Finished Jul 20 04:35:46 PM PDT 24
Peak memory 195952 kb
Host smart-43e16bc1-f885-4d28-a062-41d6eb0bbf85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596542064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3596542064
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.952619193
Short name T329
Test name
Test status
Simulation time 25312068653 ps
CPU time 158.53 seconds
Started Jul 20 04:35:43 PM PDT 24
Finished Jul 20 04:38:23 PM PDT 24
Peak memory 198144 kb
Host smart-3136ff98-adb3-447b-a936-69ac51edbef9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952619193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.952619193
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.3559271564
Short name T531
Test name
Test status
Simulation time 29768995745 ps
CPU time 765.76 seconds
Started Jul 20 04:35:53 PM PDT 24
Finished Jul 20 04:48:40 PM PDT 24
Peak memory 198312 kb
Host smart-a6b8c7a3-9c0f-4685-890c-1ab296eed1c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3559271564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.3559271564
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.519630564
Short name T365
Test name
Test status
Simulation time 21506233 ps
CPU time 0.69 seconds
Started Jul 20 04:35:52 PM PDT 24
Finished Jul 20 04:35:53 PM PDT 24
Peak memory 195052 kb
Host smart-e3dca60c-0e16-406e-b28d-61124ae89e66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519630564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.519630564
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2064798825
Short name T392
Test name
Test status
Simulation time 153649762 ps
CPU time 0.91 seconds
Started Jul 20 04:35:51 PM PDT 24
Finished Jul 20 04:35:53 PM PDT 24
Peak memory 196012 kb
Host smart-ff09b0e4-8deb-4e97-92f0-72a8410f7093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064798825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2064798825
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1155730254
Short name T584
Test name
Test status
Simulation time 596409563 ps
CPU time 16.12 seconds
Started Jul 20 04:35:53 PM PDT 24
Finished Jul 20 04:36:10 PM PDT 24
Peak memory 196620 kb
Host smart-a345c506-5dc3-4409-bdb7-7de6c2214c2a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155730254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1155730254
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.627867396
Short name T665
Test name
Test status
Simulation time 58095887 ps
CPU time 0.84 seconds
Started Jul 20 04:35:53 PM PDT 24
Finished Jul 20 04:35:55 PM PDT 24
Peak memory 195984 kb
Host smart-5a6c8585-eb77-4bf1-9321-6f2559ec38a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627867396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.627867396
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1642300379
Short name T196
Test name
Test status
Simulation time 83519693 ps
CPU time 0.96 seconds
Started Jul 20 04:35:53 PM PDT 24
Finished Jul 20 04:35:55 PM PDT 24
Peak memory 196592 kb
Host smart-98b64994-725b-4314-bec4-8c64a2375a36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642300379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1642300379
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.3481774480
Short name T274
Test name
Test status
Simulation time 25066034 ps
CPU time 1.09 seconds
Started Jul 20 04:35:50 PM PDT 24
Finished Jul 20 04:35:52 PM PDT 24
Peak memory 197408 kb
Host smart-a801d8ef-0cfe-4d0e-92c5-40dd5f547557
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481774480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.3481774480
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.915016082
Short name T22
Test name
Test status
Simulation time 143359719 ps
CPU time 3.09 seconds
Started Jul 20 04:35:52 PM PDT 24
Finished Jul 20 04:35:56 PM PDT 24
Peak memory 197052 kb
Host smart-d0d63ccc-d636-4236-99bd-9b6b93218d1a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915016082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
915016082
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1739477518
Short name T232
Test name
Test status
Simulation time 27742125 ps
CPU time 1.04 seconds
Started Jul 20 04:35:51 PM PDT 24
Finished Jul 20 04:35:53 PM PDT 24
Peak memory 196104 kb
Host smart-50133a3e-236f-4a9b-849b-8ffaac6fbf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739477518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1739477518
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.489985661
Short name T284
Test name
Test status
Simulation time 142130313 ps
CPU time 1.06 seconds
Started Jul 20 04:35:52 PM PDT 24
Finished Jul 20 04:35:54 PM PDT 24
Peak memory 196216 kb
Host smart-223b67b3-3d0f-41ad-bcb9-22145fd35def
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489985661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.489985661
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3075595316
Short name T167
Test name
Test status
Simulation time 69847454 ps
CPU time 1.37 seconds
Started Jul 20 04:35:51 PM PDT 24
Finished Jul 20 04:35:54 PM PDT 24
Peak memory 198036 kb
Host smart-ac4a6cbf-1b49-4d86-b9f7-636296ac4a1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075595316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3075595316
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.1642822893
Short name T622
Test name
Test status
Simulation time 52761249 ps
CPU time 0.92 seconds
Started Jul 20 04:35:52 PM PDT 24
Finished Jul 20 04:35:54 PM PDT 24
Peak memory 196672 kb
Host smart-d10fde3f-cbb3-4b58-be02-9b4e470fa952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642822893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.1642822893
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1595191812
Short name T110
Test name
Test status
Simulation time 183990268 ps
CPU time 0.91 seconds
Started Jul 20 04:35:51 PM PDT 24
Finished Jul 20 04:35:53 PM PDT 24
Peak memory 195836 kb
Host smart-a95c5908-1938-4cc9-99c8-d91e0ad1e14a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595191812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1595191812
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2888804730
Short name T155
Test name
Test status
Simulation time 4864348186 ps
CPU time 29.55 seconds
Started Jul 20 04:35:51 PM PDT 24
Finished Jul 20 04:36:21 PM PDT 24
Peak memory 198196 kb
Host smart-8f31b294-1c33-48ab-bce8-83f1ad0d469f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888804730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2888804730
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.4181761841
Short name T66
Test name
Test status
Simulation time 138630082572 ps
CPU time 3008.3 seconds
Started Jul 20 04:35:52 PM PDT 24
Finished Jul 20 05:26:02 PM PDT 24
Peak memory 198376 kb
Host smart-fe7b98b0-cff3-4e8f-99b8-bf370d8276e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4181761841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.4181761841
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3307123563
Short name T321
Test name
Test status
Simulation time 36422204 ps
CPU time 0.54 seconds
Started Jul 20 04:35:50 PM PDT 24
Finished Jul 20 04:35:52 PM PDT 24
Peak memory 194104 kb
Host smart-07d46651-aabd-4001-a79f-e7e338c0bae0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307123563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3307123563
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3727859824
Short name T618
Test name
Test status
Simulation time 105897561 ps
CPU time 0.62 seconds
Started Jul 20 04:35:50 PM PDT 24
Finished Jul 20 04:35:51 PM PDT 24
Peak memory 194860 kb
Host smart-16af5637-f46a-4a95-b946-3f23c597d8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727859824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3727859824
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.4286729849
Short name T14
Test name
Test status
Simulation time 914901633 ps
CPU time 22.23 seconds
Started Jul 20 04:35:49 PM PDT 24
Finished Jul 20 04:36:12 PM PDT 24
Peak memory 196932 kb
Host smart-3df02a4f-3be2-4428-b550-c337d975b2fb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286729849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.4286729849
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.463250078
Short name T664
Test name
Test status
Simulation time 33673935 ps
CPU time 0.64 seconds
Started Jul 20 04:35:50 PM PDT 24
Finished Jul 20 04:35:52 PM PDT 24
Peak memory 194360 kb
Host smart-722d0ef0-a7dd-49dc-93c6-3281c0c8309c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463250078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.463250078
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.4031380117
Short name T429
Test name
Test status
Simulation time 126795710 ps
CPU time 0.74 seconds
Started Jul 20 04:35:53 PM PDT 24
Finished Jul 20 04:35:55 PM PDT 24
Peak memory 196188 kb
Host smart-c3a65f82-c676-44a2-82e9-75e4f333f805
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031380117 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.4031380117
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.430669824
Short name T522
Test name
Test status
Simulation time 1261681417 ps
CPU time 2.73 seconds
Started Jul 20 04:35:54 PM PDT 24
Finished Jul 20 04:35:57 PM PDT 24
Peak memory 198168 kb
Host smart-4902699e-4c15-462e-82c2-af33e9f9aede
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430669824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 42.gpio_intr_with_filter_rand_intr_event.430669824
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1576283198
Short name T433
Test name
Test status
Simulation time 239912691 ps
CPU time 1.96 seconds
Started Jul 20 04:35:51 PM PDT 24
Finished Jul 20 04:35:54 PM PDT 24
Peak memory 196692 kb
Host smart-d5b24fa3-4340-41b9-ad08-974316525e83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576283198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1576283198
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.615163860
Short name T711
Test name
Test status
Simulation time 35057393 ps
CPU time 1.21 seconds
Started Jul 20 04:35:54 PM PDT 24
Finished Jul 20 04:35:56 PM PDT 24
Peak memory 197176 kb
Host smart-5456b83c-1184-4853-ab43-1a836dd7442e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615163860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.615163860
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.1227394205
Short name T227
Test name
Test status
Simulation time 110793189 ps
CPU time 0.8 seconds
Started Jul 20 04:35:55 PM PDT 24
Finished Jul 20 04:35:56 PM PDT 24
Peak memory 195548 kb
Host smart-2bf1e569-9c1f-4f02-ace0-e13747406d95
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227394205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.1227394205
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2490349989
Short name T7
Test name
Test status
Simulation time 345405374 ps
CPU time 2.66 seconds
Started Jul 20 04:35:52 PM PDT 24
Finished Jul 20 04:35:56 PM PDT 24
Peak memory 198056 kb
Host smart-a88f056f-c2bb-4ad1-ae5c-400d4160feb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490349989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2490349989
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3520487764
Short name T201
Test name
Test status
Simulation time 41042350 ps
CPU time 1.2 seconds
Started Jul 20 04:35:49 PM PDT 24
Finished Jul 20 04:35:51 PM PDT 24
Peak memory 196992 kb
Host smart-8caf09d7-44d0-4e2c-aa52-d28c3c12da0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520487764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3520487764
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3379887669
Short name T245
Test name
Test status
Simulation time 324683358 ps
CPU time 1.4 seconds
Started Jul 20 04:35:54 PM PDT 24
Finished Jul 20 04:35:56 PM PDT 24
Peak memory 195640 kb
Host smart-21ae8698-2eb9-4989-a92e-a780d012dbe1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379887669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3379887669
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.2810878430
Short name T450
Test name
Test status
Simulation time 46578038649 ps
CPU time 124.98 seconds
Started Jul 20 04:35:49 PM PDT 24
Finished Jul 20 04:37:55 PM PDT 24
Peak memory 198252 kb
Host smart-c056776d-fd28-4d98-95a4-c4c10cac8603
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810878430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.2810878430
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2511007397
Short name T68
Test name
Test status
Simulation time 118305013449 ps
CPU time 1254.53 seconds
Started Jul 20 04:35:52 PM PDT 24
Finished Jul 20 04:56:47 PM PDT 24
Peak memory 198344 kb
Host smart-5d68ec23-a21a-47e7-82d4-aec731a2ef34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2511007397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2511007397
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.2589719954
Short name T262
Test name
Test status
Simulation time 35977315 ps
CPU time 0.59 seconds
Started Jul 20 04:36:04 PM PDT 24
Finished Jul 20 04:36:07 PM PDT 24
Peak memory 194024 kb
Host smart-29b4acbf-bba2-407d-b204-df38d1b2ae3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589719954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.2589719954
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2061521605
Short name T518
Test name
Test status
Simulation time 16874359 ps
CPU time 0.65 seconds
Started Jul 20 04:36:01 PM PDT 24
Finished Jul 20 04:36:03 PM PDT 24
Peak memory 194864 kb
Host smart-652a3572-ecf3-499b-af68-618d166400b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061521605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2061521605
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.3469277297
Short name T721
Test name
Test status
Simulation time 2404575225 ps
CPU time 22.45 seconds
Started Jul 20 04:36:06 PM PDT 24
Finished Jul 20 04:36:30 PM PDT 24
Peak memory 195824 kb
Host smart-38595f31-d748-45d9-b7f1-5f84fba74060
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469277297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.3469277297
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.3012592892
Short name T453
Test name
Test status
Simulation time 79327840 ps
CPU time 1.03 seconds
Started Jul 20 04:36:03 PM PDT 24
Finished Jul 20 04:36:06 PM PDT 24
Peak memory 196560 kb
Host smart-9b22b70d-c03c-4a9b-b1cd-dac491a3e6c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012592892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.3012592892
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2596483393
Short name T442
Test name
Test status
Simulation time 642975869 ps
CPU time 1.49 seconds
Started Jul 20 04:35:59 PM PDT 24
Finished Jul 20 04:36:02 PM PDT 24
Peak memory 197388 kb
Host smart-8575ce74-cfda-4a27-b371-1a11a16ee496
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596483393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2596483393
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2911003886
Short name T62
Test name
Test status
Simulation time 944589379 ps
CPU time 2.33 seconds
Started Jul 20 04:36:04 PM PDT 24
Finished Jul 20 04:36:08 PM PDT 24
Peak memory 197372 kb
Host smart-2b3079e5-cfe4-4068-9186-0bbb5aedadb6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911003886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2911003886
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.109467341
Short name T294
Test name
Test status
Simulation time 36445505 ps
CPU time 1.35 seconds
Started Jul 20 04:36:00 PM PDT 24
Finished Jul 20 04:36:03 PM PDT 24
Peak memory 196960 kb
Host smart-6c46c5f3-76bf-4bdd-a977-b0205cc70bff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109467341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
109467341
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3688039763
Short name T473
Test name
Test status
Simulation time 85061033 ps
CPU time 0.96 seconds
Started Jul 20 04:36:04 PM PDT 24
Finished Jul 20 04:36:07 PM PDT 24
Peak memory 196156 kb
Host smart-0315842f-1119-4517-a50b-3089914f4d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688039763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3688039763
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.2881257768
Short name T669
Test name
Test status
Simulation time 97073828 ps
CPU time 1.09 seconds
Started Jul 20 04:35:59 PM PDT 24
Finished Jul 20 04:36:00 PM PDT 24
Peak memory 196920 kb
Host smart-b9776285-36dc-4883-aefd-fad6b9b96f0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881257768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.2881257768
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.1888070874
Short name T399
Test name
Test status
Simulation time 128194381 ps
CPU time 5.23 seconds
Started Jul 20 04:36:03 PM PDT 24
Finished Jul 20 04:36:10 PM PDT 24
Peak memory 198044 kb
Host smart-60d43960-ef46-4598-a656-734a12720b7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888070874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.1888070874
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.635823840
Short name T566
Test name
Test status
Simulation time 161546672 ps
CPU time 0.82 seconds
Started Jul 20 04:35:50 PM PDT 24
Finished Jul 20 04:35:51 PM PDT 24
Peak memory 195508 kb
Host smart-aab73102-2318-44c8-83e3-0247edbe2f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635823840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.635823840
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.1940899384
Short name T713
Test name
Test status
Simulation time 42465801 ps
CPU time 0.96 seconds
Started Jul 20 04:36:02 PM PDT 24
Finished Jul 20 04:36:05 PM PDT 24
Peak memory 196348 kb
Host smart-65fcfc39-4690-4682-a6b3-acdd2f9f5c5c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940899384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.1940899384
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.363795336
Short name T273
Test name
Test status
Simulation time 22917052443 ps
CPU time 99.14 seconds
Started Jul 20 04:36:03 PM PDT 24
Finished Jul 20 04:37:44 PM PDT 24
Peak memory 198228 kb
Host smart-d95e89b3-519d-4a0b-9e28-7b7ecfa702bf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363795336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.363795336
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2799816500
Short name T315
Test name
Test status
Simulation time 23718906 ps
CPU time 0.57 seconds
Started Jul 20 04:36:01 PM PDT 24
Finished Jul 20 04:36:04 PM PDT 24
Peak memory 194808 kb
Host smart-cea7d7f8-3f3b-4b2e-a418-becfd09e71e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799816500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2799816500
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.374408649
Short name T181
Test name
Test status
Simulation time 21596267 ps
CPU time 0.66 seconds
Started Jul 20 04:36:00 PM PDT 24
Finished Jul 20 04:36:01 PM PDT 24
Peak memory 194196 kb
Host smart-d1e4f579-c62f-44d8-bd34-dc7ed2914153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374408649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.374408649
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1556537219
Short name T666
Test name
Test status
Simulation time 924945219 ps
CPU time 12.15 seconds
Started Jul 20 04:36:00 PM PDT 24
Finished Jul 20 04:36:14 PM PDT 24
Peak memory 196636 kb
Host smart-d375fbf3-b6cc-40bd-8805-95d9090cad4a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556537219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1556537219
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.4270361157
Short name T134
Test name
Test status
Simulation time 344304805 ps
CPU time 1.12 seconds
Started Jul 20 04:35:59 PM PDT 24
Finished Jul 20 04:36:02 PM PDT 24
Peak memory 196836 kb
Host smart-52665c56-c4b2-495f-b97d-88bd426f08bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270361157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.4270361157
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3391699638
Short name T549
Test name
Test status
Simulation time 269032112 ps
CPU time 1.04 seconds
Started Jul 20 04:36:04 PM PDT 24
Finished Jul 20 04:36:07 PM PDT 24
Peak memory 196076 kb
Host smart-cf6398f6-e326-458c-9505-ce8651992136
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391699638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3391699638
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.75132639
Short name T163
Test name
Test status
Simulation time 45784375 ps
CPU time 1.89 seconds
Started Jul 20 04:36:03 PM PDT 24
Finished Jul 20 04:36:08 PM PDT 24
Peak memory 197908 kb
Host smart-b5e211b7-8376-4742-83ad-45107cd2a930
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75132639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 44.gpio_intr_with_filter_rand_intr_event.75132639
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2335589898
Short name T493
Test name
Test status
Simulation time 451331817 ps
CPU time 2.5 seconds
Started Jul 20 04:36:05 PM PDT 24
Finished Jul 20 04:36:10 PM PDT 24
Peak memory 196892 kb
Host smart-62e38e85-bae5-4a66-b10d-caefa6e60aef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335589898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2335589898
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.2728091046
Short name T275
Test name
Test status
Simulation time 38425517 ps
CPU time 0.75 seconds
Started Jul 20 04:36:03 PM PDT 24
Finished Jul 20 04:36:06 PM PDT 24
Peak memory 195452 kb
Host smart-c8ce150b-ea5d-4ca9-babb-3e6ddef93ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728091046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.2728091046
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.244643069
Short name T543
Test name
Test status
Simulation time 80874555 ps
CPU time 0.99 seconds
Started Jul 20 04:36:02 PM PDT 24
Finished Jul 20 04:36:05 PM PDT 24
Peak memory 195884 kb
Host smart-d63c097d-f1b6-452b-bf7c-a83fc0dfb432
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244643069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.244643069
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.2438487409
Short name T306
Test name
Test status
Simulation time 436576426 ps
CPU time 3.86 seconds
Started Jul 20 04:36:06 PM PDT 24
Finished Jul 20 04:36:11 PM PDT 24
Peak memory 198056 kb
Host smart-5fbb42e5-ff72-4234-92ce-fa575394f642
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438487409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.2438487409
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.2863694799
Short name T578
Test name
Test status
Simulation time 416890384 ps
CPU time 1.28 seconds
Started Jul 20 04:36:01 PM PDT 24
Finished Jul 20 04:36:05 PM PDT 24
Peak memory 196636 kb
Host smart-81dcbce4-cb82-4dda-948c-e07b63396075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863694799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.2863694799
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.675251916
Short name T612
Test name
Test status
Simulation time 195924567 ps
CPU time 1.31 seconds
Started Jul 20 04:36:01 PM PDT 24
Finished Jul 20 04:36:05 PM PDT 24
Peak memory 198152 kb
Host smart-c8d52d23-d971-4197-80c5-1c53e1d310f0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675251916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.675251916
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3362783158
Short name T700
Test name
Test status
Simulation time 19746888587 ps
CPU time 199.17 seconds
Started Jul 20 04:36:02 PM PDT 24
Finished Jul 20 04:39:24 PM PDT 24
Peak memory 198168 kb
Host smart-6de2a56e-1cbb-4a60-a74f-e8eded49fa29
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362783158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3362783158
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.4028041297
Short name T238
Test name
Test status
Simulation time 50666361 ps
CPU time 0.59 seconds
Started Jul 20 04:36:05 PM PDT 24
Finished Jul 20 04:36:08 PM PDT 24
Peak memory 194256 kb
Host smart-003df13e-71cf-4f61-8a62-a02fb20ca6cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028041297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.4028041297
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.165887136
Short name T182
Test name
Test status
Simulation time 190557005 ps
CPU time 0.82 seconds
Started Jul 20 04:36:03 PM PDT 24
Finished Jul 20 04:36:06 PM PDT 24
Peak memory 196348 kb
Host smart-c25b90d5-5c6c-434d-88a1-de8883374fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165887136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.165887136
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1108341642
Short name T623
Test name
Test status
Simulation time 755659467 ps
CPU time 26.97 seconds
Started Jul 20 04:36:00 PM PDT 24
Finished Jul 20 04:36:28 PM PDT 24
Peak memory 196932 kb
Host smart-34d6edea-7e95-4fac-bc12-ac387d19f955
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108341642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1108341642
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3312938459
Short name T256
Test name
Test status
Simulation time 146272639 ps
CPU time 1 seconds
Started Jul 20 04:36:01 PM PDT 24
Finished Jul 20 04:36:04 PM PDT 24
Peak memory 197244 kb
Host smart-bc510379-c1ee-4595-aca4-74a9bf457d62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312938459 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3312938459
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.4251084579
Short name T61
Test name
Test status
Simulation time 86716728 ps
CPU time 1.44 seconds
Started Jul 20 04:36:01 PM PDT 24
Finished Jul 20 04:36:05 PM PDT 24
Peak memory 197020 kb
Host smart-296c95e1-bf7a-4bfc-8434-faee35506118
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251084579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.4251084579
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2860304296
Short name T444
Test name
Test status
Simulation time 146075509 ps
CPU time 2.84 seconds
Started Jul 20 04:36:03 PM PDT 24
Finished Jul 20 04:36:09 PM PDT 24
Peak memory 198164 kb
Host smart-de917b2e-4a88-4cc4-9ca1-273cf94a63c1
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860304296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2860304296
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.3692543562
Short name T130
Test name
Test status
Simulation time 910614731 ps
CPU time 3.18 seconds
Started Jul 20 04:36:01 PM PDT 24
Finished Jul 20 04:36:06 PM PDT 24
Peak memory 195952 kb
Host smart-130eaf00-0e42-418d-a97d-fd2946d67d8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692543562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.3692543562
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.1660794848
Short name T404
Test name
Test status
Simulation time 232193238 ps
CPU time 1.39 seconds
Started Jul 20 04:36:01 PM PDT 24
Finished Jul 20 04:36:04 PM PDT 24
Peak memory 195916 kb
Host smart-0762b1ec-e4a8-4961-91f2-30ecec9d3733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660794848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.1660794848
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3500326638
Short name T421
Test name
Test status
Simulation time 72409245 ps
CPU time 1.39 seconds
Started Jul 20 04:36:03 PM PDT 24
Finished Jul 20 04:36:07 PM PDT 24
Peak memory 198056 kb
Host smart-51046e83-f485-4b34-992c-aaba0589816e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500326638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3500326638
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.994413914
Short name T441
Test name
Test status
Simulation time 1091668485 ps
CPU time 4.54 seconds
Started Jul 20 04:36:00 PM PDT 24
Finished Jul 20 04:36:05 PM PDT 24
Peak memory 198112 kb
Host smart-6591a9ff-78d9-4eec-9d9d-771df762d1ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994413914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ran
dom_long_reg_writes_reg_reads.994413914
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2002525609
Short name T502
Test name
Test status
Simulation time 35713717 ps
CPU time 0.86 seconds
Started Jul 20 04:36:00 PM PDT 24
Finished Jul 20 04:36:02 PM PDT 24
Peak memory 196088 kb
Host smart-70dd06c3-2281-4612-86ed-a0ab6585554d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002525609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2002525609
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3753755551
Short name T354
Test name
Test status
Simulation time 26771458 ps
CPU time 0.92 seconds
Started Jul 20 04:36:02 PM PDT 24
Finished Jul 20 04:36:06 PM PDT 24
Peak memory 195808 kb
Host smart-f136ba7c-5609-4cfa-9f63-5017d515be2b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753755551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3753755551
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.409103075
Short name T644
Test name
Test status
Simulation time 7488680209 ps
CPU time 202.56 seconds
Started Jul 20 04:36:04 PM PDT 24
Finished Jul 20 04:39:29 PM PDT 24
Peak memory 198220 kb
Host smart-cf731a5c-4adf-42ae-a934-631daaf5d51e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409103075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.g
pio_stress_all.409103075
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2078374312
Short name T660
Test name
Test status
Simulation time 19287209 ps
CPU time 0.58 seconds
Started Jul 20 04:36:04 PM PDT 24
Finished Jul 20 04:36:07 PM PDT 24
Peak memory 194280 kb
Host smart-70c683fe-557d-4395-8f55-570934b9cb1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078374312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2078374312
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.963912255
Short name T679
Test name
Test status
Simulation time 15523971 ps
CPU time 0.69 seconds
Started Jul 20 04:36:04 PM PDT 24
Finished Jul 20 04:36:07 PM PDT 24
Peak memory 194848 kb
Host smart-a755016a-82cf-426f-9dfe-e30f1ec820b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963912255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.963912255
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.4256794147
Short name T457
Test name
Test status
Simulation time 506714803 ps
CPU time 25.78 seconds
Started Jul 20 04:36:02 PM PDT 24
Finished Jul 20 04:36:30 PM PDT 24
Peak memory 196764 kb
Host smart-1a9f1b83-2f75-409e-9f79-46db0e8f0c22
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256794147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.4256794147
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.4287983351
Short name T424
Test name
Test status
Simulation time 233312783 ps
CPU time 0.82 seconds
Started Jul 20 04:36:01 PM PDT 24
Finished Jul 20 04:36:04 PM PDT 24
Peak memory 196832 kb
Host smart-2b2bd5ab-75ec-41b9-8ab5-69f63e6f7189
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287983351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.4287983351
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2354563398
Short name T520
Test name
Test status
Simulation time 418601712 ps
CPU time 1.48 seconds
Started Jul 20 04:36:03 PM PDT 24
Finished Jul 20 04:36:07 PM PDT 24
Peak memory 196668 kb
Host smart-8d97c22e-87d5-4ca8-bf18-578085db147d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354563398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2354563398
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1309860754
Short name T556
Test name
Test status
Simulation time 177300805 ps
CPU time 3.25 seconds
Started Jul 20 04:36:04 PM PDT 24
Finished Jul 20 04:36:10 PM PDT 24
Peak memory 198224 kb
Host smart-f4f6d2c4-4d7c-4c94-8c4f-c0c46fc53fd2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309860754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1309860754
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.2399097677
Short name T671
Test name
Test status
Simulation time 478536234 ps
CPU time 0.88 seconds
Started Jul 20 04:36:01 PM PDT 24
Finished Jul 20 04:36:04 PM PDT 24
Peak memory 194484 kb
Host smart-397fe3d1-e52b-4931-a465-fa33161fdff8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399097677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.2399097677
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.2954805641
Short name T339
Test name
Test status
Simulation time 255712441 ps
CPU time 0.79 seconds
Started Jul 20 04:36:01 PM PDT 24
Finished Jul 20 04:36:04 PM PDT 24
Peak memory 196496 kb
Host smart-4379d336-11a0-4be7-b972-c3708dc183f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954805641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.2954805641
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.3251519004
Short name T173
Test name
Test status
Simulation time 181254164 ps
CPU time 1.08 seconds
Started Jul 20 04:36:00 PM PDT 24
Finished Jul 20 04:36:02 PM PDT 24
Peak memory 196712 kb
Host smart-b12d7e4f-beff-4726-9dc5-ed65bd106575
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251519004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.3251519004
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.245195543
Short name T351
Test name
Test status
Simulation time 397895604 ps
CPU time 2.12 seconds
Started Jul 20 04:36:01 PM PDT 24
Finished Jul 20 04:36:06 PM PDT 24
Peak memory 198100 kb
Host smart-04bde0d2-7a00-4baa-bef4-81faeb8e43a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245195543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ran
dom_long_reg_writes_reg_reads.245195543
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.674875740
Short name T158
Test name
Test status
Simulation time 72544717 ps
CPU time 1.21 seconds
Started Jul 20 04:36:00 PM PDT 24
Finished Jul 20 04:36:02 PM PDT 24
Peak memory 195888 kb
Host smart-349b91f8-5aad-4fa4-9d21-6aa5402ae039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674875740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.674875740
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1573479525
Short name T511
Test name
Test status
Simulation time 45123220 ps
CPU time 0.92 seconds
Started Jul 20 04:36:03 PM PDT 24
Finished Jul 20 04:36:06 PM PDT 24
Peak memory 196480 kb
Host smart-dbb118b7-6202-4c90-a9c8-4f86e9e7ead1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573479525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1573479525
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.3765859379
Short name T668
Test name
Test status
Simulation time 26988568968 ps
CPU time 180.32 seconds
Started Jul 20 04:36:02 PM PDT 24
Finished Jul 20 04:39:05 PM PDT 24
Peak memory 198072 kb
Host smart-f260abde-df05-4796-a4a3-d3cf90bf6803
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765859379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.3765859379
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.1908229867
Short name T507
Test name
Test status
Simulation time 148452160 ps
CPU time 0.56 seconds
Started Jul 20 04:36:16 PM PDT 24
Finished Jul 20 04:36:18 PM PDT 24
Peak memory 194080 kb
Host smart-68685e4f-eecb-4e33-91ed-baec5a25a8f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908229867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.1908229867
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.2728600599
Short name T148
Test name
Test status
Simulation time 42205806 ps
CPU time 0.79 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:14 PM PDT 24
Peak memory 195352 kb
Host smart-a6340190-9ac2-4566-b18b-80f4df7a970c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728600599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.2728600599
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3485726020
Short name T452
Test name
Test status
Simulation time 574320824 ps
CPU time 8.67 seconds
Started Jul 20 04:36:13 PM PDT 24
Finished Jul 20 04:36:23 PM PDT 24
Peak memory 197108 kb
Host smart-6543b8b4-bfb1-4788-b88f-9608be56033e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485726020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3485726020
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.133871717
Short name T590
Test name
Test status
Simulation time 585879235 ps
CPU time 0.92 seconds
Started Jul 20 04:36:12 PM PDT 24
Finished Jul 20 04:36:14 PM PDT 24
Peak memory 197208 kb
Host smart-f614d304-dcea-4bd8-8e17-14604548ab31
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133871717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.133871717
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.554668765
Short name T303
Test name
Test status
Simulation time 287816018 ps
CPU time 1.14 seconds
Started Jul 20 04:36:15 PM PDT 24
Finished Jul 20 04:36:18 PM PDT 24
Peak memory 196296 kb
Host smart-d545d296-f7fd-4bcc-937f-ce51fae110dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554668765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.554668765
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3782640156
Short name T607
Test name
Test status
Simulation time 160368166 ps
CPU time 1.97 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:15 PM PDT 24
Peak memory 198156 kb
Host smart-634befb4-b3e3-45bb-a984-835c5f33a105
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782640156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3782640156
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.643136008
Short name T219
Test name
Test status
Simulation time 129412718 ps
CPU time 2.42 seconds
Started Jul 20 04:36:15 PM PDT 24
Finished Jul 20 04:36:19 PM PDT 24
Peak memory 195940 kb
Host smart-b485d172-74d8-47b1-a21b-da2e9ff8f1a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643136008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
643136008
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.3798528847
Short name T197
Test name
Test status
Simulation time 34013790 ps
CPU time 0.86 seconds
Started Jul 20 04:36:09 PM PDT 24
Finished Jul 20 04:36:10 PM PDT 24
Peak memory 196036 kb
Host smart-761b5360-5334-418b-956a-1f1ca346734c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798528847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.3798528847
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.849586352
Short name T286
Test name
Test status
Simulation time 29610258 ps
CPU time 1.15 seconds
Started Jul 20 04:36:12 PM PDT 24
Finished Jul 20 04:36:15 PM PDT 24
Peak memory 196068 kb
Host smart-0267cdd2-7d6e-4141-8b3a-f8e336b5549c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849586352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.849586352
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2985210978
Short name T350
Test name
Test status
Simulation time 2060975690 ps
CPU time 6.07 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:18 PM PDT 24
Peak memory 198088 kb
Host smart-af217a61-b01c-44b0-bf80-ff870987be3c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985210978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2985210978
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2764155284
Short name T423
Test name
Test status
Simulation time 48523230 ps
CPU time 1.27 seconds
Started Jul 20 04:36:04 PM PDT 24
Finished Jul 20 04:36:08 PM PDT 24
Peak memory 196084 kb
Host smart-60970872-0ee7-46e5-8663-5b8bfd9b9d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764155284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2764155284
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1335627553
Short name T401
Test name
Test status
Simulation time 27328767 ps
CPU time 0.97 seconds
Started Jul 20 04:36:10 PM PDT 24
Finished Jul 20 04:36:12 PM PDT 24
Peak memory 195892 kb
Host smart-72db0766-613e-41b0-b0e5-1afdfb21932f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335627553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1335627553
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1531423279
Short name T636
Test name
Test status
Simulation time 34597733610 ps
CPU time 108.13 seconds
Started Jul 20 04:36:10 PM PDT 24
Finished Jul 20 04:37:59 PM PDT 24
Peak memory 198304 kb
Host smart-5e24deef-1904-41d7-9274-bf05e7b7dfe0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531423279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1531423279
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3990784557
Short name T206
Test name
Test status
Simulation time 17056921 ps
CPU time 0.56 seconds
Started Jul 20 04:36:16 PM PDT 24
Finished Jul 20 04:36:18 PM PDT 24
Peak memory 194792 kb
Host smart-0cd039fd-2295-4529-8de8-015031b0fe6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990784557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3990784557
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1899962827
Short name T248
Test name
Test status
Simulation time 68871782 ps
CPU time 0.63 seconds
Started Jul 20 04:36:09 PM PDT 24
Finished Jul 20 04:36:11 PM PDT 24
Peak memory 194024 kb
Host smart-7615edf3-4e39-4f4a-b2b6-56f2ac33f0ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899962827 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1899962827
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3331238948
Short name T348
Test name
Test status
Simulation time 5226221313 ps
CPU time 25.82 seconds
Started Jul 20 04:36:13 PM PDT 24
Finished Jul 20 04:36:41 PM PDT 24
Peak memory 197588 kb
Host smart-e965a2b8-27f0-4e57-8f6d-ec06d04fdec5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331238948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3331238948
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.3161434562
Short name T717
Test name
Test status
Simulation time 36130963 ps
CPU time 0.65 seconds
Started Jul 20 04:36:12 PM PDT 24
Finished Jul 20 04:36:15 PM PDT 24
Peak memory 195100 kb
Host smart-89b108be-c014-41b7-a00d-36e6e38d90d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161434562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.3161434562
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.302674613
Short name T649
Test name
Test status
Simulation time 63447417 ps
CPU time 1.16 seconds
Started Jul 20 04:36:09 PM PDT 24
Finished Jul 20 04:36:11 PM PDT 24
Peak memory 196236 kb
Host smart-167d46ff-0613-49f4-a036-1c0f2cb5996c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302674613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.302674613
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.596784287
Short name T564
Test name
Test status
Simulation time 146186418 ps
CPU time 2.91 seconds
Started Jul 20 04:36:16 PM PDT 24
Finished Jul 20 04:36:20 PM PDT 24
Peak memory 198124 kb
Host smart-79a63d9b-4248-4a81-be98-207e2b7f26d3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596784287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.596784287
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3254756066
Short name T414
Test name
Test status
Simulation time 62860309 ps
CPU time 1.45 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:13 PM PDT 24
Peak memory 196720 kb
Host smart-db3cdb7f-53d0-432c-a904-48998b63c2b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254756066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3254756066
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.3927558240
Short name T405
Test name
Test status
Simulation time 32067123 ps
CPU time 0.65 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:14 PM PDT 24
Peak memory 195152 kb
Host smart-a7885396-1aa4-401d-a738-5e0ccd8e8a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927558240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.3927558240
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.848380285
Short name T236
Test name
Test status
Simulation time 72566938 ps
CPU time 1.02 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:14 PM PDT 24
Peak memory 196172 kb
Host smart-c52efd80-a62b-464f-8e6b-ef8efa7132c9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848380285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup
_pulldown.848380285
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.17939553
Short name T381
Test name
Test status
Simulation time 1357894932 ps
CPU time 4.76 seconds
Started Jul 20 04:36:10 PM PDT 24
Finished Jul 20 04:36:16 PM PDT 24
Peak memory 198084 kb
Host smart-70bda411-1976-4774-a0cb-ae7db94cddf1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17939553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand
om_long_reg_writes_reg_reads.17939553
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1984095976
Short name T397
Test name
Test status
Simulation time 110073618 ps
CPU time 0.82 seconds
Started Jul 20 04:36:10 PM PDT 24
Finished Jul 20 04:36:12 PM PDT 24
Peak memory 195240 kb
Host smart-ee151246-6df1-4d80-b5a3-16ffbaf53a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984095976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1984095976
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2005673546
Short name T592
Test name
Test status
Simulation time 49059537 ps
CPU time 1.02 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:13 PM PDT 24
Peak memory 195904 kb
Host smart-fb81962f-7e4b-46a2-aa16-d63fdbb1c308
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005673546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2005673546
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2548650947
Short name T629
Test name
Test status
Simulation time 848335400 ps
CPU time 21.77 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:34 PM PDT 24
Peak memory 198192 kb
Host smart-9b97c1ee-9f96-4212-832c-139486c1e425
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548650947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2548650947
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.2069976999
Short name T625
Test name
Test status
Simulation time 30128375734 ps
CPU time 398.32 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:42:51 PM PDT 24
Peak memory 198292 kb
Host smart-380a1209-d82a-4b7f-b2d8-a541af8dbdf7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2069976999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.2069976999
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.783255548
Short name T436
Test name
Test status
Simulation time 43394932 ps
CPU time 0.61 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:13 PM PDT 24
Peak memory 194040 kb
Host smart-ba3d5a90-72de-4b03-9aed-18328df5367c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783255548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.783255548
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.698976076
Short name T299
Test name
Test status
Simulation time 32150618 ps
CPU time 0.8 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:12 PM PDT 24
Peak memory 196256 kb
Host smart-7e4d6eb7-2660-4299-9d46-88381953623d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698976076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.698976076
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_full_random.1811214260
Short name T30
Test name
Test status
Simulation time 167176638 ps
CPU time 0.75 seconds
Started Jul 20 04:36:12 PM PDT 24
Finished Jul 20 04:36:15 PM PDT 24
Peak memory 195476 kb
Host smart-86eb5231-cc6a-45b8-8e92-dbb48fdbcfb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811214260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1811214260
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.663462709
Short name T416
Test name
Test status
Simulation time 228185595 ps
CPU time 1.04 seconds
Started Jul 20 04:36:14 PM PDT 24
Finished Jul 20 04:36:16 PM PDT 24
Peak memory 196788 kb
Host smart-5f1a1109-99c6-411d-9fa7-204818c75320
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663462709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.663462709
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1219176631
Short name T527
Test name
Test status
Simulation time 69940810 ps
CPU time 0.95 seconds
Started Jul 20 04:36:17 PM PDT 24
Finished Jul 20 04:36:19 PM PDT 24
Peak memory 196420 kb
Host smart-be86886e-1b85-4658-a44c-a7bf9dc11b0a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219176631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1219176631
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1652420255
Short name T651
Test name
Test status
Simulation time 432661195 ps
CPU time 3.12 seconds
Started Jul 20 04:36:10 PM PDT 24
Finished Jul 20 04:36:14 PM PDT 24
Peak memory 196696 kb
Host smart-7998ac42-df4e-4b88-bbfd-cd3b9520ae3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652420255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1652420255
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.200749200
Short name T628
Test name
Test status
Simulation time 83972128 ps
CPU time 0.78 seconds
Started Jul 20 04:36:12 PM PDT 24
Finished Jul 20 04:36:15 PM PDT 24
Peak memory 196172 kb
Host smart-7c364efa-4adb-4d45-9fc3-d5750bc7341c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200749200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.200749200
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3967789554
Short name T633
Test name
Test status
Simulation time 52992407 ps
CPU time 0.97 seconds
Started Jul 20 04:36:09 PM PDT 24
Finished Jul 20 04:36:11 PM PDT 24
Peak memory 196192 kb
Host smart-73caf775-e1ba-410d-9b46-6676fec24269
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967789554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3967789554
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.1332511347
Short name T263
Test name
Test status
Simulation time 2867291541 ps
CPU time 5.75 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:18 PM PDT 24
Peak memory 198160 kb
Host smart-6d06701e-3723-4757-afb5-b7e03f12a7cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332511347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.1332511347
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.281639451
Short name T675
Test name
Test status
Simulation time 165715874 ps
CPU time 0.98 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:36:13 PM PDT 24
Peak memory 196572 kb
Host smart-61bc124a-56ab-44e6-923e-c98eafb41da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281639451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.281639451
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3700499573
Short name T326
Test name
Test status
Simulation time 282532804 ps
CPU time 1.19 seconds
Started Jul 20 04:36:13 PM PDT 24
Finished Jul 20 04:36:16 PM PDT 24
Peak memory 196500 kb
Host smart-1da1a6a0-6177-4131-a0f4-b973f687a47d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700499573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3700499573
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3187172594
Short name T463
Test name
Test status
Simulation time 29319742649 ps
CPU time 168.69 seconds
Started Jul 20 04:36:11 PM PDT 24
Finished Jul 20 04:39:01 PM PDT 24
Peak memory 198272 kb
Host smart-203edb24-7ed4-43ff-b088-52630852f43c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187172594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3187172594
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.2831435775
Short name T723
Test name
Test status
Simulation time 124505538497 ps
CPU time 1994.91 seconds
Started Jul 20 04:36:10 PM PDT 24
Finished Jul 20 05:09:26 PM PDT 24
Peak memory 198336 kb
Host smart-a9d4f0a1-52fc-4c35-854f-8b859af6ba8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2831435775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.2831435775
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.793099614
Short name T333
Test name
Test status
Simulation time 22735913 ps
CPU time 0.55 seconds
Started Jul 20 04:34:13 PM PDT 24
Finished Jul 20 04:34:15 PM PDT 24
Peak memory 194752 kb
Host smart-018d141c-7472-44ef-9b19-d8cb18f66e18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793099614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.793099614
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3258688021
Short name T283
Test name
Test status
Simulation time 35199760 ps
CPU time 0.78 seconds
Started Jul 20 04:34:16 PM PDT 24
Finished Jul 20 04:34:17 PM PDT 24
Peak memory 195340 kb
Host smart-e3034b78-c507-4838-a36d-8372ab09682a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258688021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3258688021
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2183566110
Short name T619
Test name
Test status
Simulation time 812906211 ps
CPU time 10.66 seconds
Started Jul 20 04:34:13 PM PDT 24
Finished Jul 20 04:34:25 PM PDT 24
Peak memory 196808 kb
Host smart-0ef0aa03-13da-4008-a431-1ff2e733e013
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183566110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2183566110
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3422701603
Short name T231
Test name
Test status
Simulation time 56190688 ps
CPU time 0.79 seconds
Started Jul 20 04:34:15 PM PDT 24
Finished Jul 20 04:34:17 PM PDT 24
Peak memory 195768 kb
Host smart-b9eb463d-047b-46cc-ad91-6011b2efc27f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422701603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3422701603
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3208813350
Short name T596
Test name
Test status
Simulation time 121158387 ps
CPU time 1.02 seconds
Started Jul 20 04:34:13 PM PDT 24
Finished Jul 20 04:34:15 PM PDT 24
Peak memory 196116 kb
Host smart-77ae33ef-356f-449d-9bdc-ce1724b08c1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208813350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3208813350
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.164622471
Short name T558
Test name
Test status
Simulation time 63650629 ps
CPU time 2.45 seconds
Started Jul 20 04:34:13 PM PDT 24
Finished Jul 20 04:34:16 PM PDT 24
Peak memory 196372 kb
Host smart-5a9f33f4-3b96-46f9-9c14-415916a0feeb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164622471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.gpio_intr_with_filter_rand_intr_event.164622471
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.675992164
Short name T462
Test name
Test status
Simulation time 319065141 ps
CPU time 2.28 seconds
Started Jul 20 04:34:14 PM PDT 24
Finished Jul 20 04:34:18 PM PDT 24
Peak memory 195988 kb
Host smart-ec992d25-9583-4925-9bc7-faf149ddb79c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675992164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.675992164
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1427486169
Short name T379
Test name
Test status
Simulation time 33527505 ps
CPU time 1.12 seconds
Started Jul 20 04:34:20 PM PDT 24
Finished Jul 20 04:34:21 PM PDT 24
Peak memory 196816 kb
Host smart-0c16fa80-bfde-4647-8cc2-165882cd03c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427486169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1427486169
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1537231752
Short name T106
Test name
Test status
Simulation time 24357107 ps
CPU time 0.87 seconds
Started Jul 20 04:34:13 PM PDT 24
Finished Jul 20 04:34:15 PM PDT 24
Peak memory 196132 kb
Host smart-82b11514-4ed2-45c8-b69f-ba4228127e91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537231752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1537231752
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1437766503
Short name T297
Test name
Test status
Simulation time 1417115531 ps
CPU time 3.19 seconds
Started Jul 20 04:34:17 PM PDT 24
Finished Jul 20 04:34:21 PM PDT 24
Peak memory 198204 kb
Host smart-22ae75f1-6ff9-4186-b5c5-0095430ed41c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437766503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1437766503
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1275257895
Short name T648
Test name
Test status
Simulation time 301103143 ps
CPU time 1.21 seconds
Started Jul 20 04:34:15 PM PDT 24
Finished Jul 20 04:34:17 PM PDT 24
Peak memory 195656 kb
Host smart-3a3cb99d-3620-4fe9-9c62-8403d7f56d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275257895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1275257895
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1514859030
Short name T257
Test name
Test status
Simulation time 100798575 ps
CPU time 1.03 seconds
Started Jul 20 04:34:15 PM PDT 24
Finished Jul 20 04:34:17 PM PDT 24
Peak memory 196588 kb
Host smart-6407463c-0097-4be2-ae98-cae8579ca226
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514859030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1514859030
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1123736824
Short name T559
Test name
Test status
Simulation time 11621008592 ps
CPU time 145.1 seconds
Started Jul 20 04:34:14 PM PDT 24
Finished Jul 20 04:36:41 PM PDT 24
Peak memory 198196 kb
Host smart-d5129121-ccd0-4389-af75-ad6bc9d55023
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123736824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1123736824
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.244759795
Short name T715
Test name
Test status
Simulation time 416966846523 ps
CPU time 1995.37 seconds
Started Jul 20 04:34:11 PM PDT 24
Finished Jul 20 05:07:27 PM PDT 24
Peak memory 198428 kb
Host smart-356d737b-3f60-49eb-a81b-62f2a9e79131
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=244759795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.244759795
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1096070259
Short name T722
Test name
Test status
Simulation time 14055573 ps
CPU time 0.63 seconds
Started Jul 20 04:34:23 PM PDT 24
Finished Jul 20 04:34:25 PM PDT 24
Peak memory 195024 kb
Host smart-07a99838-8d90-4b2b-b63f-f9fe363729d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096070259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1096070259
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3484062478
Short name T477
Test name
Test status
Simulation time 224756136 ps
CPU time 0.88 seconds
Started Jul 20 04:34:17 PM PDT 24
Finished Jul 20 04:34:19 PM PDT 24
Peak memory 196644 kb
Host smart-46bbd544-7e74-4599-8896-a1395cf3458a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484062478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3484062478
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3403521073
Short name T161
Test name
Test status
Simulation time 953854172 ps
CPU time 9.15 seconds
Started Jul 20 04:34:11 PM PDT 24
Finished Jul 20 04:34:21 PM PDT 24
Peak memory 197176 kb
Host smart-d4f81242-b51b-484e-a703-09f426326791
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403521073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3403521073
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.4135099032
Short name T260
Test name
Test status
Simulation time 451830733 ps
CPU time 1.06 seconds
Started Jul 20 04:34:13 PM PDT 24
Finished Jul 20 04:34:15 PM PDT 24
Peak memory 196492 kb
Host smart-5337235b-739b-41a2-91ef-b86bdef8d60d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135099032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.4135099032
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2949448553
Short name T480
Test name
Test status
Simulation time 353649565 ps
CPU time 1.22 seconds
Started Jul 20 04:34:14 PM PDT 24
Finished Jul 20 04:34:16 PM PDT 24
Peak memory 195880 kb
Host smart-70246481-e0fb-4979-ae9e-a9e7911b3cbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949448553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2949448553
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1633609677
Short name T475
Test name
Test status
Simulation time 178952968 ps
CPU time 0.85 seconds
Started Jul 20 04:34:13 PM PDT 24
Finished Jul 20 04:34:15 PM PDT 24
Peak memory 195972 kb
Host smart-dc3a4332-26c0-45a3-8d3c-29ee9e90675e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633609677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1633609677
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1553160860
Short name T258
Test name
Test status
Simulation time 92931997 ps
CPU time 1.83 seconds
Started Jul 20 04:34:14 PM PDT 24
Finished Jul 20 04:34:17 PM PDT 24
Peak memory 196228 kb
Host smart-44e57ca3-24a0-41c4-b334-47036f13a71c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553160860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1553160860
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.830361887
Short name T704
Test name
Test status
Simulation time 57721532 ps
CPU time 1.41 seconds
Started Jul 20 04:34:11 PM PDT 24
Finished Jul 20 04:34:13 PM PDT 24
Peak memory 197252 kb
Host smart-4d18cdae-bfce-414d-9c6e-92374fcbeb4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830361887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.830361887
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.3217567769
Short name T521
Test name
Test status
Simulation time 277443976 ps
CPU time 1.29 seconds
Started Jul 20 04:34:17 PM PDT 24
Finished Jul 20 04:34:19 PM PDT 24
Peak memory 197140 kb
Host smart-0f78fd53-f557-43da-a7e8-a5936c476e72
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217567769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup
_pulldown.3217567769
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3561328751
Short name T191
Test name
Test status
Simulation time 762361108 ps
CPU time 3.45 seconds
Started Jul 20 04:34:13 PM PDT 24
Finished Jul 20 04:34:17 PM PDT 24
Peak memory 198060 kb
Host smart-25c32b50-81f4-4ed3-9a15-95092c6f3f32
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561328751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3561328751
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.321326468
Short name T555
Test name
Test status
Simulation time 68687954 ps
CPU time 1.39 seconds
Started Jul 20 04:34:15 PM PDT 24
Finished Jul 20 04:34:17 PM PDT 24
Peak memory 196944 kb
Host smart-e57cdb33-ddd6-4175-9944-9f2f2a967fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321326468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.321326468
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3940726414
Short name T430
Test name
Test status
Simulation time 188604466 ps
CPU time 0.71 seconds
Started Jul 20 04:34:17 PM PDT 24
Finished Jul 20 04:34:18 PM PDT 24
Peak memory 195236 kb
Host smart-aa5cc61c-4881-4894-8cda-badbe11143e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940726414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3940726414
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.1749559292
Short name T124
Test name
Test status
Simulation time 6184655986 ps
CPU time 84.83 seconds
Started Jul 20 04:34:19 PM PDT 24
Finished Jul 20 04:35:44 PM PDT 24
Peak memory 198192 kb
Host smart-a74bf9bb-21b3-4ca1-93e2-54c43c35e0e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749559292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.1749559292
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.631995568
Short name T63
Test name
Test status
Simulation time 104899945189 ps
CPU time 729.51 seconds
Started Jul 20 04:34:17 PM PDT 24
Finished Jul 20 04:46:27 PM PDT 24
Peak memory 198424 kb
Host smart-3ab0524d-e42f-4f33-86d0-aee6e69b4f3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=631995568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.631995568
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.4187775918
Short name T288
Test name
Test status
Simulation time 14824798 ps
CPU time 0.57 seconds
Started Jul 20 04:34:23 PM PDT 24
Finished Jul 20 04:34:26 PM PDT 24
Peak memory 194292 kb
Host smart-627ac178-836c-4569-ad06-92c219be2d04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187775918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.4187775918
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.1642266654
Short name T346
Test name
Test status
Simulation time 21230996 ps
CPU time 0.68 seconds
Started Jul 20 04:34:23 PM PDT 24
Finished Jul 20 04:34:25 PM PDT 24
Peak memory 194124 kb
Host smart-6d20fb21-7d77-4f89-877c-dcde4b615384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642266654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.1642266654
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.1221234119
Short name T145
Test name
Test status
Simulation time 453340270 ps
CPU time 10.1 seconds
Started Jul 20 04:34:28 PM PDT 24
Finished Jul 20 04:34:40 PM PDT 24
Peak memory 195460 kb
Host smart-51ca5a37-43e3-47bd-b103-3fb3992cd360
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221234119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.1221234119
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3985316227
Short name T259
Test name
Test status
Simulation time 425474463 ps
CPU time 0.93 seconds
Started Jul 20 04:34:25 PM PDT 24
Finished Jul 20 04:34:27 PM PDT 24
Peak memory 197012 kb
Host smart-807a6ad0-63d6-482c-9c04-e073974460e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985316227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3985316227
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.531864969
Short name T486
Test name
Test status
Simulation time 24048059 ps
CPU time 0.77 seconds
Started Jul 20 04:34:22 PM PDT 24
Finished Jul 20 04:34:24 PM PDT 24
Peak memory 195432 kb
Host smart-d4524802-0640-43d9-8a41-c105a9ce149d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531864969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.531864969
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2119154644
Short name T468
Test name
Test status
Simulation time 196179880 ps
CPU time 2.02 seconds
Started Jul 20 04:34:23 PM PDT 24
Finished Jul 20 04:34:27 PM PDT 24
Peak memory 198112 kb
Host smart-1dc0f263-5131-40c2-a8b6-f5a732c11914
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119154644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2119154644
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.2451087090
Short name T714
Test name
Test status
Simulation time 407522453 ps
CPU time 2.56 seconds
Started Jul 20 04:34:22 PM PDT 24
Finished Jul 20 04:34:26 PM PDT 24
Peak memory 197288 kb
Host smart-fcd4080b-07e2-459b-aae9-886bb083efba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451087090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
2451087090
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.151099975
Short name T54
Test name
Test status
Simulation time 811550020 ps
CPU time 1.17 seconds
Started Jul 20 04:34:22 PM PDT 24
Finished Jul 20 04:34:24 PM PDT 24
Peak memory 195904 kb
Host smart-446a76a5-6a4e-4f8f-977c-527a8efb3c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151099975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.151099975
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.3398867645
Short name T337
Test name
Test status
Simulation time 71053056 ps
CPU time 0.94 seconds
Started Jul 20 04:34:26 PM PDT 24
Finished Jul 20 04:34:28 PM PDT 24
Peak memory 196668 kb
Host smart-6a423424-886c-41f3-ac09-bfa3aadfd022
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398867645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.3398867645
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.4049448623
Short name T489
Test name
Test status
Simulation time 527560659 ps
CPU time 4.24 seconds
Started Jul 20 04:34:28 PM PDT 24
Finished Jul 20 04:34:34 PM PDT 24
Peak memory 198056 kb
Host smart-2ceec1fb-738c-4c35-bb33-9cdf53f5f11e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049448623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.4049448623
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1018043389
Short name T576
Test name
Test status
Simulation time 57729472 ps
CPU time 1.33 seconds
Started Jul 20 04:34:27 PM PDT 24
Finished Jul 20 04:34:31 PM PDT 24
Peak memory 195636 kb
Host smart-6b68ae91-8dfb-44ae-96d9-c440dd380e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018043389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1018043389
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3110531346
Short name T186
Test name
Test status
Simulation time 23081113 ps
CPU time 0.69 seconds
Started Jul 20 04:34:23 PM PDT 24
Finished Jul 20 04:34:25 PM PDT 24
Peak memory 194264 kb
Host smart-825276e1-b1d3-4097-942c-4e6758f11a50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110531346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3110531346
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1603467480
Short name T553
Test name
Test status
Simulation time 20730469915 ps
CPU time 60.76 seconds
Started Jul 20 04:34:27 PM PDT 24
Finished Jul 20 04:35:30 PM PDT 24
Peak memory 198252 kb
Host smart-a9c51b08-922c-45e6-8cd1-97be5b2110cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603467480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1603467480
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1710441696
Short name T42
Test name
Test status
Simulation time 46967435 ps
CPU time 0.54 seconds
Started Jul 20 04:34:27 PM PDT 24
Finished Jul 20 04:34:29 PM PDT 24
Peak memory 194828 kb
Host smart-93d9ada8-b86c-45fe-91a0-87972538c4a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710441696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1710441696
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.2463507719
Short name T214
Test name
Test status
Simulation time 41231822 ps
CPU time 0.75 seconds
Started Jul 20 04:34:26 PM PDT 24
Finished Jul 20 04:34:29 PM PDT 24
Peak memory 195324 kb
Host smart-2c300698-2e89-4b2c-9e74-7741c788b6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463507719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.2463507719
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2951917126
Short name T368
Test name
Test status
Simulation time 93725782 ps
CPU time 4.54 seconds
Started Jul 20 04:34:29 PM PDT 24
Finished Jul 20 04:34:35 PM PDT 24
Peak memory 196348 kb
Host smart-fe3bd2c6-b38e-45e9-bf6f-c231e103e0f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951917126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2951917126
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2725496499
Short name T642
Test name
Test status
Simulation time 45580243 ps
CPU time 0.8 seconds
Started Jul 20 04:34:27 PM PDT 24
Finished Jul 20 04:34:30 PM PDT 24
Peak memory 195936 kb
Host smart-3c633c29-24c9-4522-93b0-b5708f52b1a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725496499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2725496499
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2408475121
Short name T707
Test name
Test status
Simulation time 108231277 ps
CPU time 1.4 seconds
Started Jul 20 04:34:25 PM PDT 24
Finished Jul 20 04:34:28 PM PDT 24
Peak memory 195992 kb
Host smart-3cf193cf-50a3-4d98-ba23-c25ad3cb07e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408475121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2408475121
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.723970901
Short name T109
Test name
Test status
Simulation time 189103366 ps
CPU time 3.78 seconds
Started Jul 20 04:34:22 PM PDT 24
Finished Jul 20 04:34:26 PM PDT 24
Peak memory 198156 kb
Host smart-9b868b72-b05e-4b56-963e-23f56668591a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723970901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.723970901
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3226479616
Short name T307
Test name
Test status
Simulation time 252098619 ps
CPU time 1.66 seconds
Started Jul 20 04:34:23 PM PDT 24
Finished Jul 20 04:34:26 PM PDT 24
Peak memory 196052 kb
Host smart-20305683-f28a-4d61-90be-a4654b7af2db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226479616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3226479616
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.811444440
Short name T149
Test name
Test status
Simulation time 129524626 ps
CPU time 1.2 seconds
Started Jul 20 04:34:26 PM PDT 24
Finished Jul 20 04:34:30 PM PDT 24
Peak memory 197104 kb
Host smart-3cc8dade-9ec3-4ab3-8280-d3acdbd95992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811444440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.811444440
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.2597183196
Short name T413
Test name
Test status
Simulation time 125433696 ps
CPU time 0.81 seconds
Started Jul 20 04:34:24 PM PDT 24
Finished Jul 20 04:34:26 PM PDT 24
Peak memory 195864 kb
Host smart-e5345318-a1c2-4e5f-a03e-4bf08519fee0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597183196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.2597183196
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2733396819
Short name T314
Test name
Test status
Simulation time 200473247 ps
CPU time 2.46 seconds
Started Jul 20 04:34:28 PM PDT 24
Finished Jul 20 04:34:32 PM PDT 24
Peak memory 197956 kb
Host smart-4f9e9fa3-4787-4906-9f54-05f0e16a716c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733396819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2733396819
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2931534473
Short name T150
Test name
Test status
Simulation time 70082155 ps
CPU time 1 seconds
Started Jul 20 04:34:23 PM PDT 24
Finished Jul 20 04:34:26 PM PDT 24
Peak memory 196420 kb
Host smart-e6dd7512-16a5-4181-b307-a3bacd9e9f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931534473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2931534473
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.1178825559
Short name T682
Test name
Test status
Simulation time 70339870 ps
CPU time 1.17 seconds
Started Jul 20 04:34:27 PM PDT 24
Finished Jul 20 04:34:31 PM PDT 24
Peak memory 195724 kb
Host smart-c8491d48-c279-420f-b42a-73d873f76c84
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178825559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.1178825559
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1466671471
Short name T308
Test name
Test status
Simulation time 12308115767 ps
CPU time 33.82 seconds
Started Jul 20 04:34:21 PM PDT 24
Finished Jul 20 04:34:56 PM PDT 24
Peak memory 198196 kb
Host smart-60a6856b-ee3d-434b-8fa0-47eab5d1da43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466671471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1466671471
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3124856704
Short name T234
Test name
Test status
Simulation time 22818431 ps
CPU time 0.58 seconds
Started Jul 20 04:34:22 PM PDT 24
Finished Jul 20 04:34:23 PM PDT 24
Peak memory 194260 kb
Host smart-1e020c62-c9ac-45fc-a844-a99d9de9913b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124856704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3124856704
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1692504620
Short name T56
Test name
Test status
Simulation time 147811867 ps
CPU time 0.81 seconds
Started Jul 20 04:34:26 PM PDT 24
Finished Jul 20 04:34:29 PM PDT 24
Peak memory 195428 kb
Host smart-a3291987-9c7b-450a-b39e-56deaed05ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692504620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1692504620
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3862571951
Short name T353
Test name
Test status
Simulation time 1632696067 ps
CPU time 11.3 seconds
Started Jul 20 04:34:22 PM PDT 24
Finished Jul 20 04:34:35 PM PDT 24
Peak memory 196860 kb
Host smart-ac522781-2545-49c7-b970-48cb29ddd765
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862571951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3862571951
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3216356234
Short name T261
Test name
Test status
Simulation time 183188001 ps
CPU time 1 seconds
Started Jul 20 04:34:23 PM PDT 24
Finished Jul 20 04:34:26 PM PDT 24
Peak memory 196628 kb
Host smart-bae2131d-f160-4fa1-9a22-861ab8766151
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216356234 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3216356234
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.4001301559
Short name T363
Test name
Test status
Simulation time 26321567 ps
CPU time 0.84 seconds
Started Jul 20 04:34:26 PM PDT 24
Finished Jul 20 04:34:29 PM PDT 24
Peak memory 195400 kb
Host smart-0a6ac41c-9fb5-476b-8347-cd809b59b0e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001301559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.4001301559
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2396437522
Short name T304
Test name
Test status
Simulation time 50480651 ps
CPU time 2.12 seconds
Started Jul 20 04:34:26 PM PDT 24
Finished Jul 20 04:34:31 PM PDT 24
Peak memory 197996 kb
Host smart-dd5f59f6-9cd6-4dfe-abb8-21cd97f8244d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396437522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2396437522
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1375981013
Short name T41
Test name
Test status
Simulation time 107928600 ps
CPU time 1.7 seconds
Started Jul 20 04:34:23 PM PDT 24
Finished Jul 20 04:34:27 PM PDT 24
Peak memory 196976 kb
Host smart-1e850846-6a8c-46a2-b70f-bc610913136e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375981013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1375981013
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1555265436
Short name T631
Test name
Test status
Simulation time 95555331 ps
CPU time 0.99 seconds
Started Jul 20 04:34:30 PM PDT 24
Finished Jul 20 04:34:32 PM PDT 24
Peak memory 196144 kb
Host smart-1b0745de-b3cd-4ffc-a196-675ae250fad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555265436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1555265436
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.2644029079
Short name T154
Test name
Test status
Simulation time 102788933 ps
CPU time 0.82 seconds
Started Jul 20 04:34:26 PM PDT 24
Finished Jul 20 04:34:29 PM PDT 24
Peak memory 196584 kb
Host smart-1ddc1a0b-3f0f-4d59-a87e-8b85f30cfffa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644029079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.2644029079
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.368362112
Short name T565
Test name
Test status
Simulation time 896987160 ps
CPU time 3.84 seconds
Started Jul 20 04:34:22 PM PDT 24
Finished Jul 20 04:34:27 PM PDT 24
Peak memory 198084 kb
Host smart-bab2dbea-81c2-4fbd-aaf1-5375a531a083
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368362112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.368362112
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3878531690
Short name T290
Test name
Test status
Simulation time 82477312 ps
CPU time 0.87 seconds
Started Jul 20 04:34:28 PM PDT 24
Finished Jul 20 04:34:31 PM PDT 24
Peak memory 195404 kb
Host smart-924454d6-effb-4b7b-a905-bc28d6c65bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878531690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3878531690
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.2968708927
Short name T709
Test name
Test status
Simulation time 288375324 ps
CPU time 0.93 seconds
Started Jul 20 04:34:26 PM PDT 24
Finished Jul 20 04:34:28 PM PDT 24
Peak memory 195888 kb
Host smart-d6be35f5-de54-4d2f-9b14-7bdfbee2550e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968708927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.2968708927
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2876773231
Short name T400
Test name
Test status
Simulation time 36528869300 ps
CPU time 187.75 seconds
Started Jul 20 04:34:21 PM PDT 24
Finished Jul 20 04:37:30 PM PDT 24
Peak memory 198184 kb
Host smart-c50244ea-f696-44c3-b620-ec8593f218dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876773231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2876773231
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3644213641
Short name T33
Test name
Test status
Simulation time 76080493485 ps
CPU time 1184.98 seconds
Started Jul 20 04:34:24 PM PDT 24
Finished Jul 20 04:54:11 PM PDT 24
Peak memory 198384 kb
Host smart-c77eb9f2-ff3d-4d05-bf12-275737b90753
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3644213641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3644213641
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2811635829
Short name T846
Test name
Test status
Simulation time 39292528 ps
CPU time 0.94 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 04:33:41 PM PDT 24
Peak memory 192012 kb
Host smart-09b2b765-94cd-4a9d-8083-77d60afea969
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2811635829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2811635829
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3887629689
Short name T849
Test name
Test status
Simulation time 368989564 ps
CPU time 0.94 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 04:33:34 PM PDT 24
Peak memory 197512 kb
Host smart-2880353c-853a-4ecb-ab64-932fded9fab3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887629689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3887629689
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.14776387
Short name T891
Test name
Test status
Simulation time 91644502 ps
CPU time 1.18 seconds
Started Jul 20 04:33:35 PM PDT 24
Finished Jul 20 04:33:45 PM PDT 24
Peak memory 192068 kb
Host smart-73c39359-01da-486b-9977-3d858970a740
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=14776387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.14776387
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2563577987
Short name T862
Test name
Test status
Simulation time 68457096 ps
CPU time 1.26 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:33:33 PM PDT 24
Peak memory 192012 kb
Host smart-274a12d9-8984-4f9a-8ff0-bc83d6c9dfe1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563577987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2563577987
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1504913373
Short name T894
Test name
Test status
Simulation time 33454871 ps
CPU time 0.92 seconds
Started Jul 20 04:33:41 PM PDT 24
Finished Jul 20 04:33:49 PM PDT 24
Peak memory 191848 kb
Host smart-d1134090-d609-4360-b812-b2338e3af19b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1504913373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1504913373
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1140464711
Short name T914
Test name
Test status
Simulation time 188378064 ps
CPU time 1.38 seconds
Started Jul 20 04:33:35 PM PDT 24
Finished Jul 20 04:33:45 PM PDT 24
Peak memory 198364 kb
Host smart-598aea5f-705a-4310-9ba3-9f8b85d3f2bf
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140464711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1140464711
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.369420319
Short name T851
Test name
Test status
Simulation time 163132764 ps
CPU time 1.05 seconds
Started Jul 20 04:34:20 PM PDT 24
Finished Jul 20 04:34:22 PM PDT 24
Peak memory 191984 kb
Host smart-80caeb60-1665-4100-a323-3143a329c27c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=369420319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.369420319
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.415303101
Short name T864
Test name
Test status
Simulation time 255623013 ps
CPU time 1.25 seconds
Started Jul 20 04:33:42 PM PDT 24
Finished Jul 20 04:33:49 PM PDT 24
Peak memory 191876 kb
Host smart-2391087c-dc25-4099-b4d0-53837be5e956
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415303101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.415303101
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.832730226
Short name T895
Test name
Test status
Simulation time 38205166 ps
CPU time 1.04 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:33:38 PM PDT 24
Peak memory 192032 kb
Host smart-59c73056-cba6-4738-ba2d-788276864fcc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=832730226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.832730226
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.115752620
Short name T885
Test name
Test status
Simulation time 54271717 ps
CPU time 1.32 seconds
Started Jul 20 04:33:37 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 192016 kb
Host smart-8d0e2d16-1f58-4d5c-9e5c-d26b78ee9b7c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115752620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.115752620
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.130086944
Short name T896
Test name
Test status
Simulation time 56436005 ps
CPU time 0.83 seconds
Started Jul 20 04:33:27 PM PDT 24
Finished Jul 20 04:33:35 PM PDT 24
Peak memory 192036 kb
Host smart-3027d361-fe86-4f32-b1a0-470d71f151cc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=130086944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.130086944
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.763302857
Short name T858
Test name
Test status
Simulation time 145726332 ps
CPU time 0.91 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:33:39 PM PDT 24
Peak memory 191844 kb
Host smart-4e3d099f-e868-4bbb-9a8f-872261018b76
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763302857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.763302857
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.827212953
Short name T893
Test name
Test status
Simulation time 69989228 ps
CPU time 1.23 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:33:38 PM PDT 24
Peak memory 192024 kb
Host smart-41c7c7c2-d897-4c94-b968-492ebbb5a45b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=827212953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.827212953
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.551479551
Short name T855
Test name
Test status
Simulation time 207180705 ps
CPU time 1.09 seconds
Started Jul 20 04:33:40 PM PDT 24
Finished Jul 20 04:33:48 PM PDT 24
Peak memory 192056 kb
Host smart-68748d16-3285-4cd5-8766-d0c1e5554fd4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551479551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.551479551
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3664712551
Short name T863
Test name
Test status
Simulation time 72041697 ps
CPU time 1.25 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:33:39 PM PDT 24
Peak memory 192052 kb
Host smart-b84b478f-80fd-48b1-b654-966cb0c53687
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3664712551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3664712551
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.592342769
Short name T892
Test name
Test status
Simulation time 62723148 ps
CPU time 0.91 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:33:38 PM PDT 24
Peak memory 198188 kb
Host smart-beb5a0f6-96f1-4d74-9786-c8864ac79ade
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592342769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.592342769
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3300027764
Short name T869
Test name
Test status
Simulation time 108569373 ps
CPU time 0.94 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:33:39 PM PDT 24
Peak memory 192020 kb
Host smart-4a2d3164-3b73-4684-be13-3a797b4b5a94
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3300027764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3300027764
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2223488471
Short name T903
Test name
Test status
Simulation time 113778359 ps
CPU time 1.03 seconds
Started Jul 20 04:33:36 PM PDT 24
Finished Jul 20 04:33:45 PM PDT 24
Peak memory 191952 kb
Host smart-e0ae7117-56b5-4720-a029-cf98265bff7e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223488471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2223488471
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3597313675
Short name T938
Test name
Test status
Simulation time 130545393 ps
CPU time 0.95 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:33:38 PM PDT 24
Peak memory 192024 kb
Host smart-7631baec-47df-49ba-be3c-0a737b84b3b5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3597313675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3597313675
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.791261739
Short name T886
Test name
Test status
Simulation time 134197936 ps
CPU time 1.19 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:33:39 PM PDT 24
Peak memory 192020 kb
Host smart-cc94e3d4-6d8c-4e72-89ed-eff7914b3494
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791261739 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.791261739
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.805693341
Short name T872
Test name
Test status
Simulation time 152677894 ps
CPU time 1.2 seconds
Started Jul 20 04:34:21 PM PDT 24
Finished Jul 20 04:34:23 PM PDT 24
Peak memory 191988 kb
Host smart-16c2bdf2-2573-4314-8f30-0fdb6aefbdce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=805693341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.805693341
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.194467913
Short name T923
Test name
Test status
Simulation time 128883601 ps
CPU time 1.16 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:33:38 PM PDT 24
Peak memory 192020 kb
Host smart-4ede6695-a42a-4087-a897-fda12edcd91e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194467913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.194467913
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.3524950348
Short name T887
Test name
Test status
Simulation time 57158462 ps
CPU time 1.03 seconds
Started Jul 20 04:34:21 PM PDT 24
Finished Jul 20 04:34:22 PM PDT 24
Peak memory 191964 kb
Host smart-2615ccd3-b0d8-4dcc-80c6-17a0039d2eb9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3524950348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.3524950348
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.567083468
Short name T943
Test name
Test status
Simulation time 971541713 ps
CPU time 1.38 seconds
Started Jul 20 04:33:20 PM PDT 24
Finished Jul 20 04:33:28 PM PDT 24
Peak memory 198424 kb
Host smart-8c0fbedd-befa-42d9-b8c0-ceed721cd86e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567083468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.567083468
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1524916804
Short name T878
Test name
Test status
Simulation time 31937113 ps
CPU time 0.89 seconds
Started Jul 20 04:33:35 PM PDT 24
Finished Jul 20 04:33:45 PM PDT 24
Peak memory 192020 kb
Host smart-3b374f57-da25-4746-84f4-1db9352a7de1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1524916804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1524916804
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.271623863
Short name T919
Test name
Test status
Simulation time 1246099775 ps
CPU time 1.23 seconds
Started Jul 20 04:33:32 PM PDT 24
Finished Jul 20 04:33:41 PM PDT 24
Peak memory 198512 kb
Host smart-a7fb5692-1206-4b7e-b866-72673aa620ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271623863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.271623863
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1042590706
Short name T927
Test name
Test status
Simulation time 187579587 ps
CPU time 0.93 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:33:38 PM PDT 24
Peak memory 191852 kb
Host smart-325bdedc-5b94-4932-ab6d-4af2179d0bc8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1042590706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1042590706
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3114197555
Short name T932
Test name
Test status
Simulation time 97333613 ps
CPU time 0.91 seconds
Started Jul 20 04:33:27 PM PDT 24
Finished Jul 20 04:33:36 PM PDT 24
Peak memory 192092 kb
Host smart-70c316fa-a8f7-4fca-8166-8e9031b836bd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114197555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3114197555
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1049464749
Short name T922
Test name
Test status
Simulation time 93335043 ps
CPU time 0.94 seconds
Started Jul 20 04:33:33 PM PDT 24
Finished Jul 20 04:33:43 PM PDT 24
Peak memory 192052 kb
Host smart-cc771229-e503-4d04-9954-06774de045ec
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1049464749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1049464749
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1795093768
Short name T888
Test name
Test status
Simulation time 132606251 ps
CPU time 1.03 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 04:33:40 PM PDT 24
Peak memory 191948 kb
Host smart-60207c2a-e4a2-49fa-8d3d-00f1bf317a6f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795093768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1795093768
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.1279954548
Short name T918
Test name
Test status
Simulation time 526559649 ps
CPU time 1.14 seconds
Started Jul 20 04:33:32 PM PDT 24
Finished Jul 20 04:33:42 PM PDT 24
Peak memory 192072 kb
Host smart-ec6f67eb-a6ed-4158-868e-20c0694ff48b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1279954548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.1279954548
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1740026931
Short name T859
Test name
Test status
Simulation time 262846361 ps
CPU time 1.12 seconds
Started Jul 20 04:34:34 PM PDT 24
Finished Jul 20 04:34:39 PM PDT 24
Peak memory 189640 kb
Host smart-5d3d52db-a515-4520-8d58-410ab9d66a32
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740026931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1740026931
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.3209960695
Short name T868
Test name
Test status
Simulation time 26724163 ps
CPU time 0.79 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 04:33:40 PM PDT 24
Peak memory 191904 kb
Host smart-df701156-a497-4e91-a8e1-92af3aa7ea0d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3209960695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.3209960695
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1747781764
Short name T905
Test name
Test status
Simulation time 23515817 ps
CPU time 0.8 seconds
Started Jul 20 04:33:18 PM PDT 24
Finished Jul 20 04:33:25 PM PDT 24
Peak memory 191840 kb
Host smart-f03f3d9a-4ff6-423a-a1e3-568dee928aa9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747781764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1747781764
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.156020483
Short name T879
Test name
Test status
Simulation time 218070743 ps
CPU time 1.1 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 04:33:40 PM PDT 24
Peak memory 192100 kb
Host smart-8a4984e7-7070-4197-bc45-c674a7d74c74
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=156020483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.156020483
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3225609330
Short name T937
Test name
Test status
Simulation time 47504923 ps
CPU time 0.9 seconds
Started Jul 20 04:33:39 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 191916 kb
Host smart-1f08fad8-56da-4ee5-bdf5-81a0cdee327c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225609330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3225609330
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.501619189
Short name T939
Test name
Test status
Simulation time 36639457 ps
CPU time 0.97 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 04:33:34 PM PDT 24
Peak memory 192032 kb
Host smart-44855bd0-62a4-4731-b0e3-1b54808f7646
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=501619189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.501619189
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3573554614
Short name T900
Test name
Test status
Simulation time 49924321 ps
CPU time 0.88 seconds
Started Jul 20 04:33:38 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 196480 kb
Host smart-b37bfe9e-ceb6-4a0d-b3b8-b1c1ccab702d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573554614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3573554614
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1815396912
Short name T873
Test name
Test status
Simulation time 44343326 ps
CPU time 1.01 seconds
Started Jul 20 04:33:25 PM PDT 24
Finished Jul 20 04:33:33 PM PDT 24
Peak memory 192020 kb
Host smart-bf576b3a-6da3-4a73-8b28-87092591fcd9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1815396912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1815396912
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4118609223
Short name T921
Test name
Test status
Simulation time 53763591 ps
CPU time 1.3 seconds
Started Jul 20 04:33:27 PM PDT 24
Finished Jul 20 04:33:36 PM PDT 24
Peak memory 192008 kb
Host smart-7cdd4cf0-197c-4fc7-aee8-f2bc52a7ea34
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118609223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4118609223
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3225982341
Short name T897
Test name
Test status
Simulation time 29035408 ps
CPU time 0.75 seconds
Started Jul 20 04:33:43 PM PDT 24
Finished Jul 20 04:33:49 PM PDT 24
Peak memory 191912 kb
Host smart-d2337f30-7b8b-47b8-82c6-28f9cad25003
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3225982341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3225982341
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2049188139
Short name T881
Test name
Test status
Simulation time 305975757 ps
CPU time 1.33 seconds
Started Jul 20 04:34:46 PM PDT 24
Finished Jul 20 04:34:48 PM PDT 24
Peak memory 191924 kb
Host smart-8156892f-d009-4902-a427-0261ffc0d97e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049188139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2049188139
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.324745925
Short name T860
Test name
Test status
Simulation time 359442286 ps
CPU time 0.99 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 04:33:35 PM PDT 24
Peak memory 192004 kb
Host smart-36f1c5f6-9515-4a10-a9a4-3269ce47825d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=324745925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.324745925
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1815077446
Short name T942
Test name
Test status
Simulation time 34396122 ps
CPU time 0.91 seconds
Started Jul 20 04:34:34 PM PDT 24
Finished Jul 20 04:34:39 PM PDT 24
Peak memory 189368 kb
Host smart-e94f6526-4d11-408a-92eb-717f9a63f2ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815077446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1815077446
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.693275002
Short name T934
Test name
Test status
Simulation time 231129446 ps
CPU time 1.32 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:33:39 PM PDT 24
Peak memory 192056 kb
Host smart-3f6483ab-dc8c-4f53-83e8-2ad34513262c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=693275002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.693275002
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1758539075
Short name T845
Test name
Test status
Simulation time 35059323 ps
CPU time 0.88 seconds
Started Jul 20 04:33:38 PM PDT 24
Finished Jul 20 04:33:46 PM PDT 24
Peak memory 191892 kb
Host smart-d2f4094b-b360-40a8-8476-2a66ea1bd75a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758539075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1758539075
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.441226378
Short name T883
Test name
Test status
Simulation time 152715783 ps
CPU time 1.27 seconds
Started Jul 20 04:33:41 PM PDT 24
Finished Jul 20 04:33:49 PM PDT 24
Peak memory 198484 kb
Host smart-899e0e86-47b9-4b64-b0f6-d7aaf69f2a04
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=441226378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.441226378
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3279010937
Short name T928
Test name
Test status
Simulation time 41702964 ps
CPU time 1.06 seconds
Started Jul 20 04:33:33 PM PDT 24
Finished Jul 20 04:33:43 PM PDT 24
Peak memory 192024 kb
Host smart-6caf40f4-202b-4797-b1f6-394e2b488e51
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279010937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3279010937
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1509245050
Short name T890
Test name
Test status
Simulation time 70499635 ps
CPU time 1.03 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:33:40 PM PDT 24
Peak memory 192076 kb
Host smart-52d04efc-f411-4bf9-9342-4529fa1a06b4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1509245050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1509245050
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1156456724
Short name T877
Test name
Test status
Simulation time 294935437 ps
CPU time 1.23 seconds
Started Jul 20 04:33:37 PM PDT 24
Finished Jul 20 04:33:46 PM PDT 24
Peak memory 192024 kb
Host smart-b81ddca9-4f14-4c03-9e02-fd79797c33e4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156456724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1156456724
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1995291777
Short name T898
Test name
Test status
Simulation time 83578392 ps
CPU time 0.88 seconds
Started Jul 20 04:33:41 PM PDT 24
Finished Jul 20 04:33:48 PM PDT 24
Peak memory 196620 kb
Host smart-40907f87-dc76-42c9-8b31-c1ba9bb36b62
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1995291777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1995291777
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2376626595
Short name T875
Test name
Test status
Simulation time 177279432 ps
CPU time 1.3 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:33:38 PM PDT 24
Peak memory 192176 kb
Host smart-cf4228c8-0ac1-46c4-a594-8159df2037b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376626595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2376626595
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.2647899656
Short name T941
Test name
Test status
Simulation time 427700539 ps
CPU time 1.06 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:33:38 PM PDT 24
Peak memory 192084 kb
Host smart-5149ecc2-c494-49bc-abc4-3fd6dce1385d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2647899656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.2647899656
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4282044906
Short name T884
Test name
Test status
Simulation time 381612821 ps
CPU time 1.04 seconds
Started Jul 20 04:33:38 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 192048 kb
Host smart-fd9ec6f6-7a64-46be-a99f-69792ac8d4b8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282044906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4282044906
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.3849466787
Short name T865
Test name
Test status
Simulation time 177350874 ps
CPU time 1.16 seconds
Started Jul 20 04:34:46 PM PDT 24
Finished Jul 20 04:34:48 PM PDT 24
Peak memory 198308 kb
Host smart-77e5ac44-07e5-457d-9632-615fab5c5a87
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3849466787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.3849466787
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4153202431
Short name T854
Test name
Test status
Simulation time 115251242 ps
CPU time 0.92 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:33:40 PM PDT 24
Peak memory 191996 kb
Host smart-95b3bf2e-fce1-4a8f-be0e-01d1f6adc40d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153202431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4153202431
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.530085956
Short name T902
Test name
Test status
Simulation time 154030839 ps
CPU time 1.18 seconds
Started Jul 20 04:33:41 PM PDT 24
Finished Jul 20 04:33:49 PM PDT 24
Peak memory 198492 kb
Host smart-a2f79513-58a2-4f05-bcce-bb6954f3cfc4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=530085956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.530085956
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3725792522
Short name T857
Test name
Test status
Simulation time 91137011 ps
CPU time 1.05 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:33:38 PM PDT 24
Peak memory 198484 kb
Host smart-bb710e78-ee7c-4953-9de1-1c92ccd8f247
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725792522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3725792522
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.120254528
Short name T889
Test name
Test status
Simulation time 47735280 ps
CPU time 1.05 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 04:33:40 PM PDT 24
Peak memory 197836 kb
Host smart-08ca5eab-6683-4180-b0b2-92b0385404d0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=120254528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.120254528
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2770314138
Short name T925
Test name
Test status
Simulation time 481202664 ps
CPU time 1.28 seconds
Started Jul 20 04:33:38 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 198428 kb
Host smart-f5964ea7-64f9-490a-8826-ec5c8250e915
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770314138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2770314138
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.4136543006
Short name T912
Test name
Test status
Simulation time 127604990 ps
CPU time 1.08 seconds
Started Jul 20 04:33:31 PM PDT 24
Finished Jul 20 04:33:40 PM PDT 24
Peak memory 191980 kb
Host smart-58a65393-d0ca-4989-8d81-6a24741c70c1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4136543006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.4136543006
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3664097488
Short name T924
Test name
Test status
Simulation time 184533305 ps
CPU time 1.01 seconds
Started Jul 20 04:33:25 PM PDT 24
Finished Jul 20 04:33:33 PM PDT 24
Peak memory 196688 kb
Host smart-f457ebc7-3d85-4060-a248-3bdd99b9b009
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664097488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3664097488
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.224080483
Short name T930
Test name
Test status
Simulation time 34594305 ps
CPU time 0.92 seconds
Started Jul 20 04:34:47 PM PDT 24
Finished Jul 20 04:34:48 PM PDT 24
Peak memory 191916 kb
Host smart-43a303c1-f9c5-43db-ae9e-2200816c5cd1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=224080483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.224080483
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.473985374
Short name T920
Test name
Test status
Simulation time 349247826 ps
CPU time 1.36 seconds
Started Jul 20 04:33:40 PM PDT 24
Finished Jul 20 04:33:48 PM PDT 24
Peak memory 192020 kb
Host smart-1c2d699a-275d-4571-841b-55fbdbdb0b00
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473985374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.473985374
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3086032241
Short name T882
Test name
Test status
Simulation time 36489131 ps
CPU time 1.02 seconds
Started Jul 20 04:33:38 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 197672 kb
Host smart-5b32ae6a-1aa8-4d37-ac2d-ebd78fa44184
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3086032241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3086032241
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.233104028
Short name T844
Test name
Test status
Simulation time 65870513 ps
CPU time 1.02 seconds
Started Jul 20 04:33:32 PM PDT 24
Finished Jul 20 04:33:42 PM PDT 24
Peak memory 192104 kb
Host smart-34181e73-dea4-4f61-ac78-a2b4feca620c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233104028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.233104028
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1986637616
Short name T913
Test name
Test status
Simulation time 43920551 ps
CPU time 0.97 seconds
Started Jul 20 04:33:39 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 192088 kb
Host smart-b2b50d76-8391-46bd-bdbc-77c47fd0019b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1986637616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1986637616
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3671203635
Short name T880
Test name
Test status
Simulation time 277300891 ps
CPU time 1.17 seconds
Started Jul 20 04:33:37 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 192024 kb
Host smart-b2b89a91-9525-4ca5-b48d-5a965bd766ef
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671203635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3671203635
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.3428760626
Short name T940
Test name
Test status
Simulation time 40819691 ps
CPU time 0.8 seconds
Started Jul 20 04:33:36 PM PDT 24
Finished Jul 20 04:33:46 PM PDT 24
Peak memory 191940 kb
Host smart-ca22bc83-a6db-4344-bf2f-c9f151e079e9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3428760626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.3428760626
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2122773840
Short name T850
Test name
Test status
Simulation time 34518469 ps
CPU time 0.9 seconds
Started Jul 20 04:33:35 PM PDT 24
Finished Jul 20 04:33:45 PM PDT 24
Peak memory 191856 kb
Host smart-79401a05-ff35-4b46-8524-6b49650a0956
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122773840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2122773840
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.289794973
Short name T933
Test name
Test status
Simulation time 53552321 ps
CPU time 1.14 seconds
Started Jul 20 04:33:37 PM PDT 24
Finished Jul 20 04:33:46 PM PDT 24
Peak memory 197936 kb
Host smart-7f5be812-9c36-454f-bb33-53eaf834ae19
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=289794973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.289794973
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1654434057
Short name T904
Test name
Test status
Simulation time 61673329 ps
CPU time 1.23 seconds
Started Jul 20 04:33:37 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 192060 kb
Host smart-983e0585-ceee-4c66-9059-315f9d96f4eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654434057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1654434057
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.4222751143
Short name T853
Test name
Test status
Simulation time 373581957 ps
CPU time 1.15 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:33:38 PM PDT 24
Peak memory 192076 kb
Host smart-8417369e-eb54-4995-9b80-756416440250
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4222751143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.4222751143
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.747410970
Short name T867
Test name
Test status
Simulation time 41882014 ps
CPU time 1.12 seconds
Started Jul 20 04:33:35 PM PDT 24
Finished Jul 20 04:33:45 PM PDT 24
Peak memory 192108 kb
Host smart-afafadb9-b8d7-463a-a539-e0ae26394dc7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747410970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.747410970
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.4284243645
Short name T871
Test name
Test status
Simulation time 203776686 ps
CPU time 1.37 seconds
Started Jul 20 04:33:29 PM PDT 24
Finished Jul 20 04:33:38 PM PDT 24
Peak memory 191960 kb
Host smart-9c301c66-60a5-4ca1-8d23-96960ba64395
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4284243645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.4284243645
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3921398888
Short name T926
Test name
Test status
Simulation time 62364779 ps
CPU time 1.25 seconds
Started Jul 20 04:33:32 PM PDT 24
Finished Jul 20 04:33:42 PM PDT 24
Peak memory 192108 kb
Host smart-63953fdc-3232-44e4-8adc-1b36e20eee56
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921398888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3921398888
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.2152145309
Short name T906
Test name
Test status
Simulation time 100892038 ps
CPU time 1.35 seconds
Started Jul 20 04:33:26 PM PDT 24
Finished Jul 20 04:33:35 PM PDT 24
Peak memory 191964 kb
Host smart-4cab0afd-6659-4dd1-9af5-67fad0c90765
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2152145309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.2152145309
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3193643948
Short name T931
Test name
Test status
Simulation time 34183883 ps
CPU time 0.99 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:33:39 PM PDT 24
Peak memory 192024 kb
Host smart-49ad2b18-a597-4038-b261-f5f8819c2e17
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193643948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3193643948
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3779043167
Short name T910
Test name
Test status
Simulation time 142252847 ps
CPU time 0.84 seconds
Started Jul 20 04:33:33 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 196608 kb
Host smart-b6b69787-2fba-4acf-a909-9aa0c2fb357a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3779043167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3779043167
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1941540944
Short name T936
Test name
Test status
Simulation time 170722953 ps
CPU time 0.93 seconds
Started Jul 20 04:33:34 PM PDT 24
Finished Jul 20 04:33:43 PM PDT 24
Peak memory 197548 kb
Host smart-356e2128-a447-4036-8cf8-b5a7d7bf30a9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941540944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1941540944
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2051945288
Short name T915
Test name
Test status
Simulation time 62158250 ps
CPU time 1.16 seconds
Started Jul 20 04:34:34 PM PDT 24
Finished Jul 20 04:34:39 PM PDT 24
Peak memory 195896 kb
Host smart-556f2964-f4f5-40f5-9f47-6aec87244e56
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2051945288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2051945288
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.976736206
Short name T901
Test name
Test status
Simulation time 62466067 ps
CPU time 1.03 seconds
Started Jul 20 04:33:25 PM PDT 24
Finished Jul 20 04:33:33 PM PDT 24
Peak memory 192040 kb
Host smart-84a210f0-8e90-465e-948a-2ecd0d704bd5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976736206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.976736206
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.4122168205
Short name T847
Test name
Test status
Simulation time 108067014 ps
CPU time 0.75 seconds
Started Jul 20 04:33:34 PM PDT 24
Finished Jul 20 04:33:43 PM PDT 24
Peak memory 195588 kb
Host smart-69e27f2a-18ba-4967-a1c9-51cfcb4d5a6e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4122168205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.4122168205
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2233743936
Short name T929
Test name
Test status
Simulation time 209660915 ps
CPU time 1.18 seconds
Started Jul 20 04:33:32 PM PDT 24
Finished Jul 20 04:33:46 PM PDT 24
Peak memory 192120 kb
Host smart-8b5bfd88-1387-419a-9a5b-2643bc164955
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233743936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2233743936
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3926305299
Short name T848
Test name
Test status
Simulation time 78721729 ps
CPU time 1.1 seconds
Started Jul 20 04:33:25 PM PDT 24
Finished Jul 20 04:33:33 PM PDT 24
Peak memory 192116 kb
Host smart-fee26d9f-2a34-4c0e-a98e-8af434e81e5a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3926305299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3926305299
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.723324316
Short name T911
Test name
Test status
Simulation time 138290585 ps
CPU time 1.3 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:33:32 PM PDT 24
Peak memory 192088 kb
Host smart-412f438b-824a-4816-a61b-eed943490220
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723324316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.723324316
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.840827652
Short name T935
Test name
Test status
Simulation time 221910967 ps
CPU time 1.06 seconds
Started Jul 20 04:34:34 PM PDT 24
Finished Jul 20 04:34:39 PM PDT 24
Peak memory 190144 kb
Host smart-41880a1c-be85-45f5-87f1-5c3809f2146a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=840827652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.840827652
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1972121532
Short name T916
Test name
Test status
Simulation time 52428601 ps
CPU time 1.29 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:33:40 PM PDT 24
Peak memory 198460 kb
Host smart-e86b6980-8e0c-4b7a-903b-2cbf7e1b59e7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972121532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1972121532
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.614012242
Short name T876
Test name
Test status
Simulation time 311031440 ps
CPU time 1.31 seconds
Started Jul 20 04:33:42 PM PDT 24
Finished Jul 20 04:33:49 PM PDT 24
Peak memory 192080 kb
Host smart-f6b28e5e-709c-4a79-88d1-6bf5892fc113
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=614012242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.614012242
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3876352349
Short name T908
Test name
Test status
Simulation time 244708346 ps
CPU time 1.34 seconds
Started Jul 20 04:33:30 PM PDT 24
Finished Jul 20 04:33:40 PM PDT 24
Peak memory 198424 kb
Host smart-bd18ca47-3871-43aa-9c61-00a321f182f1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876352349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3876352349
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3357991266
Short name T856
Test name
Test status
Simulation time 52602312 ps
CPU time 1.04 seconds
Started Jul 20 04:33:20 PM PDT 24
Finished Jul 20 04:33:27 PM PDT 24
Peak memory 192032 kb
Host smart-012c8e86-eefe-4484-a255-3e08add64b80
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3357991266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3357991266
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1930774199
Short name T866
Test name
Test status
Simulation time 50459784 ps
CPU time 0.81 seconds
Started Jul 20 04:33:33 PM PDT 24
Finished Jul 20 04:33:43 PM PDT 24
Peak memory 191852 kb
Host smart-2d39a620-d52b-48b0-9686-a7aeef606e19
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930774199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1930774199
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.3880780995
Short name T917
Test name
Test status
Simulation time 123059486 ps
CPU time 1.04 seconds
Started Jul 20 04:33:24 PM PDT 24
Finished Jul 20 04:33:32 PM PDT 24
Peak memory 198416 kb
Host smart-ee5eb280-ee9b-4908-8043-4fa33a0ee65d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3880780995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.3880780995
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2788896740
Short name T899
Test name
Test status
Simulation time 83667288 ps
CPU time 0.8 seconds
Started Jul 20 04:33:38 PM PDT 24
Finished Jul 20 04:33:47 PM PDT 24
Peak memory 191844 kb
Host smart-2fcc7d37-1e27-4f04-abee-92434e993862
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788896740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2788896740
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2671992067
Short name T870
Test name
Test status
Simulation time 89684065 ps
CPU time 1.28 seconds
Started Jul 20 04:33:28 PM PDT 24
Finished Jul 20 04:33:37 PM PDT 24
Peak memory 192120 kb
Host smart-2c7c12cd-d187-4418-9841-926b82114fab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2671992067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2671992067
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.930538825
Short name T907
Test name
Test status
Simulation time 306605725 ps
CPU time 1.15 seconds
Started Jul 20 04:34:21 PM PDT 24
Finished Jul 20 04:34:23 PM PDT 24
Peak memory 191992 kb
Host smart-4e0d5013-99d1-41d1-915b-e88ddb7fe65d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930538825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.930538825
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.1229373764
Short name T874
Test name
Test status
Simulation time 49235364 ps
CPU time 0.84 seconds
Started Jul 20 04:33:33 PM PDT 24
Finished Jul 20 04:33:42 PM PDT 24
Peak memory 196568 kb
Host smart-f8941667-107a-4a06-83b5-25bf097904f0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1229373764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.1229373764
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.666495033
Short name T909
Test name
Test status
Simulation time 176161313 ps
CPU time 1.32 seconds
Started Jul 20 04:33:33 PM PDT 24
Finished Jul 20 04:33:43 PM PDT 24
Peak memory 192064 kb
Host smart-d57bd2cc-97c9-4be8-b060-1b716f7429df
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666495033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.666495033
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3547703568
Short name T852
Test name
Test status
Simulation time 108229551 ps
CPU time 0.91 seconds
Started Jul 20 04:33:33 PM PDT 24
Finished Jul 20 04:33:42 PM PDT 24
Peak memory 191860 kb
Host smart-c43f4255-25a5-4f1e-8dc0-82ae080dbab4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3547703568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3547703568
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1544997206
Short name T861
Test name
Test status
Simulation time 43541150 ps
CPU time 1.08 seconds
Started Jul 20 04:33:33 PM PDT 24
Finished Jul 20 04:33:43 PM PDT 24
Peak memory 192024 kb
Host smart-6fa6956c-7555-4249-bfd6-80cdc6ca0097
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544997206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1544997206
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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