Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	3127967	1			T22	1		T23	94		T24	1
all_pins[1]	3127967	1			T22	1		T23	94		T24	1
all_pins[2]	3127967	1			T22	1		T23	94		T24	1
all_pins[3]	3127967	1			T22	1		T23	94		T24	1
all_pins[4]	3127967	1			T22	1		T23	94		T24	1
all_pins[5]	3127967	1			T22	1		T23	94		T24	1
all_pins[6]	3127967	1			T22	1		T23	94		T24	1
all_pins[7]	3127967	1			T22	1		T23	94		T24	1
all_pins[8]	3127967	1			T22	1		T23	94		T24	1
all_pins[9]	3127967	1			T22	1		T23	94		T24	1
all_pins[10]	3127967	1			T22	1		T23	94		T24	1
all_pins[11]	3127967	1			T22	1		T23	94		T24	1
all_pins[12]	3127967	1			T22	1		T23	94		T24	1
all_pins[13]	3127967	1			T22	1		T23	94		T24	1
all_pins[14]	3127967	1			T22	1		T23	94		T24	1
all_pins[15]	3127967	1			T22	1		T23	94		T24	1
all_pins[16]	3127967	1			T22	1		T23	94		T24	1
all_pins[17]	3127967	1			T22	1		T23	94		T24	1
all_pins[18]	3127967	1			T22	1		T23	94		T24	1
all_pins[19]	3127967	1			T22	1		T23	94		T24	1
all_pins[20]	3127967	1			T22	1		T23	94		T24	1
all_pins[21]	3127967	1			T22	1		T23	94		T24	1
all_pins[22]	3127967	1			T22	1		T23	94		T24	1
all_pins[23]	3127967	1			T22	1		T23	94		T24	1
all_pins[24]	3127967	1			T22	1		T23	94		T24	1
all_pins[25]	3127967	1			T22	1		T23	94		T24	1
all_pins[26]	3127967	1			T22	1		T23	94		T24	1
all_pins[27]	3127967	1			T22	1		T23	94		T24	1
all_pins[28]	3127967	1			T22	1		T23	94		T24	1
all_pins[29]	3127967	1			T22	1		T23	94		T24	1
all_pins[30]	3127967	1			T22	1		T23	94		T24	1
all_pins[31]	3127967	1			T22	1		T23	94		T24	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	62161887	1			T22	32		T23	2368		T24	32
values[0x1]	37933057	1			T23	640		T25	1495		T26	220
transitions[0x0=>0x1]	22717822	1			T23	428		T25	896		T26	100
transitions[0x1=>0x0]	22717674	1			T23	428		T25	895		T26	100

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	1941931	1			T22	1		T23	73		T24	1
all_pins[0]	values[0x1]	1186036	1			T23	21		T25	48		T26	9
all_pins[0]	transitions[0x0=>0x1]	732866	1			T23	20		T25	24		T26	6
all_pins[0]	transitions[0x1=>0x0]	730537	1			T23	15		T25	29		T26	2
all_pins[1]	values[0x0]	1941336	1			T22	1		T23	72		T24	1
all_pins[1]	values[0x1]	1186631	1			T23	22		T25	67		T26	8
all_pins[1]	transitions[0x0=>0x1]	710933	1			T23	13		T25	43		T26	1
all_pins[1]	transitions[0x1=>0x0]	710338	1			T23	12		T25	24		T26	2
all_pins[2]	values[0x0]	1938953	1			T22	1		T23	72		T24	1
all_pins[2]	values[0x1]	1189014	1			T23	22		T25	42		T26	8
all_pins[2]	transitions[0x0=>0x1]	711696	1			T23	14		T25	22		T26	3
all_pins[2]	transitions[0x1=>0x0]	709313	1			T23	14		T25	47		T26	3
all_pins[3]	values[0x0]	1944596	1			T22	1		T23	74		T24	1
all_pins[3]	values[0x1]	1183371	1			T23	20		T25	37		T26	6
all_pins[3]	transitions[0x0=>0x1]	706260	1			T23	10		T25	28		T26	2
all_pins[3]	transitions[0x1=>0x0]	711903	1			T23	12		T25	33		T26	4
all_pins[4]	values[0x0]	1942873	1			T22	1		T23	76		T24	1
all_pins[4]	values[0x1]	1185094	1			T23	18		T25	62		T26	10
all_pins[4]	transitions[0x0=>0x1]	710234	1			T23	12		T25	46		T26	6
all_pins[4]	transitions[0x1=>0x0]	708511	1			T23	14		T25	21		T26	2
all_pins[5]	values[0x0]	1947680	1			T22	1		T23	86		T24	1
all_pins[5]	values[0x1]	1180287	1			T23	8		T25	63		T26	8
all_pins[5]	transitions[0x0=>0x1]	706396	1			T23	5		T25	29		T26	3
all_pins[5]	transitions[0x1=>0x0]	711203	1			T23	15		T25	28		T26	5
all_pins[6]	values[0x0]	1946065	1			T22	1		T23	72		T24	1
all_pins[6]	values[0x1]	1181902	1			T23	22		T25	29		T26	9
all_pins[6]	transitions[0x0=>0x1]	709252	1			T23	18		T25	15		T26	4
all_pins[6]	transitions[0x1=>0x0]	707637	1			T23	4		T25	49		T26	3
all_pins[7]	values[0x0]	1941904	1			T22	1		T23	77		T24	1
all_pins[7]	values[0x1]	1186063	1			T23	17		T25	48		T26	5
all_pins[7]	transitions[0x0=>0x1]	711181	1			T23	10		T25	34		T26	2
all_pins[7]	transitions[0x1=>0x0]	707020	1			T23	15		T25	15		T26	6
all_pins[8]	values[0x0]	1938142	1			T22	1		T23	79		T24	1
all_pins[8]	values[0x1]	1189825	1			T23	15		T25	39		T26	6
all_pins[8]	transitions[0x0=>0x1]	710236	1			T23	8		T25	23		T26	4
all_pins[8]	transitions[0x1=>0x0]	706474	1			T23	10		T25	32		T26	3
all_pins[9]	values[0x0]	1939242	1			T22	1		T23	68		T24	1
all_pins[9]	values[0x1]	1188725	1			T23	26		T25	33		T26	6
all_pins[9]	transitions[0x0=>0x1]	709553	1			T23	16		T25	17		T26	4
all_pins[9]	transitions[0x1=>0x0]	710653	1			T23	5		T25	23		T26	4
all_pins[10]	values[0x0]	1946441	1			T22	1		T23	54		T24	1
all_pins[10]	values[0x1]	1181526	1			T23	40		T25	45		T26	3
all_pins[10]	transitions[0x0=>0x1]	707471	1			T23	23		T25	38		T27	118
all_pins[10]	transitions[0x1=>0x0]	714670	1			T23	9		T25	26		T26	3
all_pins[11]	values[0x0]	1945714	1			T22	1		T23	77		T24	1
all_pins[11]	values[0x1]	1182253	1			T23	17		T25	31		T26	7
all_pins[11]	transitions[0x0=>0x1]	709292	1			T23	6		T25	14		T26	4
all_pins[11]	transitions[0x1=>0x0]	708565	1			T23	29		T25	28		T27	84
all_pins[12]	values[0x0]	1944656	1			T22	1		T23	72		T24	1
all_pins[12]	values[0x1]	1183311	1			T23	22		T25	62		T26	7
all_pins[12]	transitions[0x0=>0x1]	707837	1			T23	16		T25	46		T26	4
all_pins[12]	transitions[0x1=>0x0]	706779	1			T23	11		T25	15		T26	4
all_pins[13]	values[0x0]	1939865	1			T22	1		T23	62		T24	1
all_pins[13]	values[0x1]	1188102	1			T23	32		T25	42		T26	8
all_pins[13]	transitions[0x0=>0x1]	712099	1			T23	20		T25	23		T26	4
all_pins[13]	transitions[0x1=>0x0]	707308	1			T23	10		T25	43		T26	3
all_pins[14]	values[0x0]	1942225	1			T22	1		T23	84		T24	1
all_pins[14]	values[0x1]	1185742	1			T23	10		T25	49		T26	9
all_pins[14]	transitions[0x0=>0x1]	707070	1			T25	33		T26	4		T27	68
all_pins[14]	transitions[0x1=>0x0]	709430	1			T23	22		T25	26		T26	3
all_pins[15]	values[0x0]	1940108	1			T22	1		T23	64		T24	1
all_pins[15]	values[0x1]	1187859	1			T23	30		T25	37		T26	6
all_pins[15]	transitions[0x0=>0x1]	710592	1			T23	22		T25	25		T26	2
all_pins[15]	transitions[0x1=>0x0]	708475	1			T23	2		T25	37		T26	5
all_pins[16]	values[0x0]	1942040	1			T22	1		T23	75		T24	1
all_pins[16]	values[0x1]	1185927	1			T23	19		T25	55		T26	8
all_pins[16]	transitions[0x0=>0x1]	709410	1			T23	6		T25	27		T26	3
all_pins[16]	transitions[0x1=>0x0]	711342	1			T23	17		T25	9		T26	1
all_pins[17]	values[0x0]	1939794	1			T22	1		T23	86		T24	1
all_pins[17]	values[0x1]	1188173	1			T23	8		T25	55		T26	9
all_pins[17]	transitions[0x0=>0x1]	711685	1			T23	7		T25	26		T26	2
all_pins[17]	transitions[0x1=>0x0]	709439	1			T23	18		T25	26		T26	1
all_pins[18]	values[0x0]	1942395	1			T22	1		T23	76		T24	1
all_pins[18]	values[0x1]	1185572	1			T23	18		T25	52		T26	5
all_pins[18]	transitions[0x0=>0x1]	707050	1			T23	15		T25	31		T26	1
all_pins[18]	transitions[0x1=>0x0]	709651	1			T23	5		T25	34		T26	5
all_pins[19]	values[0x0]	1941598	1			T22	1		T23	67		T24	1
all_pins[19]	values[0x1]	1186369	1			T23	27		T25	38		T26	7
all_pins[19]	transitions[0x0=>0x1]	709884	1			T23	21		T25	24		T26	4
all_pins[19]	transitions[0x1=>0x0]	709087	1			T23	12		T25	38		T26	2
all_pins[20]	values[0x0]	1940789	1			T22	1		T23	74		T24	1
all_pins[20]	values[0x1]	1187178	1			T23	20		T25	50		T26	9
all_pins[20]	transitions[0x0=>0x1]	710479	1			T23	13		T25	29		T26	3
all_pins[20]	transitions[0x1=>0x0]	709670	1			T23	20		T25	17		T26	1
all_pins[21]	values[0x0]	1938981	1			T22	1		T23	86		T24	1
all_pins[21]	values[0x1]	1188986	1			T23	8		T25	54		T26	4
all_pins[21]	transitions[0x0=>0x1]	709523	1			T23	5		T25	29		T27	65
all_pins[21]	transitions[0x1=>0x0]	707715	1			T23	17		T25	25		T26	5
all_pins[22]	values[0x0]	1937084	1			T22	1		T23	65		T24	1
all_pins[22]	values[0x1]	1190883	1			T23	29		T25	46		T26	7
all_pins[22]	transitions[0x0=>0x1]	713165	1			T23	25		T25	17		T26	5
all_pins[22]	transitions[0x1=>0x0]	711268	1			T23	4		T25	25		T26	2
all_pins[23]	values[0x0]	1942535	1			T22	1		T23	75		T24	1
all_pins[23]	values[0x1]	1185432	1			T23	19		T25	54		T26	8
all_pins[23]	transitions[0x0=>0x1]	705295	1			T23	15		T25	27		T26	3
all_pins[23]	transitions[0x1=>0x0]	710746	1			T23	25		T25	19		T26	2
all_pins[24]	values[0x0]	1943869	1			T22	1		T23	75		T24	1
all_pins[24]	values[0x1]	1184098	1			T23	19		T25	31		T26	6
all_pins[24]	transitions[0x0=>0x1]	708540	1			T23	13		T25	20		T26	4
all_pins[24]	transitions[0x1=>0x0]	709874	1			T23	13		T25	43		T26	6
all_pins[25]	values[0x0]	1945735	1			T22	1		T23	75		T24	1
all_pins[25]	values[0x1]	1182232	1			T23	19		T25	56		T26	7
all_pins[25]	transitions[0x0=>0x1]	708001	1			T23	11		T25	40		T26	4
all_pins[25]	transitions[0x1=>0x0]	709867	1			T23	11		T25	15		T26	3
all_pins[26]	values[0x0]	1946938	1			T22	1		T23	74		T24	1
all_pins[26]	values[0x1]	1181029	1			T23	20		T25	45		T26	7
all_pins[26]	transitions[0x0=>0x1]	706804	1			T23	14		T25	32		T26	4
all_pins[26]	transitions[0x1=>0x0]	708007	1			T23	13		T25	43		T26	4
all_pins[27]	values[0x0]	1943419	1			T22	1		T23	75		T24	1
all_pins[27]	values[0x1]	1184548	1			T23	19		T25	68		T26	7
all_pins[27]	transitions[0x0=>0x1]	710995	1			T23	15		T25	45		T26	3
all_pins[27]	transitions[0x1=>0x0]	707476	1			T23	16		T25	22		T26	3
all_pins[28]	values[0x0]	1944742	1			T22	1		T23	81		T24	1
all_pins[28]	values[0x1]	1183225	1			T23	13		T25	31		T26	5
all_pins[28]	transitions[0x0=>0x1]	706547	1			T23	13		T25	13		T26	3
all_pins[28]	transitions[0x1=>0x0]	707870	1			T23	19		T25	50		T26	5
all_pins[29]	values[0x0]	1938939	1			T22	1		T23	69		T24	1
all_pins[29]	values[0x1]	1189028	1			T23	25		T25	48		T26	6
all_pins[29]	transitions[0x0=>0x1]	712441	1			T23	22		T25	28		T26	4
all_pins[29]	transitions[0x1=>0x0]	706638	1			T23	10		T25	11		T26	3
all_pins[30]	values[0x0]	1947186	1			T22	1		T23	75		T24	1
all_pins[30]	values[0x1]	1180781	1			T23	19		T25	24		T26	5
all_pins[30]	transitions[0x0=>0x1]	704777	1			T23	13		T25	7		T26	2
all_pins[30]	transitions[0x1=>0x0]	713024	1			T23	19		T25	31		T26	3
all_pins[31]	values[0x0]	1944112	1			T22	1		T23	78		T24	1
all_pins[31]	values[0x1]	1183855	1			T23	16		T25	54		T26	5
all_pins[31]	transitions[0x0=>0x1]	710258	1			T23	7		T25	41		T26	2
all_pins[31]	transitions[0x1=>0x0]	707184	1			T23	10		T25	11		T26	2