Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	11122005	1			T22	410		T23	171		T24	1
all_values[1]	11122005	1			T22	410		T23	171		T24	1
all_values[2]	11122005	1			T22	410		T23	171		T24	1
all_values[3]	11122005	1			T22	410		T23	171		T24	1
all_values[4]	11122005	1			T22	410		T23	171		T24	1
all_values[5]	11122005	1			T22	410		T23	171		T24	1
all_values[6]	11122005	1			T22	410		T23	171		T24	1
all_values[7]	11122005	1			T22	410		T23	171		T24	1
all_values[8]	11122005	1			T22	410		T23	171		T24	1
all_values[9]	11122005	1			T22	410		T23	171		T24	1
all_values[10]	11122005	1			T22	410		T23	171		T24	1
all_values[11]	11122005	1			T22	410		T23	171		T24	1
all_values[12]	11122005	1			T22	410		T23	171		T24	1
all_values[13]	11122005	1			T22	410		T23	171		T24	1
all_values[14]	11122005	1			T22	410		T23	171		T24	1
all_values[15]	11122005	1			T22	410		T23	171		T24	1
all_values[16]	11122005	1			T22	410		T23	171		T24	1
all_values[17]	11122005	1			T22	410		T23	171		T24	1
all_values[18]	11122005	1			T22	410		T23	171		T24	1
all_values[19]	11122005	1			T22	410		T23	171		T24	1
all_values[20]	11122005	1			T22	410		T23	171		T24	1
all_values[21]	11122005	1			T22	410		T23	171		T24	1
all_values[22]	11122005	1			T22	410		T23	171		T24	1
all_values[23]	11122005	1			T22	410		T23	171		T24	1
all_values[24]	11122005	1			T22	410		T23	171		T24	1
all_values[25]	11122005	1			T22	410		T23	171		T24	1
all_values[26]	11122005	1			T22	410		T23	171		T24	1
all_values[27]	11122005	1			T22	410		T23	171		T24	1
all_values[28]	11122005	1			T22	410		T23	171		T24	1
all_values[29]	11122005	1			T22	410		T23	171		T24	1
all_values[30]	11122005	1			T22	410		T23	171		T24	1
all_values[31]	11122005	1			T22	410		T23	171		T24	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

215185162

1

T22

13120

T23

3727

T24

32

auto[1]

140718998

1

T23

1745

T25

3221

T27

17135

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101351866

1

T22

13120

T23

2697

T24

32

auto[1]

254552294

1

T23

2775

T25

5129

T27

27984

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

352219079

1

T22

13120

T23

5138

T24

32

auto[1]

3685081

1

T23

334

T27

1259

T32

159441

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2740428	1			T22	410		T23	66		T24	1
all_values[0]	auto[0]	auto[0]	auto[1]	3906254	1			T23	43		T25	57		T27	323
all_values[0]	auto[0]	auto[1]	auto[0]	428119	1			T23	21		T25	37		T27	112
all_values[0]	auto[0]	auto[1]	auto[1]	3931879	1			T23	32		T25	83		T27	454
all_values[0]	auto[1]	auto[0]	auto[1]	57994	1			T23	7		T27	12		T32	2497
all_values[0]	auto[1]	auto[1]	auto[1]	57331	1			T23	2		T27	24		T32	2483
all_values[1]	auto[0]	auto[0]	auto[0]	2751459	1			T22	410		T23	62		T24	1
all_values[1]	auto[0]	auto[0]	auto[1]	3905262	1			T23	39		T25	64		T27	372
all_values[1]	auto[0]	auto[1]	auto[0]	434334	1			T23	30		T25	11		T27	43
all_values[1]	auto[0]	auto[1]	auto[1]	3915719	1			T23	32		T25	112		T27	475
all_values[1]	auto[1]	auto[0]	auto[1]	57840	1			T23	8		T27	18		T32	2512
all_values[1]	auto[1]	auto[1]	auto[1]	57391	1			T27	25		T32	2453		T1	13
all_values[2]	auto[0]	auto[0]	auto[0]	2738243	1			T22	410		T23	61		T24	1
all_values[2]	auto[0]	auto[0]	auto[1]	3914810	1			T23	31		T25	86		T27	395
all_values[2]	auto[0]	auto[1]	auto[0]	433831	1			T23	33		T25	9		T27	38
all_values[2]	auto[0]	auto[1]	auto[1]	3920480	1			T23	36		T25	70		T27	449
all_values[2]	auto[1]	auto[0]	auto[1]	57595	1			T23	7		T27	23		T32	2505
all_values[2]	auto[1]	auto[1]	auto[1]	57046	1			T23	3		T27	21		T32	2448
all_values[3]	auto[0]	auto[0]	auto[0]	2737893	1			T22	410		T23	63		T24	1
all_values[3]	auto[0]	auto[0]	auto[1]	3933157	1			T23	41		T25	83		T27	303
all_values[3]	auto[0]	auto[1]	auto[0]	426439	1			T23	27		T25	35		T27	92
all_values[3]	auto[0]	auto[1]	auto[1]	3909730	1			T23	29		T25	67		T27	519
all_values[3]	auto[1]	auto[0]	auto[1]	57526	1			T23	8		T27	15		T32	2513
all_values[3]	auto[1]	auto[1]	auto[1]	57260	1			T23	3		T27	22		T32	2401
all_values[4]	auto[0]	auto[0]	auto[0]	2738172	1			T22	410		T23	74		T24	1
all_values[4]	auto[0]	auto[0]	auto[1]	3899169	1			T23	46		T25	51		T27	569
all_values[4]	auto[0]	auto[1]	auto[0]	430132	1			T23	14		T25	13		T27	42
all_values[4]	auto[0]	auto[1]	auto[1]	3939338	1			T23	27		T25	98		T27	231
all_values[4]	auto[1]	auto[0]	auto[1]	57213	1			T23	6		T27	26		T32	2482
all_values[4]	auto[1]	auto[1]	auto[1]	57981	1			T23	4		T27	12		T32	2549
all_values[5]	auto[0]	auto[0]	auto[0]	2738131	1			T22	410		T23	67		T24	1
all_values[5]	auto[0]	auto[0]	auto[1]	3938335	1			T23	68		T25	65		T27	405
all_values[5]	auto[0]	auto[1]	auto[0]	431807	1			T23	15		T25	15		T27	87
all_values[5]	auto[0]	auto[1]	auto[1]	3898395	1			T23	11		T25	98		T27	412
all_values[5]	auto[1]	auto[0]	auto[1]	57955	1			T23	9		T27	25		T32	2480
all_values[5]	auto[1]	auto[1]	auto[1]	57382	1			T23	1		T27	20		T32	2442
all_values[6]	auto[0]	auto[0]	auto[0]	2729901	1			T22	410		T23	71		T24	1
all_values[6]	auto[0]	auto[0]	auto[1]	3942721	1			T23	47		T25	95		T27	491
all_values[6]	auto[0]	auto[1]	auto[0]	428580	1			T23	14		T25	15		T27	111
all_values[6]	auto[0]	auto[1]	auto[1]	3905992	1			T23	30		T25	59		T27	264
all_values[6]	auto[1]	auto[0]	auto[1]	57742	1			T23	6		T27	17		T32	2527
all_values[6]	auto[1]	auto[1]	auto[1]	57069	1			T23	3		T27	13		T32	2481
all_values[7]	auto[0]	auto[0]	auto[0]	2737046	1			T22	410		T23	65		T24	1
all_values[7]	auto[0]	auto[0]	auto[1]	3953622	1			T23	44		T25	98		T27	255
all_values[7]	auto[0]	auto[1]	auto[0]	429543	1			T23	29		T25	1		T27	138
all_values[7]	auto[0]	auto[1]	auto[1]	3886458	1			T23	22		T25	66		T27	524
all_values[7]	auto[1]	auto[0]	auto[1]	57843	1			T23	8		T27	16		T32	2551
all_values[7]	auto[1]	auto[1]	auto[1]	57493	1			T23	3		T27	26		T32	2515
all_values[8]	auto[0]	auto[0]	auto[0]	2731704	1			T22	410		T23	50		T24	1
all_values[8]	auto[0]	auto[0]	auto[1]	3913538	1			T23	69		T25	113		T27	544
all_values[8]	auto[0]	auto[1]	auto[0]	432399	1			T23	24		T25	10		T27	26
all_values[8]	auto[0]	auto[1]	auto[1]	3929115	1			T23	13		T25	64		T27	350
all_values[8]	auto[1]	auto[0]	auto[1]	57587	1			T23	10		T27	25		T32	2329
all_values[8]	auto[1]	auto[1]	auto[1]	57662	1			T23	5		T27	15		T32	2572
all_values[9]	auto[0]	auto[0]	auto[0]	2735158	1			T22	410		T23	42		T24	1
all_values[9]	auto[0]	auto[0]	auto[1]	3938223	1			T23	49		T25	87		T27	312
all_values[9]	auto[0]	auto[1]	auto[0]	425121	1			T23	34		T25	22		T27	92
all_values[9]	auto[0]	auto[1]	auto[1]	3908158	1			T23	34		T25	60		T27	511
all_values[9]	auto[1]	auto[0]	auto[1]	57967	1			T23	9		T27	13		T32	2516
all_values[9]	auto[1]	auto[1]	auto[1]	57378	1			T23	3		T27	27		T32	2409
all_values[10]	auto[0]	auto[0]	auto[0]	2739414	1			T22	410		T23	35		T24	1
all_values[10]	auto[0]	auto[0]	auto[1]	3962252	1			T23	44		T25	92		T27	273
all_values[10]	auto[0]	auto[1]	auto[0]	426528	1			T23	25		T25	27		T27	46
all_values[10]	auto[0]	auto[1]	auto[1]	3878874	1			T23	54		T25	77		T27	569
all_values[10]	auto[1]	auto[0]	auto[1]	57984	1			T23	8		T27	20		T32	2531
all_values[10]	auto[1]	auto[1]	auto[1]	56953	1			T23	5		T27	24		T32	2460
all_values[11]	auto[0]	auto[0]	auto[0]	2740062	1			T22	410		T23	68		T24	1
all_values[11]	auto[0]	auto[0]	auto[1]	3938457	1			T23	41		T25	93		T27	228
all_values[11]	auto[0]	auto[1]	auto[0]	428532	1			T23	29		T25	23		T27	92
all_values[11]	auto[0]	auto[1]	auto[1]	3900159	1			T23	23		T25	56		T27	621
all_values[11]	auto[1]	auto[0]	auto[1]	57413	1			T23	9		T27	11		T32	2457
all_values[11]	auto[1]	auto[1]	auto[1]	57382	1			T23	1		T27	27		T32	2469
all_values[12]	auto[0]	auto[0]	auto[0]	2737163	1			T22	410		T23	57		T24	1
all_values[12]	auto[0]	auto[0]	auto[1]	3922899	1			T23	51		T25	73		T27	436
all_values[12]	auto[0]	auto[1]	auto[0]	430256	1			T23	17		T25	11		T27	122
all_values[12]	auto[0]	auto[1]	auto[1]	3916839	1			T23	33		T25	109		T27	353
all_values[12]	auto[1]	auto[0]	auto[1]	57641	1			T23	11		T27	19		T32	2525
all_values[12]	auto[1]	auto[1]	auto[1]	57207	1			T23	2		T27	16		T32	2460
all_values[13]	auto[0]	auto[0]	auto[0]	2736026	1			T22	410		T23	51		T24	1
all_values[13]	auto[0]	auto[0]	auto[1]	3919620	1			T23	49		T25	98		T27	286
all_values[13]	auto[0]	auto[1]	auto[0]	419837	1			T23	15		T25	13		T27	120
all_values[13]	auto[0]	auto[1]	auto[1]	3931664	1			T23	45		T25	78		T27	505
all_values[13]	auto[1]	auto[0]	auto[1]	57655	1			T23	9		T27	15		T32	2441
all_values[13]	auto[1]	auto[1]	auto[1]	57203	1			T23	2		T27	27		T32	2504
all_values[14]	auto[0]	auto[0]	auto[0]	2741157	1			T22	410		T23	63		T24	1
all_values[14]	auto[0]	auto[0]	auto[1]	3925307	1			T23	53		T25	48		T27	524
all_values[14]	auto[0]	auto[1]	auto[0]	433689	1			T23	27		T25	39		T27	31
all_values[14]	auto[0]	auto[1]	auto[1]	3906825	1			T23	16		T25	90		T27	353
all_values[14]	auto[1]	auto[0]	auto[1]	57724	1			T23	11		T27	26		T32	2549
all_values[14]	auto[1]	auto[1]	auto[1]	57303	1			T23	1		T27	18		T32	2423
all_values[15]	auto[0]	auto[0]	auto[0]	2737487	1			T22	410		T23	61		T24	1
all_values[15]	auto[0]	auto[0]	auto[1]	3929846	1			T23	35		T25	112		T27	323
all_values[15]	auto[0]	auto[1]	auto[0]	422717	1			T23	22		T25	17		T27	53
all_values[15]	auto[0]	auto[1]	auto[1]	3916870	1			T23	46		T25	64		T27	565
all_values[15]	auto[1]	auto[0]	auto[1]	57688	1			T23	5		T27	17		T32	2521
all_values[15]	auto[1]	auto[1]	auto[1]	57397	1			T23	2		T27	24		T32	2494
all_values[16]	auto[0]	auto[0]	auto[0]	2740345	1			T22	410		T23	46		T24	1
all_values[16]	auto[0]	auto[0]	auto[1]	3931018	1			T23	63		T25	72		T27	389
all_values[16]	auto[0]	auto[1]	auto[0]	422100	1			T23	18		T25	16		T27	69
all_values[16]	auto[0]	auto[1]	auto[1]	3913394	1			T23	32		T25	88		T27	471
all_values[16]	auto[1]	auto[0]	auto[1]	57600	1			T23	10		T27	12		T32	2444
all_values[16]	auto[1]	auto[1]	auto[1]	57548	1			T23	2		T27	25		T32	2543
all_values[17]	auto[0]	auto[0]	auto[0]	2742009	1			T22	410		T23	75		T24	1
all_values[17]	auto[0]	auto[0]	auto[1]	3931791	1			T23	62		T25	46		T27	345
all_values[17]	auto[0]	auto[1]	auto[0]	429938	1			T23	13		T25	32		T27	90
all_values[17]	auto[0]	auto[1]	auto[1]	3903013	1			T23	12		T25	99		T27	467
all_values[17]	auto[1]	auto[0]	auto[1]	57599	1			T23	8		T27	16		T32	2399
all_values[17]	auto[1]	auto[1]	auto[1]	57655	1			T23	1		T27	25		T32	2532
all_values[18]	auto[0]	auto[0]	auto[0]	2729168	1			T22	410		T23	45		T24	1
all_values[18]	auto[0]	auto[0]	auto[1]	3917121	1			T23	52		T25	73		T27	352
all_values[18]	auto[0]	auto[1]	auto[0]	429916	1			T23	41		T25	12		T27	102
all_values[18]	auto[0]	auto[1]	auto[1]	3929914	1			T23	23		T25	97		T27	447
all_values[18]	auto[1]	auto[0]	auto[1]	58233	1			T23	7		T27	14		T32	2564
all_values[18]	auto[1]	auto[1]	auto[1]	57653	1			T23	3		T27	22		T32	2396
all_values[19]	auto[0]	auto[0]	auto[0]	2745291	1			T22	410		T23	54		T24	1
all_values[19]	auto[0]	auto[0]	auto[1]	3933178	1			T23	52		T25	98		T27	396
all_values[19]	auto[0]	auto[1]	auto[0]	426640	1			T23	16		T25	21		T27	66
all_values[19]	auto[0]	auto[1]	auto[1]	3902066	1			T23	37		T25	66		T27	452
all_values[19]	auto[1]	auto[0]	auto[1]	57747	1			T23	9		T27	14		T32	2449
all_values[19]	auto[1]	auto[1]	auto[1]	57083	1			T23	3		T27	21		T32	2487
all_values[20]	auto[0]	auto[0]	auto[0]	2742706	1			T22	410		T23	64		T24	1
all_values[20]	auto[0]	auto[0]	auto[1]	3914821	1			T23	39		T25	92		T27	323
all_values[20]	auto[0]	auto[1]	auto[0]	430916	1			T23	31		T25	17		T27	70
all_values[20]	auto[0]	auto[1]	auto[1]	3918069	1			T23	26		T25	84		T27	531
all_values[20]	auto[1]	auto[0]	auto[1]	57943	1			T23	7		T27	20		T32	2430
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all_values[21]	auto[0]	auto[1]	auto[0]	425084	1			T23	10		T25	5		T27	104
all_values[21]	auto[0]	auto[1]	auto[1]	3928469	1			T23	11		T25	95		T27	483
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all_values[21]	auto[1]	auto[1]	auto[1]	57503	1			T23	1		T27	26		T32	2480
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all_values[22]	auto[1]	auto[1]	auto[1]	57556	1			T23	6		T27	17		T32	2523
all_values[23]	auto[0]	auto[0]	auto[0]	2734576	1			T22	410		T23	56		T24	1
all_values[23]	auto[0]	auto[0]	auto[1]	3912400	1			T23	60		T25	40		T27	425
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all_values[25]	auto[1]	auto[1]	auto[1]	57056	1			T23	1		T27	22		T32	2478
all_values[26]	auto[0]	auto[0]	auto[0]	2743624	1			T22	410		T23	57		T24	1
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all_values[26]	auto[1]	auto[1]	auto[1]	57163	1			T23	3		T27	28		T32	2496
all_values[27]	auto[0]	auto[0]	auto[0]	2744443	1			T22	410		T23	57		T24	1
all_values[27]	auto[0]	auto[0]	auto[1]	3917828	1			T23	33		T25	57		T27	510
all_values[27]	auto[0]	auto[1]	auto[0]	432543	1			T23	48		T25	13		T27	42
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all_values[27]	auto[1]	auto[1]	auto[1]	57255	1			T23	4		T27	14		T32	2458
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all_values[28]	auto[0]	auto[1]	auto[0]	437916	1			T23	19		T27	32		T110	96
all_values[28]	auto[0]	auto[1]	auto[1]	3922167	1			T23	21		T25	58		T27	402
all_values[28]	auto[1]	auto[0]	auto[1]	57640	1			T23	5		T27	24		T32	2486
all_values[28]	auto[1]	auto[1]	auto[1]	57622	1			T27	24		T32	2491		T1	19
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all_values[29]	auto[0]	auto[0]	auto[1]	3931342	1			T23	64		T25	56		T27	390
all_values[29]	auto[0]	auto[1]	auto[0]	422072	1			T23	25		T25	30		T27	66
all_values[29]	auto[0]	auto[1]	auto[1]	3915116	1			T23	29		T25	89		T27	431
all_values[29]	auto[1]	auto[0]	auto[1]	57952	1			T23	7		T27	21		T32	2424
all_values[29]	auto[1]	auto[1]	auto[1]	57346	1			T23	3		T27	19		T32	2552
all_values[30]	auto[0]	auto[0]	auto[0]	2740082	1			T22	410		T23	70		T24	1
all_values[30]	auto[0]	auto[0]	auto[1]	3924534	1			T23	37		T25	115		T27	624
all_values[30]	auto[0]	auto[1]	auto[0]	432083	1			T23	30		T25	17		T27	30
all_values[30]	auto[0]	auto[1]	auto[1]	3909836	1			T23	27		T25	36		T27	257
all_values[30]	auto[1]	auto[0]	auto[1]	57896	1			T23	5		T27	23		T32	2552
all_values[30]	auto[1]	auto[1]	auto[1]	57574	1			T23	2		T27	17		T32	2527
all_values[31]	auto[0]	auto[0]	auto[0]	2738919	1			T22	410		T23	61		T24	1
all_values[31]	auto[0]	auto[0]	auto[1]	3928021	1			T23	49		T25	67		T27	332
all_values[31]	auto[0]	auto[1]	auto[0]	427369	1			T23	27		T25	22		T27	52
all_values[31]	auto[0]	auto[1]	auto[1]	3912552	1			T23	23		T25	93		T27	502
all_values[31]	auto[1]	auto[0]	auto[1]	57923	1			T23	9		T27	22		T32	2547
all_values[31]	auto[1]	auto[1]	auto[1]	57221	1			T23	2		T27	15		T32	2505

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal