Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[1]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[2]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[3]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[4]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[5]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[6]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[7]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[8]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[9]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[10]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[11]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[12]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[13]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[14]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[15]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[16]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[17]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[18]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[19]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[20]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[21]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[22]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[23]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[24]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[25]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[26]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[27]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[28]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[29]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[30]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[31]	10951549	1			T22	728		T23	168		T24	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

203773887

1

T22

16871

T23

2560

T24

32

auto[1]

146675681

1

T22

6425

T23

2816

T25

1383

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

285158710

1

T22

13258

T23

4994

T24

32

auto[1]

65290858

1

T22

10038

T23

382

T27

13002

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

266183103

1

T22

13238

T23

3828

T24

32

auto[1]

84266465

1

T22

10058

T23

1548

T27

14947

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	4090334	1			T22	209		T23	96		T24	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3200105	1			T22	44		T23	36		T25	53
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1025772	1			T22	140		T23	1		T27	300
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1247881	1			T22	186		T23	32		T27	10
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	372738	1			T23	3		T27	215		T28	97
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1014719	1			T22	149		T27	145		T28	12
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	4098436	1			T22	192		T23	65		T24	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3197105	1			T22	49		T23	32		T25	47
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1025384	1			T22	183		T23	6		T27	250
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1242966	1			T22	166		T23	32		T27	6
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	369825	1			T23	15		T27	157		T28	89
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1017833	1			T22	138		T23	18		T27	223
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	4088727	1			T22	249		T23	57		T24	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3202576	1			T22	45		T23	84		T25	40
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1027197	1			T22	158		T23	1		T27	121
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1243619	1			T22	174		T23	6		T27	18
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	371295	1			T23	10		T27	300		T28	104
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1018135	1			T22	102		T23	10		T27	254
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	4104668	1			T22	209		T23	10		T24	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3189710	1			T22	58		T23	92		T25	52
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1023304	1			T22	149		T23	1		T27	215
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1246255	1			T22	156		T23	10		T27	7
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	372274	1			T23	31		T27	182		T28	64
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1015338	1			T22	156		T23	24		T27	186
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	4089038	1			T22	205		T23	59		T24	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3202517	1			T22	46		T23	73		T25	32
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1027032	1			T22	150		T27	245		T28	16
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1240622	1			T22	145		T23	12		T27	6
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	373899	1			T23	17		T27	212		T28	108
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1018441	1			T22	182		T23	7		T27	217
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	4095787	1			T22	196		T23	86		T24	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3199385	1			T22	43		T23	35		T25	48
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1025191	1			T22	125		T23	12		T27	162
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1241215	1			T22	196		T23	15		T27	17
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	371517	1			T23	14		T27	251		T28	91
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1018454	1			T22	168		T23	6		T27	186
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	4102856	1			T22	240		T23	69		T24	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3190087	1			T22	35		T23	27		T25	50
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1028205	1			T22	153		T23	4		T27	265
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1243290	1			T22	152		T23	54		T27	11
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	370714	1			T23	9		T27	209		T28	110
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1016397	1			T22	148		T23	5		T27	218
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	4096673	1			T22	206		T23	93		T24	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3190710	1			T22	51		T23	52		T25	47
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1022017	1			T22	160		T23	2		T27	157
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1247742	1			T22	150		T23	18		T27	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	373296	1			T23	3		T27	262		T28	67
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1021111	1			T22	161		T27	233		T28	14
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	4092046	1			T22	186		T23	83		T24	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3193336	1			T22	53		T23	29		T25	41
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1025001	1			T22	149		T27	173		T28	6
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1251232	1			T22	160		T23	34		T27	15
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	373778	1			T23	17		T27	268		T28	106
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1016156	1			T22	180		T23	5		T27	235
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	4096940	1			T22	216		T23	24		T24	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3194295	1			T22	42		T23	59		T25	42
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1026587	1			T22	178		T27	167		T28	14
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1244402	1			T22	154		T23	23		T27	16
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	369932	1			T23	41		T27	292		T28	92
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1019393	1			T22	138		T23	21		T27	256
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	4102109	1			T22	196		T23	25		T24	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3187972	1			T22	38		T23	93		T25	30
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1026144	1			T22	134		T27	170		T28	16
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1243170	1			T22	174		T23	22		T27	15
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	373936	1			T23	21		T27	277		T28	64
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1018218	1			T22	186		T23	7		T27	208
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	4094973	1			T22	182		T23	38		T24	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3190817	1			T22	47		T23	79		T25	34
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1024482	1			T22	160		T23	5		T27	229
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1242455	1			T22	151		T23	19		T27	18
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	377109	1			T23	24		T27	291		T28	77
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1021713	1			T22	188		T23	3		T27	194
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	4091150	1			T22	180		T23	31		T24	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3201553	1			T22	49		T23	66		T25	41
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1028378	1			T22	192		T27	127		T28	8
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1241022	1			T22	166		T23	31		T27	12
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	372230	1			T23	26		T27	296		T28	143
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1017216	1			T22	141		T23	14		T27	166
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	4104107	1			T22	201		T23	24		T24	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3186199	1			T22	42		T23	78		T25	51
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1030039	1			T22	141		T27	221		T28	12
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1239833	1			T22	168		T23	19		T27	13
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	372851	1			T23	38		T27	219		T28	79
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1018520	1			T22	176		T23	9		T27	289
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	4085081	1			T22	174		T23	63		T24	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3207433	1			T22	47		T23	55		T25	43
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1028206	1			T22	175		T27	194		T28	25
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1244119	1			T22	162		T23	37		T27	6
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	374755	1			T23	6		T27	234		T28	31
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1011955	1			T22	170		T23	7		T27	258
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	4094234	1			T22	210		T23	55		T24	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3194604	1			T22	49		T23	39		T25	44
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1023098	1			T22	146		T23	5		T27	167
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1250328	1			T22	172		T23	34		T27	7
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	370939	1			T23	22		T27	266		T28	94
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1018346	1			T22	151		T23	13		T27	166
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	4086309	1			T22	247		T23	41		T24	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3201371	1			T22	46		T23	72		T25	55
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1025203	1			T22	163		T23	11		T27	206
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1247878	1			T22	170		T23	24		T27	7
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	374830	1			T23	13		T27	262		T28	121
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1015958	1			T22	102		T23	7		T27	199
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	4109693	1			T22	219		T23	60		T24	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3185790	1			T22	39		T23	42		T25	37
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1021175	1			T22	182		T23	1		T27	159
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1249177	1			T22	154		T23	36		T27	16
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	372383	1			T23	11		T27	247		T28	99
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1013331	1			T22	134		T23	18		T27	211
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	4105607	1			T22	225		T23	36		T24	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3190802	1			T22	54		T23	85		T25	34
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1027241	1			T22	158		T23	7		T27	205
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1239514	1			T22	149		T23	5		T27	11
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	373752	1			T23	14		T27	200		T28	122
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1014633	1			T22	142		T23	21		T27	225
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	4099337	1			T22	182		T23	30		T24	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3204059	1			T22	47		T23	105		T25	51
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1023336	1			T22	172		T27	224		T28	2
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1240744	1			T22	155		T23	15		T27	3
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	373815	1			T23	14		T27	192		T28	77
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1010258	1			T22	172		T23	4		T27	137
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	4106704	1			T22	174		T23	83		T24	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3190515	1			T22	50		T23	45		T25	41
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1025768	1			T22	196		T27	255		T28	6
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1244249	1			T22	136		T23	24		T27	12
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	372027	1			T23	16		T27	245		T28	103
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1012286	1			T22	172		T27	221		T28	12
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	4097111	1			T22	204		T23	77		T24	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3196745	1			T22	37		T23	40		T25	49
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1022428	1			T22	172		T23	4		T27	163
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1249321	1			T22	155		T23	39		T27	12
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	374391	1			T23	4		T27	280		T28	50
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1011553	1			T22	160		T23	4		T27	202
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	4094982	1			T22	203		T23	77		T24	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3201728	1			T22	48		T23	36		T25	42
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1022753	1			T22	205		T27	96		T28	16
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1248750	1			T22	156		T23	46		T27	16
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	369288	1			T23	8		T27	306		T28	65
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1014048	1			T22	116		T23	1		T27	239
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	4107448	1			T22	195		T23	81		T24	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3190496	1			T22	46		T23	45		T25	50
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1025752	1			T22	140		T23	8		T27	199
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1243144	1			T22	179		T23	23		T27	21
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	372921	1			T23	9		T27	243		T28	111
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1011788	1			T22	168		T23	2		T27	165
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	4098066	1			T22	233		T23	27		T24	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3195366	1			T22	42		T23	76		T25	53
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1025586	1			T22	154		T27	224		T28	6
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1246213	1			T22	145		T23	26		T27	4
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	373257	1			T23	29		T27	260		T28	107
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1013061	1			T22	154		T23	10		T27	201
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	4093007	1			T22	216		T23	89		T24	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3201996	1			T22	45		T23	52		T25	49
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1022403	1			T22	168		T23	4		T27	216
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1247414	1			T22	146		T23	14		T27	10
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	371866	1			T23	9		T27	236		T28	117
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1014863	1			T22	153		T27	268		T28	15
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	4097493	1			T22	227		T23	30		T24	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3191459	1			T22	46		T23	74		T25	43
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1017664	1			T22	139		T23	1		T27	176
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1249367	1			T22	178		T23	18		T27	14
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	374588	1			T23	23		T27	295		T28	152
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1020978	1			T22	138		T23	22		T27	180
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	4104007	1			T22	258		T23	67		T24	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3195149	1			T22	46		T23	72		T25	41
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1027047	1			T22	164		T23	1		T27	240
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1240510	1			T22	116		T23	20		T27	7
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	369385	1			T23	8		T27	216		T28	36
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1015451	1			T22	144		T27	191		T28	2
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	4110770	1			T22	222		T23	45		T24	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3192000	1			T22	45		T23	73		T25	44
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1019884	1			T22	125		T23	9		T27	190
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1241781	1			T22	184		T23	15		T27	17
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	373755	1			T23	10		T27	266		T28	62
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1013359	1			T22	152		T23	16		T27	143
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	4105077	1			T22	169		T23	30		T24	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3192287	1			T22	58		T23	68		T25	40
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1022410	1			T22	162		T23	6		T27	249
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1245213	1			T22	128		T23	24		T27	8
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	372514	1			T23	12		T27	274		T28	162
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1014048	1			T22	211		T23	28		T27	173
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	4103005	1			T22	238		T23	65		T24	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3195739	1			T22	47		T23	83		T25	30
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1025100	1			T22	156		T27	225		T28	6
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1246016	1			T22	151		T23	1		T27	15
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	372533	1			T23	17		T27	235		T28	107
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1009156	1			T22	136		T23	2		T27	192
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	4096940	1			T22	204		T23	16		T24	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3195041	1			T22	45		T23	110		T25	29
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1021654	1			T22	143		T27	208		T28	12
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1250289	1			T22	178		T23	11		T27	13
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	374924	1			T23	22		T27	276		T28	66
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1012701	1			T22	158		T23	9		T27	223

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal