Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[1]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[2]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[3]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[4]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[5]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[6]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[7]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[8]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[9]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[10]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[11]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[12]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[13]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[14]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[15]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[16]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[17]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[18]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[19]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[20]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[21]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[22]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[23]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[24]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[25]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[26]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[27]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[28]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[29]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[30]	10951549	1			T22	728		T23	168		T24	1
bins_for_gpio_bits[31]	10951549	1			T22	728		T23	168		T24	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

203773887

1

T22

16871

T23

2560

T24

32

auto[1]

146675681

1

T22

6425

T23

2816

T25

1383

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

203765912

1

T22

16865

T23

2558

T24

32

auto[1]

146683656

1

T22

6431

T23

2818

T25

1383

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	6181255	1			T22	497		T23	129		T24	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	182478	1			T22	37		T27	30		T28	3
bins_for_gpio_bits[0]	auto[1]	auto[0]	182732	1			T22	38		T27	30		T28	3
bins_for_gpio_bits[0]	auto[1]	auto[1]	4405084	1			T22	156		T23	39		T25	53
bins_for_gpio_bits[1]	auto[0]	auto[0]	6183723	1			T22	497		T23	103		T24	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	182808	1			T22	44		T27	37		T28	6
bins_for_gpio_bits[1]	auto[1]	auto[0]	183063	1			T22	44		T27	37		T28	6
bins_for_gpio_bits[1]	auto[1]	auto[1]	4401955	1			T22	143		T23	65		T25	47
bins_for_gpio_bits[2]	auto[0]	auto[0]	6176412	1			T22	549		T23	64		T24	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	182855	1			T22	32		T27	18		T28	7
bins_for_gpio_bits[2]	auto[1]	auto[0]	183131	1			T22	32		T27	18		T28	7
bins_for_gpio_bits[2]	auto[1]	auto[1]	4409151	1			T22	115		T23	104		T25	40
bins_for_gpio_bits[3]	auto[0]	auto[0]	6191126	1			T22	476		T23	21		T24	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	182827	1			T22	38		T27	31		T28	2
bins_for_gpio_bits[3]	auto[1]	auto[0]	183101	1			T22	38		T27	31		T28	2
bins_for_gpio_bits[3]	auto[1]	auto[1]	4394495	1			T22	176		T23	147		T25	52
bins_for_gpio_bits[4]	auto[0]	auto[0]	6174024	1			T22	460		T23	71		T24	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	182436	1			T22	40		T27	32		T28	4
bins_for_gpio_bits[4]	auto[1]	auto[0]	182668	1			T22	40		T27	32		T28	4
bins_for_gpio_bits[4]	auto[1]	auto[1]	4412421	1			T22	188		T23	97		T25	32
bins_for_gpio_bits[5]	auto[0]	auto[0]	6179746	1			T22	479		T23	112		T24	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	182252	1			T22	38		T27	27		T28	5
bins_for_gpio_bits[5]	auto[1]	auto[0]	182447	1			T22	38		T23	1		T27	27
bins_for_gpio_bits[5]	auto[1]	auto[1]	4407104	1			T22	173		T23	55		T25	48
bins_for_gpio_bits[6]	auto[0]	auto[0]	6191920	1			T22	512		T23	127		T24	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	182143	1			T22	33		T27	30		T28	2
bins_for_gpio_bits[6]	auto[1]	auto[0]	182431	1			T22	33		T27	30		T28	2
bins_for_gpio_bits[6]	auto[1]	auto[1]	4395055	1			T22	150		T23	41		T25	50
bins_for_gpio_bits[7]	auto[0]	auto[0]	6183685	1			T22	479		T23	113		T24	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	182474	1			T22	36		T27	26		T28	2
bins_for_gpio_bits[7]	auto[1]	auto[0]	182747	1			T22	37		T27	25		T28	2
bins_for_gpio_bits[7]	auto[1]	auto[1]	4402643	1			T22	176		T23	55		T25	47
bins_for_gpio_bits[8]	auto[0]	auto[0]	6185586	1			T22	454		T23	117		T24	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	182452	1			T22	41		T27	28		T28	2
bins_for_gpio_bits[8]	auto[1]	auto[0]	182693	1			T22	41		T27	28		T28	2
bins_for_gpio_bits[8]	auto[1]	auto[1]	4400818	1			T22	192		T23	51		T25	41
bins_for_gpio_bits[9]	auto[0]	auto[0]	6184360	1			T22	509		T23	47		T24	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	183321	1			T22	39		T27	28		T28	6
bins_for_gpio_bits[9]	auto[1]	auto[0]	183569	1			T22	39		T27	28		T28	6
bins_for_gpio_bits[9]	auto[1]	auto[1]	4400299	1			T22	141		T23	121		T25	42
bins_for_gpio_bits[10]	auto[0]	auto[0]	6188624	1			T22	463		T23	47		T24	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	182570	1			T22	41		T27	30		T28	4
bins_for_gpio_bits[10]	auto[1]	auto[0]	182799	1			T22	41		T27	29		T28	4
bins_for_gpio_bits[10]	auto[1]	auto[1]	4397556	1			T22	183		T23	121		T25	30
bins_for_gpio_bits[11]	auto[0]	auto[0]	6179094	1			T22	448		T23	62		T24	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	182567	1			T22	45		T27	29		T28	6
bins_for_gpio_bits[11]	auto[1]	auto[0]	182816	1			T22	45		T27	29		T28	6
bins_for_gpio_bits[11]	auto[1]	auto[1]	4407072	1			T22	190		T23	106		T25	34
bins_for_gpio_bits[12]	auto[0]	auto[0]	6178185	1			T22	499		T23	62		T24	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	182113	1			T22	38		T27	22		T28	4
bins_for_gpio_bits[12]	auto[1]	auto[0]	182365	1			T22	39		T27	22		T28	4
bins_for_gpio_bits[12]	auto[1]	auto[1]	4408886	1			T22	152		T23	106		T25	41
bins_for_gpio_bits[13]	auto[0]	auto[0]	6190974	1			T22	471		T23	43		T24	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	182772	1			T22	39		T27	34		T28	4
bins_for_gpio_bits[13]	auto[1]	auto[0]	183005	1			T22	39		T27	33		T28	4
bins_for_gpio_bits[13]	auto[1]	auto[1]	4394798	1			T22	179		T23	125		T25	51
bins_for_gpio_bits[14]	auto[0]	auto[0]	6174716	1			T22	476		T23	100		T24	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	182432	1			T22	35		T27	31		T28	7
bins_for_gpio_bits[14]	auto[1]	auto[0]	182690	1			T22	35		T27	31		T28	7
bins_for_gpio_bits[14]	auto[1]	auto[1]	4411711	1			T22	182		T23	68		T25	43
bins_for_gpio_bits[15]	auto[0]	auto[0]	6184924	1			T22	489		T23	93		T24	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	182498	1			T22	38		T23	1		T27	32
bins_for_gpio_bits[15]	auto[1]	auto[0]	182736	1			T22	39		T23	1		T27	32
bins_for_gpio_bits[15]	auto[1]	auto[1]	4401391	1			T22	162		T23	73		T25	44
bins_for_gpio_bits[16]	auto[0]	auto[0]	6176295	1			T22	545		T23	74		T24	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	182832	1			T22	35		T23	1		T27	36
bins_for_gpio_bits[16]	auto[1]	auto[0]	183095	1			T22	35		T23	2		T27	36
bins_for_gpio_bits[16]	auto[1]	auto[1]	4409327	1			T22	113		T23	91		T25	55
bins_for_gpio_bits[17]	auto[0]	auto[0]	6197332	1			T22	516		T23	97		T24	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	182438	1			T22	39		T27	28		T28	5
bins_for_gpio_bits[17]	auto[1]	auto[0]	182713	1			T22	39		T27	28		T28	5
bins_for_gpio_bits[17]	auto[1]	auto[1]	4389066	1			T22	134		T23	71		T25	37
bins_for_gpio_bits[18]	auto[0]	auto[0]	6189269	1			T22	488		T23	47		T24	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	182842	1			T22	44		T23	1		T27	30
bins_for_gpio_bits[18]	auto[1]	auto[0]	183093	1			T22	44		T23	1		T27	30
bins_for_gpio_bits[18]	auto[1]	auto[1]	4396345	1			T22	152		T23	119		T25	34
bins_for_gpio_bits[19]	auto[0]	auto[0]	6181174	1			T22	467		T23	45		T24	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	182004	1			T22	42		T27	34		T28	1
bins_for_gpio_bits[19]	auto[1]	auto[0]	182243	1			T22	42		T27	34		T28	1
bins_for_gpio_bits[19]	auto[1]	auto[1]	4406128	1			T22	177		T23	123		T25	51
bins_for_gpio_bits[20]	auto[0]	auto[0]	6193843	1			T22	459		T23	107		T24	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	182640	1			T22	47		T27	36		T28	3
bins_for_gpio_bits[20]	auto[1]	auto[0]	182878	1			T22	47		T27	35		T28	3
bins_for_gpio_bits[20]	auto[1]	auto[1]	4392188	1			T22	175		T23	61		T25	41
bins_for_gpio_bits[21]	auto[0]	auto[0]	6186026	1			T22	483		T23	120		T24	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	182615	1			T22	48		T27	25		T28	5
bins_for_gpio_bits[21]	auto[1]	auto[0]	182834	1			T22	48		T27	25		T28	5
bins_for_gpio_bits[21]	auto[1]	auto[1]	4400074	1			T22	149		T23	48		T25	49
bins_for_gpio_bits[22]	auto[0]	auto[0]	6183398	1			T22	526		T23	123		T24	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	182849	1			T22	38		T27	18		T28	4
bins_for_gpio_bits[22]	auto[1]	auto[0]	183087	1			T22	38		T27	18		T28	4
bins_for_gpio_bits[22]	auto[1]	auto[1]	4402215	1			T22	126		T23	45		T25	42
bins_for_gpio_bits[23]	auto[0]	auto[0]	6193677	1			T22	476		T23	112		T24	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	182402	1			T22	38		T27	30		T28	2
bins_for_gpio_bits[23]	auto[1]	auto[0]	182667	1			T22	38		T27	30		T28	2
bins_for_gpio_bits[23]	auto[1]	auto[1]	4392803	1			T22	176		T23	56		T25	50
bins_for_gpio_bits[24]	auto[0]	auto[0]	6187119	1			T22	494		T23	53		T24	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	182522	1			T22	38		T27	36		T28	3
bins_for_gpio_bits[24]	auto[1]	auto[0]	182746	1			T22	38		T27	35		T28	3
bins_for_gpio_bits[24]	auto[1]	auto[1]	4399162	1			T22	158		T23	115		T25	53
bins_for_gpio_bits[25]	auto[0]	auto[0]	6179646	1			T22	488		T23	107		T24	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	182895	1			T22	41		T27	45		T28	2
bins_for_gpio_bits[25]	auto[1]	auto[0]	183178	1			T22	42		T27	45		T28	2
bins_for_gpio_bits[25]	auto[1]	auto[1]	4405830	1			T22	157		T23	61		T25	49
bins_for_gpio_bits[26]	auto[0]	auto[0]	6181508	1			T22	509		T23	49		T24	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	182723	1			T22	35		T27	23		T28	3
bins_for_gpio_bits[26]	auto[1]	auto[0]	183016	1			T22	35		T27	22		T28	2
bins_for_gpio_bits[26]	auto[1]	auto[1]	4404302	1			T22	149		T23	119		T25	43
bins_for_gpio_bits[27]	auto[0]	auto[0]	6188511	1			T22	503		T23	88		T24	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	182820	1			T22	35		T27	34		T28	7
bins_for_gpio_bits[27]	auto[1]	auto[0]	183053	1			T22	35		T27	33		T28	6
bins_for_gpio_bits[27]	auto[1]	auto[1]	4397165	1			T22	155		T23	80		T25	41
bins_for_gpio_bits[28]	auto[0]	auto[0]	6190037	1			T22	491		T23	68		T24	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	182144	1			T22	40		T23	1		T27	29
bins_for_gpio_bits[28]	auto[1]	auto[0]	182398	1			T22	40		T23	1		T27	29
bins_for_gpio_bits[28]	auto[1]	auto[1]	4396970	1			T22	157		T23	98		T25	44
bins_for_gpio_bits[29]	auto[0]	auto[0]	6189714	1			T22	415		T23	60		T24	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	182767	1			T22	43		T27	29		T28	3
bins_for_gpio_bits[29]	auto[1]	auto[0]	182986	1			T22	44		T27	29		T28	2
bins_for_gpio_bits[29]	auto[1]	auto[1]	4396082	1			T22	226		T23	108		T25	40
bins_for_gpio_bits[30]	auto[0]	auto[0]	6191494	1			T22	509		T23	66		T24	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	182422	1			T22	36		T27	36		T28	2
bins_for_gpio_bits[30]	auto[1]	auto[0]	182627	1			T22	36		T27	36		T28	2
bins_for_gpio_bits[30]	auto[1]	auto[1]	4395006	1			T22	147		T23	102		T25	30
bins_for_gpio_bits[31]	auto[0]	auto[0]	6186353	1			T22	483		T23	27		T24	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	182249	1			T22	42		T27	29		T28	4
bins_for_gpio_bits[31]	auto[1]	auto[0]	182530	1			T22	42		T27	28		T28	4
bins_for_gpio_bits[31]	auto[1]	auto[1]	4400417	1			T22	161		T23	141		T25	29