Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6704676 |
1 |
|
|
T22 |
410 |
|
T23 |
116 |
|
T24 |
1 |
| auto[1] |
4417329 |
1 |
|
|
T23 |
55 |
|
T25 |
120 |
|
T27 |
590 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10556019 |
1 |
|
|
T22 |
410 |
|
T23 |
170 |
|
T24 |
1 |
| auto[1] |
565986 |
1 |
|
|
T23 |
1 |
|
T25 |
3 |
|
T27 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6706562 |
1 |
|
|
T22 |
410 |
|
T23 |
104 |
|
T24 |
1 |
| auto[1] |
4415443 |
1 |
|
|
T23 |
67 |
|
T25 |
77 |
|
T27 |
429 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1933439 |
1 |
|
|
T23 |
44 |
|
T25 |
36 |
|
T27 |
164 |
| auto[1] |
auto[0] |
auto[1] |
285033 |
1 |
|
|
T25 |
3 |
|
T27 |
4 |
|
T110 |
58 |
| auto[1] |
auto[1] |
auto[0] |
1916018 |
1 |
|
|
T23 |
22 |
|
T25 |
38 |
|
T27 |
252 |
| auto[1] |
auto[1] |
auto[1] |
280953 |
1 |
|
|
T23 |
1 |
|
T27 |
9 |
|
T110 |
51 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6714561 |
1 |
|
|
T22 |
410 |
|
T23 |
109 |
|
T24 |
1 |
| auto[1] |
4407444 |
1 |
|
|
T23 |
62 |
|
T25 |
123 |
|
T27 |
543 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10563954 |
1 |
|
|
T22 |
410 |
|
T23 |
170 |
|
T24 |
1 |
| auto[1] |
558051 |
1 |
|
|
T23 |
1 |
|
T25 |
5 |
|
T27 |
19 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6757167 |
1 |
|
|
T22 |
410 |
|
T23 |
111 |
|
T24 |
1 |
| auto[1] |
4364838 |
1 |
|
|
T23 |
60 |
|
T25 |
109 |
|
T27 |
430 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1909528 |
1 |
|
|
T23 |
43 |
|
T25 |
44 |
|
T27 |
153 |
| auto[1] |
auto[0] |
auto[1] |
280961 |
1 |
|
|
T25 |
2 |
|
T27 |
4 |
|
T110 |
41 |
| auto[1] |
auto[1] |
auto[0] |
1897259 |
1 |
|
|
T23 |
16 |
|
T25 |
60 |
|
T27 |
258 |
| auto[1] |
auto[1] |
auto[1] |
277090 |
1 |
|
|
T23 |
1 |
|
T25 |
3 |
|
T27 |
15 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6759650 |
1 |
|
|
T22 |
410 |
|
T23 |
87 |
|
T24 |
1 |
| auto[1] |
4362355 |
1 |
|
|
T23 |
84 |
|
T25 |
104 |
|
T27 |
639 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10555145 |
1 |
|
|
T22 |
410 |
|
T23 |
169 |
|
T24 |
1 |
| auto[1] |
566860 |
1 |
|
|
T23 |
2 |
|
T25 |
4 |
|
T27 |
24 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6706685 |
1 |
|
|
T22 |
410 |
|
T23 |
107 |
|
T24 |
1 |
| auto[1] |
4415320 |
1 |
|
|
T23 |
64 |
|
T25 |
74 |
|
T27 |
476 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1950745 |
1 |
|
|
T23 |
33 |
|
T25 |
33 |
|
T27 |
175 |
| auto[1] |
auto[0] |
auto[1] |
288010 |
1 |
|
|
T23 |
1 |
|
T25 |
3 |
|
T27 |
6 |
| auto[1] |
auto[1] |
auto[0] |
1897715 |
1 |
|
|
T23 |
29 |
|
T25 |
37 |
|
T27 |
277 |
| auto[1] |
auto[1] |
auto[1] |
278850 |
1 |
|
|
T23 |
1 |
|
T25 |
1 |
|
T27 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6735932 |
1 |
|
|
T22 |
410 |
|
T23 |
118 |
|
T24 |
1 |
| auto[1] |
4386073 |
1 |
|
|
T23 |
53 |
|
T25 |
79 |
|
T27 |
740 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10559110 |
1 |
|
|
T22 |
410 |
|
T23 |
168 |
|
T24 |
1 |
| auto[1] |
562895 |
1 |
|
|
T23 |
3 |
|
T25 |
3 |
|
T27 |
16 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6731713 |
1 |
|
|
T22 |
410 |
|
T23 |
112 |
|
T24 |
1 |
| auto[1] |
4390292 |
1 |
|
|
T23 |
59 |
|
T25 |
120 |
|
T27 |
425 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1922936 |
1 |
|
|
T23 |
32 |
|
T25 |
59 |
|
T27 |
98 |
| auto[1] |
auto[0] |
auto[1] |
283204 |
1 |
|
|
T23 |
3 |
|
T25 |
1 |
|
T27 |
4 |
| auto[1] |
auto[1] |
auto[0] |
1904461 |
1 |
|
|
T23 |
24 |
|
T25 |
58 |
|
T27 |
311 |
| auto[1] |
auto[1] |
auto[1] |
279691 |
1 |
|
|
T25 |
2 |
|
T27 |
12 |
|
T110 |
54 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6717703 |
1 |
|
|
T22 |
410 |
|
T23 |
119 |
|
T24 |
1 |
| auto[1] |
4404302 |
1 |
|
|
T23 |
52 |
|
T25 |
120 |
|
T27 |
491 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10557598 |
1 |
|
|
T22 |
410 |
|
T23 |
167 |
|
T24 |
1 |
| auto[1] |
564407 |
1 |
|
|
T23 |
4 |
|
T25 |
6 |
|
T27 |
9 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6716474 |
1 |
|
|
T22 |
410 |
|
T23 |
106 |
|
T24 |
1 |
| auto[1] |
4405531 |
1 |
|
|
T23 |
65 |
|
T25 |
105 |
|
T27 |
394 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1919779 |
1 |
|
|
T23 |
30 |
|
T25 |
45 |
|
T27 |
187 |
| auto[1] |
auto[0] |
auto[1] |
282478 |
1 |
|
|
T23 |
3 |
|
T25 |
2 |
|
T27 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1921345 |
1 |
|
|
T23 |
31 |
|
T25 |
54 |
|
T27 |
198 |
| auto[1] |
auto[1] |
auto[1] |
281929 |
1 |
|
|
T23 |
1 |
|
T25 |
4 |
|
T27 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6713301 |
1 |
|
|
T22 |
410 |
|
T23 |
109 |
|
T24 |
1 |
| auto[1] |
4408704 |
1 |
|
|
T23 |
62 |
|
T25 |
91 |
|
T27 |
652 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10559802 |
1 |
|
|
T22 |
410 |
|
T23 |
168 |
|
T24 |
1 |
| auto[1] |
562203 |
1 |
|
|
T23 |
3 |
|
T25 |
6 |
|
T27 |
32 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6735196 |
1 |
|
|
T22 |
410 |
|
T23 |
125 |
|
T24 |
1 |
| auto[1] |
4386809 |
1 |
|
|
T23 |
46 |
|
T25 |
100 |
|
T27 |
613 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1895070 |
1 |
|
|
T23 |
16 |
|
T25 |
44 |
|
T27 |
189 |
| auto[1] |
auto[0] |
auto[1] |
277581 |
1 |
|
|
T23 |
1 |
|
T25 |
2 |
|
T27 |
11 |
| auto[1] |
auto[1] |
auto[0] |
1929536 |
1 |
|
|
T23 |
27 |
|
T25 |
50 |
|
T27 |
392 |
| auto[1] |
auto[1] |
auto[1] |
284622 |
1 |
|
|
T23 |
2 |
|
T25 |
4 |
|
T27 |
21 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6724188 |
1 |
|
|
T22 |
410 |
|
T23 |
127 |
|
T24 |
1 |
| auto[1] |
4397817 |
1 |
|
|
T23 |
44 |
|
T25 |
129 |
|
T27 |
402 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10561602 |
1 |
|
|
T22 |
410 |
|
T23 |
168 |
|
T24 |
1 |
| auto[1] |
560403 |
1 |
|
|
T23 |
3 |
|
T25 |
4 |
|
T27 |
26 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6750125 |
1 |
|
|
T22 |
410 |
|
T23 |
121 |
|
T24 |
1 |
| auto[1] |
4371880 |
1 |
|
|
T23 |
50 |
|
T25 |
107 |
|
T27 |
502 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1908501 |
1 |
|
|
T23 |
29 |
|
T25 |
31 |
|
T27 |
298 |
| auto[1] |
auto[0] |
auto[1] |
281380 |
1 |
|
|
T23 |
2 |
|
T25 |
1 |
|
T27 |
19 |
| auto[1] |
auto[1] |
auto[0] |
1902976 |
1 |
|
|
T23 |
18 |
|
T25 |
72 |
|
T27 |
178 |
| auto[1] |
auto[1] |
auto[1] |
279023 |
1 |
|
|
T23 |
1 |
|
T25 |
3 |
|
T27 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6725021 |
1 |
|
|
T22 |
410 |
|
T23 |
101 |
|
T24 |
1 |
| auto[1] |
4396984 |
1 |
|
|
T23 |
70 |
|
T25 |
81 |
|
T27 |
642 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10559510 |
1 |
|
|
T22 |
410 |
|
T23 |
170 |
|
T24 |
1 |
| auto[1] |
562495 |
1 |
|
|
T23 |
1 |
|
T25 |
5 |
|
T27 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6742902 |
1 |
|
|
T22 |
410 |
|
T23 |
98 |
|
T24 |
1 |
| auto[1] |
4379103 |
1 |
|
|
T23 |
73 |
|
T25 |
65 |
|
T27 |
554 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1906010 |
1 |
|
|
T23 |
42 |
|
T25 |
38 |
|
T27 |
205 |
| auto[1] |
auto[0] |
auto[1] |
281439 |
1 |
|
|
T23 |
1 |
|
T25 |
2 |
|
T27 |
14 |
| auto[1] |
auto[1] |
auto[0] |
1910598 |
1 |
|
|
T23 |
30 |
|
T25 |
22 |
|
T27 |
322 |
| auto[1] |
auto[1] |
auto[1] |
281056 |
1 |
|
|
T25 |
3 |
|
T27 |
13 |
|
T110 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6728963 |
1 |
|
|
T22 |
410 |
|
T23 |
119 |
|
T24 |
1 |
| auto[1] |
4393042 |
1 |
|
|
T23 |
52 |
|
T25 |
104 |
|
T27 |
565 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10556516 |
1 |
|
|
T22 |
410 |
|
T23 |
169 |
|
T24 |
1 |
| auto[1] |
565489 |
1 |
|
|
T23 |
2 |
|
T25 |
3 |
|
T27 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6708584 |
1 |
|
|
T22 |
410 |
|
T23 |
110 |
|
T24 |
1 |
| auto[1] |
4413421 |
1 |
|
|
T23 |
61 |
|
T25 |
93 |
|
T27 |
483 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1918655 |
1 |
|
|
T23 |
43 |
|
T25 |
49 |
|
T27 |
226 |
| auto[1] |
auto[0] |
auto[1] |
281679 |
1 |
|
|
T23 |
2 |
|
T25 |
3 |
|
T27 |
7 |
| auto[1] |
auto[1] |
auto[0] |
1929277 |
1 |
|
|
T23 |
16 |
|
T25 |
41 |
|
T27 |
236 |
| auto[1] |
auto[1] |
auto[1] |
283810 |
1 |
|
|
T27 |
14 |
|
T110 |
46 |
|
T112 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6731399 |
1 |
|
|
T22 |
410 |
|
T23 |
145 |
|
T24 |
1 |
| auto[1] |
4390606 |
1 |
|
|
T23 |
26 |
|
T25 |
131 |
|
T27 |
582 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10558680 |
1 |
|
|
T22 |
410 |
|
T23 |
170 |
|
T24 |
1 |
| auto[1] |
563325 |
1 |
|
|
T23 |
1 |
|
T25 |
1 |
|
T27 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6726436 |
1 |
|
|
T22 |
410 |
|
T23 |
106 |
|
T24 |
1 |
| auto[1] |
4395569 |
1 |
|
|
T23 |
65 |
|
T25 |
56 |
|
T27 |
484 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1920248 |
1 |
|
|
T23 |
55 |
|
T25 |
24 |
|
T27 |
200 |
| auto[1] |
auto[0] |
auto[1] |
282692 |
1 |
|
|
T27 |
7 |
|
T110 |
48 |
|
T112 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1911996 |
1 |
|
|
T23 |
9 |
|
T25 |
31 |
|
T27 |
269 |
| auto[1] |
auto[1] |
auto[1] |
280633 |
1 |
|
|
T23 |
1 |
|
T25 |
1 |
|
T27 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6704522 |
1 |
|
|
T22 |
410 |
|
T23 |
104 |
|
T24 |
1 |
| auto[1] |
4417483 |
1 |
|
|
T23 |
67 |
|
T25 |
109 |
|
T27 |
571 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10554941 |
1 |
|
|
T22 |
410 |
|
T23 |
169 |
|
T24 |
1 |
| auto[1] |
567064 |
1 |
|
|
T23 |
2 |
|
T25 |
3 |
|
T27 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6698573 |
1 |
|
|
T22 |
410 |
|
T23 |
100 |
|
T24 |
1 |
| auto[1] |
4423432 |
1 |
|
|
T23 |
71 |
|
T25 |
109 |
|
T27 |
548 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1922420 |
1 |
|
|
T23 |
47 |
|
T25 |
46 |
|
T27 |
251 |
| auto[1] |
auto[0] |
auto[1] |
282938 |
1 |
|
|
T23 |
1 |
|
T25 |
2 |
|
T27 |
8 |
| auto[1] |
auto[1] |
auto[0] |
1933948 |
1 |
|
|
T23 |
22 |
|
T25 |
60 |
|
T27 |
279 |
| auto[1] |
auto[1] |
auto[1] |
284126 |
1 |
|
|
T23 |
1 |
|
T25 |
1 |
|
T27 |
10 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6736216 |
1 |
|
|
T22 |
410 |
|
T23 |
115 |
|
T24 |
1 |
| auto[1] |
4385789 |
1 |
|
|
T23 |
56 |
|
T25 |
87 |
|
T27 |
539 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10554348 |
1 |
|
|
T22 |
410 |
|
T23 |
169 |
|
T24 |
1 |
| auto[1] |
567657 |
1 |
|
|
T23 |
2 |
|
T25 |
4 |
|
T27 |
23 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6698068 |
1 |
|
|
T22 |
410 |
|
T23 |
95 |
|
T24 |
1 |
| auto[1] |
4423937 |
1 |
|
|
T23 |
76 |
|
T25 |
112 |
|
T27 |
551 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1938342 |
1 |
|
|
T23 |
34 |
|
T25 |
59 |
|
T27 |
185 |
| auto[1] |
auto[0] |
auto[1] |
285466 |
1 |
|
|
T23 |
2 |
|
T25 |
1 |
|
T27 |
8 |
| auto[1] |
auto[1] |
auto[0] |
1917938 |
1 |
|
|
T23 |
40 |
|
T25 |
49 |
|
T27 |
343 |
| auto[1] |
auto[1] |
auto[1] |
282191 |
1 |
|
|
T25 |
3 |
|
T27 |
15 |
|
T110 |
59 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6710648 |
1 |
|
|
T22 |
410 |
|
T23 |
99 |
|
T24 |
1 |
| auto[1] |
4411357 |
1 |
|
|
T23 |
72 |
|
T25 |
79 |
|
T27 |
508 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10554725 |
1 |
|
|
T22 |
410 |
|
T23 |
169 |
|
T24 |
1 |
| auto[1] |
567280 |
1 |
|
|
T23 |
2 |
|
T25 |
5 |
|
T27 |
15 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6700949 |
1 |
|
|
T22 |
410 |
|
T23 |
99 |
|
T24 |
1 |
| auto[1] |
4421056 |
1 |
|
|
T23 |
72 |
|
T25 |
95 |
|
T27 |
504 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1928144 |
1 |
|
|
T23 |
30 |
|
T25 |
53 |
|
T27 |
289 |
| auto[1] |
auto[0] |
auto[1] |
283161 |
1 |
|
|
T25 |
4 |
|
T27 |
10 |
|
T110 |
27 |
| auto[1] |
auto[1] |
auto[0] |
1925632 |
1 |
|
|
T23 |
40 |
|
T25 |
37 |
|
T27 |
200 |
| auto[1] |
auto[1] |
auto[1] |
284119 |
1 |
|
|
T23 |
2 |
|
T25 |
1 |
|
T27 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6715470 |
1 |
|
|
T22 |
410 |
|
T23 |
110 |
|
T24 |
1 |
| auto[1] |
4406535 |
1 |
|
|
T23 |
61 |
|
T25 |
101 |
|
T27 |
615 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10557905 |
1 |
|
|
T22 |
410 |
|
T23 |
169 |
|
T24 |
1 |
| auto[1] |
564100 |
1 |
|
|
T23 |
2 |
|
T25 |
7 |
|
T27 |
18 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6714899 |
1 |
|
|
T22 |
410 |
|
T23 |
116 |
|
T24 |
1 |
| auto[1] |
4407106 |
1 |
|
|
T23 |
55 |
|
T25 |
107 |
|
T27 |
452 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1921895 |
1 |
|
|
T23 |
23 |
|
T25 |
48 |
|
T27 |
188 |
| auto[1] |
auto[0] |
auto[1] |
281285 |
1 |
|
|
T23 |
1 |
|
T25 |
4 |
|
T27 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1921111 |
1 |
|
|
T23 |
30 |
|
T25 |
52 |
|
T27 |
246 |
| auto[1] |
auto[1] |
auto[1] |
282815 |
1 |
|
|
T23 |
1 |
|
T25 |
3 |
|
T27 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6710949 |
1 |
|
|
T22 |
410 |
|
T23 |
149 |
|
T24 |
1 |
| auto[1] |
4411056 |
1 |
|
|
T23 |
22 |
|
T25 |
100 |
|
T27 |
613 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10555356 |
1 |
|
|
T22 |
410 |
|
T23 |
168 |
|
T24 |
1 |
| auto[1] |
566649 |
1 |
|
|
T23 |
3 |
|
T25 |
2 |
|
T27 |
23 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6713459 |
1 |
|
|
T22 |
410 |
|
T23 |
100 |
|
T24 |
1 |
| auto[1] |
4408546 |
1 |
|
|
T23 |
71 |
|
T25 |
76 |
|
T27 |
671 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1916783 |
1 |
|
|
T23 |
56 |
|
T25 |
50 |
|
T27 |
200 |
| auto[1] |
auto[0] |
auto[1] |
282251 |
1 |
|
|
T23 |
2 |
|
T25 |
1 |
|
T27 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1925114 |
1 |
|
|
T23 |
12 |
|
T25 |
24 |
|
T27 |
448 |
| auto[1] |
auto[1] |
auto[1] |
284398 |
1 |
|
|
T23 |
1 |
|
T25 |
1 |
|
T27 |
18 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6733850 |
1 |
|
|
T22 |
410 |
|
T23 |
96 |
|
T24 |
1 |
| auto[1] |
4388155 |
1 |
|
|
T23 |
75 |
|
T25 |
119 |
|
T27 |
464 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10558825 |
1 |
|
|
T22 |
410 |
|
T23 |
170 |
|
T24 |
1 |
| auto[1] |
563180 |
1 |
|
|
T23 |
1 |
|
T25 |
7 |
|
T27 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6721185 |
1 |
|
|
T22 |
410 |
|
T23 |
127 |
|
T24 |
1 |
| auto[1] |
4400820 |
1 |
|
|
T23 |
44 |
|
T25 |
93 |
|
T27 |
687 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1928308 |
1 |
|
|
T23 |
26 |
|
T25 |
38 |
|
T27 |
341 |
| auto[1] |
auto[0] |
auto[1] |
283428 |
1 |
|
|
T25 |
4 |
|
T27 |
8 |
|
T110 |
63 |
| auto[1] |
auto[1] |
auto[0] |
1909332 |
1 |
|
|
T23 |
17 |
|
T25 |
48 |
|
T27 |
324 |
| auto[1] |
auto[1] |
auto[1] |
279752 |
1 |
|
|
T23 |
1 |
|
T25 |
3 |
|
T27 |
14 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6704537 |
1 |
|
|
T22 |
410 |
|
T23 |
126 |
|
T24 |
1 |
| auto[1] |
4417468 |
1 |
|
|
T23 |
45 |
|
T25 |
148 |
|
T27 |
510 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10559081 |
1 |
|
|
T22 |
410 |
|
T23 |
169 |
|
T24 |
1 |
| auto[1] |
562924 |
1 |
|
|
T23 |
2 |
|
T25 |
5 |
|
T27 |
20 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6730893 |
1 |
|
|
T22 |
410 |
|
T23 |
121 |
|
T24 |
1 |
| auto[1] |
4391112 |
1 |
|
|
T23 |
50 |
|
T25 |
103 |
|
T27 |
628 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1909928 |
1 |
|
|
T23 |
34 |
|
T25 |
32 |
|
T27 |
246 |
| auto[1] |
auto[0] |
auto[1] |
279861 |
1 |
|
|
T23 |
2 |
|
T25 |
2 |
|
T27 |
5 |
| auto[1] |
auto[1] |
auto[0] |
1918260 |
1 |
|
|
T23 |
14 |
|
T25 |
66 |
|
T27 |
362 |
| auto[1] |
auto[1] |
auto[1] |
283063 |
1 |
|
|
T25 |
3 |
|
T27 |
15 |
|
T110 |
27 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6740790 |
1 |
|
|
T22 |
410 |
|
T23 |
117 |
|
T24 |
1 |
| auto[1] |
4381215 |
1 |
|
|
T23 |
54 |
|
T25 |
78 |
|
T27 |
488 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10556334 |
1 |
|
|
T22 |
410 |
|
T23 |
170 |
|
T24 |
1 |
| auto[1] |
565671 |
1 |
|
|
T23 |
1 |
|
T25 |
7 |
|
T27 |
24 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6709252 |
1 |
|
|
T22 |
410 |
|
T23 |
106 |
|
T24 |
1 |
| auto[1] |
4412753 |
1 |
|
|
T23 |
65 |
|
T25 |
124 |
|
T27 |
644 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1934484 |
1 |
|
|
T23 |
45 |
|
T25 |
74 |
|
T27 |
321 |
| auto[1] |
auto[0] |
auto[1] |
285028 |
1 |
|
|
T23 |
1 |
|
T25 |
4 |
|
T27 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1912598 |
1 |
|
|
T23 |
19 |
|
T25 |
43 |
|
T27 |
299 |
| auto[1] |
auto[1] |
auto[1] |
280643 |
1 |
|
|
T25 |
3 |
|
T27 |
15 |
|
T110 |
50 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6746069 |
1 |
|
|
T22 |
410 |
|
T23 |
127 |
|
T24 |
1 |
| auto[1] |
4375936 |
1 |
|
|
T23 |
44 |
|
T25 |
124 |
|
T27 |
516 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10559045 |
1 |
|
|
T22 |
410 |
|
T23 |
168 |
|
T24 |
1 |
| auto[1] |
562960 |
1 |
|
|
T23 |
3 |
|
T25 |
5 |
|
T27 |
38 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6732378 |
1 |
|
|
T22 |
410 |
|
T23 |
85 |
|
T24 |
1 |
| auto[1] |
4389627 |
1 |
|
|
T23 |
86 |
|
T25 |
87 |
|
T27 |
592 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1921428 |
1 |
|
|
T23 |
56 |
|
T25 |
38 |
|
T27 |
272 |
| auto[1] |
auto[0] |
auto[1] |
282573 |
1 |
|
|
T23 |
3 |
|
T25 |
2 |
|
T27 |
20 |
| auto[1] |
auto[1] |
auto[0] |
1905239 |
1 |
|
|
T23 |
27 |
|
T25 |
44 |
|
T27 |
282 |
| auto[1] |
auto[1] |
auto[1] |
280387 |
1 |
|
|
T25 |
3 |
|
T27 |
18 |
|
T110 |
88 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6756752 |
1 |
|
|
T22 |
410 |
|
T23 |
112 |
|
T24 |
1 |
| auto[1] |
4365253 |
1 |
|
|
T23 |
59 |
|
T25 |
91 |
|
T27 |
633 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10563365 |
1 |
|
|
T22 |
410 |
|
T23 |
171 |
|
T24 |
1 |
| auto[1] |
558640 |
1 |
|
|
T25 |
4 |
|
T27 |
16 |
|
T110 |
130 |