Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6730364 |
1 |
|
|
T22 |
410 |
|
T23 |
124 |
|
T24 |
1 |
| auto[1] |
4391641 |
1 |
|
|
T23 |
47 |
|
T25 |
74 |
|
T27 |
388 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10553730 |
1 |
|
|
T22 |
410 |
|
T23 |
170 |
|
T24 |
1 |
| auto[1] |
568275 |
1 |
|
|
T23 |
1 |
|
T25 |
3 |
|
T27 |
24 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6701903 |
1 |
|
|
T22 |
410 |
|
T23 |
102 |
|
T24 |
1 |
| auto[1] |
4420102 |
1 |
|
|
T23 |
69 |
|
T25 |
65 |
|
T27 |
589 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1938089 |
1 |
|
|
T23 |
52 |
|
T25 |
35 |
|
T27 |
392 |
| auto[1] |
auto[0] |
auto[1] |
286503 |
1 |
|
|
T25 |
1 |
|
T27 |
15 |
|
T110 |
61 |
| auto[1] |
auto[1] |
auto[0] |
1913738 |
1 |
|
|
T23 |
16 |
|
T25 |
27 |
|
T27 |
173 |
| auto[1] |
auto[1] |
auto[1] |
281772 |
1 |
|
|
T23 |
1 |
|
T25 |
2 |
|
T27 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |