Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6702829 |
1 |
|
|
T22 |
410 |
|
T23 |
129 |
|
T24 |
1 |
| auto[1] |
4419176 |
1 |
|
|
T23 |
42 |
|
T25 |
74 |
|
T27 |
391 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10558057 |
1 |
|
|
T22 |
410 |
|
T23 |
169 |
|
T24 |
1 |
| auto[1] |
563948 |
1 |
|
|
T23 |
2 |
|
T25 |
7 |
|
T27 |
25 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6721257 |
1 |
|
|
T22 |
410 |
|
T23 |
106 |
|
T24 |
1 |
| auto[1] |
4400748 |
1 |
|
|
T23 |
65 |
|
T25 |
85 |
|
T27 |
591 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1915743 |
1 |
|
|
T23 |
46 |
|
T25 |
51 |
|
T27 |
402 |
| auto[1] |
auto[0] |
auto[1] |
281748 |
1 |
|
|
T23 |
2 |
|
T25 |
3 |
|
T27 |
18 |
| auto[1] |
auto[1] |
auto[0] |
1921057 |
1 |
|
|
T23 |
17 |
|
T25 |
27 |
|
T27 |
164 |
| auto[1] |
auto[1] |
auto[1] |
282200 |
1 |
|
|
T25 |
4 |
|
T27 |
7 |
|
T110 |
67 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |