Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6704676 |
1 |
|
|
T22 |
410 |
|
T23 |
116 |
|
T24 |
1 |
| auto[1] |
4417329 |
1 |
|
|
T23 |
55 |
|
T25 |
120 |
|
T27 |
590 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9269771 |
1 |
|
|
T22 |
410 |
|
T23 |
155 |
|
T24 |
1 |
| auto[1] |
1852234 |
1 |
|
|
T23 |
16 |
|
T25 |
54 |
|
T27 |
314 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6733994 |
1 |
|
|
T22 |
410 |
|
T23 |
110 |
|
T24 |
1 |
| auto[1] |
4388011 |
1 |
|
|
T23 |
61 |
|
T25 |
83 |
|
T27 |
471 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1255597 |
1 |
|
|
T23 |
24 |
|
T25 |
8 |
|
T27 |
45 |
| auto[1] |
auto[0] |
auto[1] |
918225 |
1 |
|
|
T23 |
9 |
|
T25 |
17 |
|
T27 |
137 |
| auto[1] |
auto[1] |
auto[0] |
1280180 |
1 |
|
|
T23 |
21 |
|
T25 |
21 |
|
T27 |
112 |
| auto[1] |
auto[1] |
auto[1] |
934009 |
1 |
|
|
T23 |
7 |
|
T25 |
37 |
|
T27 |
177 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |