Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6714561 |
1 |
|
|
T22 |
410 |
|
T23 |
109 |
|
T24 |
1 |
| auto[1] |
4407444 |
1 |
|
|
T23 |
62 |
|
T25 |
123 |
|
T27 |
543 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9265314 |
1 |
|
|
T22 |
410 |
|
T23 |
158 |
|
T24 |
1 |
| auto[1] |
1856691 |
1 |
|
|
T23 |
13 |
|
T25 |
57 |
|
T27 |
380 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6732014 |
1 |
|
|
T22 |
410 |
|
T23 |
112 |
|
T24 |
1 |
| auto[1] |
4389991 |
1 |
|
|
T23 |
59 |
|
T25 |
103 |
|
T27 |
505 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1257660 |
1 |
|
|
T23 |
27 |
|
T25 |
6 |
|
T27 |
53 |
| auto[1] |
auto[0] |
auto[1] |
921486 |
1 |
|
|
T23 |
5 |
|
T25 |
24 |
|
T27 |
147 |
| auto[1] |
auto[1] |
auto[0] |
1275640 |
1 |
|
|
T23 |
19 |
|
T25 |
40 |
|
T27 |
72 |
| auto[1] |
auto[1] |
auto[1] |
935205 |
1 |
|
|
T23 |
8 |
|
T25 |
33 |
|
T27 |
233 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |