Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6759650 |
1 |
|
|
T22 |
410 |
|
T23 |
87 |
|
T24 |
1 |
| auto[1] |
4362355 |
1 |
|
|
T23 |
84 |
|
T25 |
104 |
|
T27 |
639 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9269535 |
1 |
|
|
T22 |
410 |
|
T23 |
120 |
|
T24 |
1 |
| auto[1] |
1852470 |
1 |
|
|
T23 |
51 |
|
T25 |
45 |
|
T27 |
394 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6748257 |
1 |
|
|
T22 |
410 |
|
T23 |
89 |
|
T24 |
1 |
| auto[1] |
4373748 |
1 |
|
|
T23 |
82 |
|
T25 |
86 |
|
T27 |
485 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1265057 |
1 |
|
|
T23 |
15 |
|
T25 |
21 |
|
T27 |
16 |
| auto[1] |
auto[0] |
auto[1] |
930160 |
1 |
|
|
T23 |
32 |
|
T25 |
21 |
|
T27 |
104 |
| auto[1] |
auto[1] |
auto[0] |
1256221 |
1 |
|
|
T23 |
16 |
|
T25 |
20 |
|
T27 |
75 |
| auto[1] |
auto[1] |
auto[1] |
922310 |
1 |
|
|
T23 |
19 |
|
T25 |
24 |
|
T27 |
290 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |