Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6735932 |
1 |
|
|
T22 |
410 |
|
T23 |
118 |
|
T24 |
1 |
| auto[1] |
4386073 |
1 |
|
|
T23 |
53 |
|
T25 |
79 |
|
T27 |
740 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9267379 |
1 |
|
|
T22 |
410 |
|
T23 |
141 |
|
T24 |
1 |
| auto[1] |
1854626 |
1 |
|
|
T23 |
30 |
|
T25 |
7 |
|
T27 |
386 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6726958 |
1 |
|
|
T22 |
410 |
|
T23 |
126 |
|
T24 |
1 |
| auto[1] |
4395047 |
1 |
|
|
T23 |
45 |
|
T25 |
54 |
|
T27 |
506 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1278552 |
1 |
|
|
T23 |
15 |
|
T25 |
33 |
|
T27 |
32 |
| auto[1] |
auto[0] |
auto[1] |
933296 |
1 |
|
|
T23 |
13 |
|
T25 |
4 |
|
T27 |
88 |
| auto[1] |
auto[1] |
auto[0] |
1261869 |
1 |
|
|
T25 |
14 |
|
T27 |
88 |
|
T110 |
100 |
| auto[1] |
auto[1] |
auto[1] |
921330 |
1 |
|
|
T23 |
17 |
|
T25 |
3 |
|
T27 |
298 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |