Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6717703 |
1 |
|
|
T22 |
410 |
|
T23 |
119 |
|
T24 |
1 |
| auto[1] |
4404302 |
1 |
|
|
T23 |
52 |
|
T25 |
120 |
|
T27 |
491 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9253508 |
1 |
|
|
T22 |
410 |
|
T23 |
129 |
|
T24 |
1 |
| auto[1] |
1868497 |
1 |
|
|
T23 |
42 |
|
T25 |
61 |
|
T27 |
418 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6703238 |
1 |
|
|
T22 |
410 |
|
T23 |
101 |
|
T24 |
1 |
| auto[1] |
4418767 |
1 |
|
|
T23 |
70 |
|
T25 |
97 |
|
T27 |
475 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1278830 |
1 |
|
|
T23 |
19 |
|
T25 |
13 |
|
T27 |
24 |
| auto[1] |
auto[0] |
auto[1] |
939520 |
1 |
|
|
T23 |
21 |
|
T25 |
27 |
|
T27 |
205 |
| auto[1] |
auto[1] |
auto[0] |
1271440 |
1 |
|
|
T23 |
9 |
|
T25 |
23 |
|
T27 |
33 |
| auto[1] |
auto[1] |
auto[1] |
928977 |
1 |
|
|
T23 |
21 |
|
T25 |
34 |
|
T27 |
213 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |