Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6713301 |
1 |
|
|
T22 |
410 |
|
T23 |
109 |
|
T24 |
1 |
| auto[1] |
4408704 |
1 |
|
|
T23 |
62 |
|
T25 |
91 |
|
T27 |
652 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9257376 |
1 |
|
|
T22 |
410 |
|
T23 |
105 |
|
T24 |
1 |
| auto[1] |
1864629 |
1 |
|
|
T23 |
66 |
|
T25 |
22 |
|
T27 |
301 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6703712 |
1 |
|
|
T22 |
410 |
|
T23 |
99 |
|
T24 |
1 |
| auto[1] |
4418293 |
1 |
|
|
T23 |
72 |
|
T25 |
50 |
|
T27 |
388 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1274633 |
1 |
|
|
T23 |
2 |
|
T25 |
19 |
|
T27 |
40 |
| auto[1] |
auto[0] |
auto[1] |
935553 |
1 |
|
|
T23 |
33 |
|
T25 |
5 |
|
T27 |
102 |
| auto[1] |
auto[1] |
auto[0] |
1279031 |
1 |
|
|
T23 |
4 |
|
T25 |
9 |
|
T27 |
47 |
| auto[1] |
auto[1] |
auto[1] |
929076 |
1 |
|
|
T23 |
33 |
|
T25 |
17 |
|
T27 |
199 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |