Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6724188 |
1 |
|
|
T22 |
410 |
|
T23 |
127 |
|
T24 |
1 |
| auto[1] |
4397817 |
1 |
|
|
T23 |
44 |
|
T25 |
129 |
|
T27 |
402 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9272486 |
1 |
|
|
T22 |
410 |
|
T23 |
140 |
|
T24 |
1 |
| auto[1] |
1849519 |
1 |
|
|
T23 |
31 |
|
T25 |
42 |
|
T27 |
431 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6729048 |
1 |
|
|
T22 |
410 |
|
T23 |
85 |
|
T24 |
1 |
| auto[1] |
4392957 |
1 |
|
|
T23 |
86 |
|
T25 |
112 |
|
T27 |
549 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1265011 |
1 |
|
|
T23 |
35 |
|
T25 |
5 |
|
T27 |
75 |
| auto[1] |
auto[0] |
auto[1] |
922543 |
1 |
|
|
T23 |
26 |
|
T25 |
22 |
|
T27 |
258 |
| auto[1] |
auto[1] |
auto[0] |
1278427 |
1 |
|
|
T23 |
20 |
|
T25 |
65 |
|
T27 |
43 |
| auto[1] |
auto[1] |
auto[1] |
926976 |
1 |
|
|
T23 |
5 |
|
T25 |
20 |
|
T27 |
173 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |