Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6725021 |
1 |
|
|
T22 |
410 |
|
T23 |
101 |
|
T24 |
1 |
| auto[1] |
4396984 |
1 |
|
|
T23 |
70 |
|
T25 |
81 |
|
T27 |
642 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9267854 |
1 |
|
|
T22 |
410 |
|
T23 |
118 |
|
T24 |
1 |
| auto[1] |
1854151 |
1 |
|
|
T23 |
53 |
|
T25 |
22 |
|
T27 |
541 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6729965 |
1 |
|
|
T22 |
410 |
|
T23 |
107 |
|
T24 |
1 |
| auto[1] |
4392040 |
1 |
|
|
T23 |
64 |
|
T25 |
60 |
|
T27 |
673 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1270551 |
1 |
|
|
T23 |
6 |
|
T25 |
18 |
|
T27 |
53 |
| auto[1] |
auto[0] |
auto[1] |
930126 |
1 |
|
|
T23 |
17 |
|
T25 |
15 |
|
T27 |
195 |
| auto[1] |
auto[1] |
auto[0] |
1267338 |
1 |
|
|
T23 |
5 |
|
T25 |
20 |
|
T27 |
79 |
| auto[1] |
auto[1] |
auto[1] |
924025 |
1 |
|
|
T23 |
36 |
|
T25 |
7 |
|
T27 |
346 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |