Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6728963 |
1 |
|
|
T22 |
410 |
|
T23 |
119 |
|
T24 |
1 |
| auto[1] |
4393042 |
1 |
|
|
T23 |
52 |
|
T25 |
104 |
|
T27 |
565 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9254435 |
1 |
|
|
T22 |
410 |
|
T23 |
139 |
|
T24 |
1 |
| auto[1] |
1867570 |
1 |
|
|
T23 |
32 |
|
T25 |
31 |
|
T27 |
326 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6680836 |
1 |
|
|
T22 |
410 |
|
T23 |
93 |
|
T24 |
1 |
| auto[1] |
4441169 |
1 |
|
|
T23 |
78 |
|
T25 |
61 |
|
T27 |
449 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1289202 |
1 |
|
|
T23 |
36 |
|
T25 |
14 |
|
T27 |
35 |
| auto[1] |
auto[0] |
auto[1] |
933758 |
1 |
|
|
T23 |
26 |
|
T25 |
12 |
|
T27 |
164 |
| auto[1] |
auto[1] |
auto[0] |
1284397 |
1 |
|
|
T23 |
10 |
|
T25 |
16 |
|
T27 |
88 |
| auto[1] |
auto[1] |
auto[1] |
933812 |
1 |
|
|
T23 |
6 |
|
T25 |
19 |
|
T27 |
162 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |