Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6731399 |
1 |
|
|
T22 |
410 |
|
T23 |
145 |
|
T24 |
1 |
| auto[1] |
4390606 |
1 |
|
|
T23 |
26 |
|
T25 |
131 |
|
T27 |
582 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9261237 |
1 |
|
|
T22 |
410 |
|
T23 |
147 |
|
T24 |
1 |
| auto[1] |
1860768 |
1 |
|
|
T23 |
24 |
|
T25 |
41 |
|
T27 |
397 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6710793 |
1 |
|
|
T22 |
410 |
|
T23 |
109 |
|
T24 |
1 |
| auto[1] |
4411212 |
1 |
|
|
T23 |
62 |
|
T25 |
100 |
|
T27 |
475 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1274600 |
1 |
|
|
T23 |
38 |
|
T25 |
13 |
|
T27 |
35 |
| auto[1] |
auto[0] |
auto[1] |
932398 |
1 |
|
|
T23 |
18 |
|
T25 |
17 |
|
T27 |
165 |
| auto[1] |
auto[1] |
auto[0] |
1275844 |
1 |
|
|
T25 |
46 |
|
T27 |
43 |
|
T110 |
127 |
| auto[1] |
auto[1] |
auto[1] |
928370 |
1 |
|
|
T23 |
6 |
|
T25 |
24 |
|
T27 |
232 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |