Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6704522 |
1 |
|
|
T22 |
410 |
|
T23 |
104 |
|
T24 |
1 |
| auto[1] |
4417483 |
1 |
|
|
T23 |
67 |
|
T25 |
109 |
|
T27 |
571 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9273796 |
1 |
|
|
T22 |
410 |
|
T23 |
133 |
|
T24 |
1 |
| auto[1] |
1848209 |
1 |
|
|
T23 |
38 |
|
T25 |
27 |
|
T27 |
346 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6741114 |
1 |
|
|
T22 |
410 |
|
T23 |
107 |
|
T24 |
1 |
| auto[1] |
4380891 |
1 |
|
|
T23 |
64 |
|
T25 |
101 |
|
T27 |
444 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1260716 |
1 |
|
|
T23 |
19 |
|
T25 |
17 |
|
T27 |
45 |
| auto[1] |
auto[0] |
auto[1] |
922937 |
1 |
|
|
T23 |
27 |
|
T25 |
14 |
|
T27 |
149 |
| auto[1] |
auto[1] |
auto[0] |
1271966 |
1 |
|
|
T23 |
7 |
|
T25 |
57 |
|
T27 |
53 |
| auto[1] |
auto[1] |
auto[1] |
925272 |
1 |
|
|
T23 |
11 |
|
T25 |
13 |
|
T27 |
197 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |