Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6736216 |
1 |
|
|
T22 |
410 |
|
T23 |
115 |
|
T24 |
1 |
| auto[1] |
4385789 |
1 |
|
|
T23 |
56 |
|
T25 |
87 |
|
T27 |
539 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9267492 |
1 |
|
|
T22 |
410 |
|
T23 |
139 |
|
T24 |
1 |
| auto[1] |
1854513 |
1 |
|
|
T23 |
32 |
|
T25 |
37 |
|
T27 |
322 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6727674 |
1 |
|
|
T22 |
410 |
|
T23 |
101 |
|
T24 |
1 |
| auto[1] |
4394331 |
1 |
|
|
T23 |
70 |
|
T25 |
72 |
|
T27 |
419 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1271029 |
1 |
|
|
T23 |
22 |
|
T25 |
22 |
|
T27 |
61 |
| auto[1] |
auto[0] |
auto[1] |
930020 |
1 |
|
|
T23 |
16 |
|
T25 |
18 |
|
T27 |
141 |
| auto[1] |
auto[1] |
auto[0] |
1268789 |
1 |
|
|
T23 |
16 |
|
T25 |
13 |
|
T27 |
36 |
| auto[1] |
auto[1] |
auto[1] |
924493 |
1 |
|
|
T23 |
16 |
|
T25 |
19 |
|
T27 |
181 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |