Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6710648 |
1 |
|
|
T22 |
410 |
|
T23 |
99 |
|
T24 |
1 |
| auto[1] |
4411357 |
1 |
|
|
T23 |
72 |
|
T25 |
79 |
|
T27 |
508 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9262798 |
1 |
|
|
T22 |
410 |
|
T23 |
132 |
|
T24 |
1 |
| auto[1] |
1859207 |
1 |
|
|
T23 |
39 |
|
T25 |
52 |
|
T27 |
405 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6717872 |
1 |
|
|
T22 |
410 |
|
T23 |
119 |
|
T24 |
1 |
| auto[1] |
4404133 |
1 |
|
|
T23 |
52 |
|
T25 |
98 |
|
T27 |
477 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1278410 |
1 |
|
|
T23 |
4 |
|
T25 |
25 |
|
T27 |
50 |
| auto[1] |
auto[0] |
auto[1] |
926936 |
1 |
|
|
T23 |
23 |
|
T25 |
29 |
|
T27 |
175 |
| auto[1] |
auto[1] |
auto[0] |
1266516 |
1 |
|
|
T23 |
9 |
|
T25 |
21 |
|
T27 |
22 |
| auto[1] |
auto[1] |
auto[1] |
932271 |
1 |
|
|
T23 |
16 |
|
T25 |
23 |
|
T27 |
230 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |