Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6715470 |
1 |
|
|
T22 |
410 |
|
T23 |
110 |
|
T24 |
1 |
| auto[1] |
4406535 |
1 |
|
|
T23 |
61 |
|
T25 |
101 |
|
T27 |
615 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9269510 |
1 |
|
|
T22 |
410 |
|
T23 |
158 |
|
T24 |
1 |
| auto[1] |
1852495 |
1 |
|
|
T23 |
13 |
|
T25 |
88 |
|
T27 |
407 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6718296 |
1 |
|
|
T22 |
410 |
|
T23 |
114 |
|
T24 |
1 |
| auto[1] |
4403709 |
1 |
|
|
T23 |
57 |
|
T25 |
121 |
|
T27 |
594 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1281395 |
1 |
|
|
T23 |
24 |
|
T25 |
7 |
|
T27 |
63 |
| auto[1] |
auto[0] |
auto[1] |
929369 |
1 |
|
|
T23 |
6 |
|
T25 |
40 |
|
T27 |
143 |
| auto[1] |
auto[1] |
auto[0] |
1269819 |
1 |
|
|
T23 |
20 |
|
T25 |
26 |
|
T27 |
124 |
| auto[1] |
auto[1] |
auto[1] |
923126 |
1 |
|
|
T23 |
7 |
|
T25 |
48 |
|
T27 |
264 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |