Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6710949 |
1 |
|
|
T22 |
410 |
|
T23 |
149 |
|
T24 |
1 |
| auto[1] |
4411056 |
1 |
|
|
T23 |
22 |
|
T25 |
100 |
|
T27 |
613 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9263065 |
1 |
|
|
T22 |
410 |
|
T23 |
162 |
|
T24 |
1 |
| auto[1] |
1858940 |
1 |
|
|
T23 |
9 |
|
T25 |
50 |
|
T27 |
367 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6707662 |
1 |
|
|
T22 |
410 |
|
T23 |
98 |
|
T24 |
1 |
| auto[1] |
4414343 |
1 |
|
|
T23 |
73 |
|
T25 |
76 |
|
T27 |
481 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1280315 |
1 |
|
|
T23 |
57 |
|
T25 |
11 |
|
T27 |
40 |
| auto[1] |
auto[0] |
auto[1] |
930329 |
1 |
|
|
T23 |
5 |
|
T25 |
16 |
|
T27 |
108 |
| auto[1] |
auto[1] |
auto[0] |
1275088 |
1 |
|
|
T23 |
7 |
|
T25 |
15 |
|
T27 |
74 |
| auto[1] |
auto[1] |
auto[1] |
928611 |
1 |
|
|
T23 |
4 |
|
T25 |
34 |
|
T27 |
259 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |