Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6720216 |
1 |
|
|
T22 |
410 |
|
T23 |
94 |
|
T24 |
1 |
| auto[1] |
4401789 |
1 |
|
|
T23 |
77 |
|
T25 |
135 |
|
T27 |
451 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10555835 |
1 |
|
|
T22 |
410 |
|
T23 |
168 |
|
T24 |
1 |
| auto[1] |
566170 |
1 |
|
|
T23 |
3 |
|
T25 |
4 |
|
T27 |
26 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6711684 |
1 |
|
|
T22 |
410 |
|
T23 |
111 |
|
T24 |
1 |
| auto[1] |
4410321 |
1 |
|
|
T23 |
60 |
|
T25 |
83 |
|
T27 |
533 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1922042 |
1 |
|
|
T23 |
32 |
|
T25 |
39 |
|
T27 |
285 |
| auto[1] |
auto[0] |
auto[1] |
283181 |
1 |
|
|
T23 |
2 |
|
T25 |
3 |
|
T27 |
13 |
| auto[1] |
auto[1] |
auto[0] |
1922109 |
1 |
|
|
T23 |
25 |
|
T25 |
40 |
|
T27 |
222 |
| auto[1] |
auto[1] |
auto[1] |
282989 |
1 |
|
|
T23 |
1 |
|
T25 |
1 |
|
T27 |
13 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |