Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6733850 |
1 |
|
|
T22 |
410 |
|
T23 |
96 |
|
T24 |
1 |
| auto[1] |
4388155 |
1 |
|
|
T23 |
75 |
|
T25 |
119 |
|
T27 |
464 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9260429 |
1 |
|
|
T22 |
410 |
|
T23 |
163 |
|
T24 |
1 |
| auto[1] |
1861576 |
1 |
|
|
T23 |
8 |
|
T25 |
30 |
|
T27 |
415 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6706688 |
1 |
|
|
T22 |
410 |
|
T23 |
126 |
|
T24 |
1 |
| auto[1] |
4415317 |
1 |
|
|
T23 |
45 |
|
T25 |
92 |
|
T27 |
461 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1281243 |
1 |
|
|
T23 |
23 |
|
T25 |
31 |
|
T27 |
12 |
| auto[1] |
auto[0] |
auto[1] |
933509 |
1 |
|
|
T23 |
8 |
|
T25 |
17 |
|
T27 |
260 |
| auto[1] |
auto[1] |
auto[0] |
1272498 |
1 |
|
|
T23 |
14 |
|
T25 |
31 |
|
T27 |
34 |
| auto[1] |
auto[1] |
auto[1] |
928067 |
1 |
|
|
T25 |
13 |
|
T27 |
155 |
|
T110 |
120 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |