Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6704537 |
1 |
|
|
T22 |
410 |
|
T23 |
126 |
|
T24 |
1 |
| auto[1] |
4417468 |
1 |
|
|
T23 |
45 |
|
T25 |
148 |
|
T27 |
510 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9255779 |
1 |
|
|
T22 |
410 |
|
T23 |
139 |
|
T24 |
1 |
| auto[1] |
1866226 |
1 |
|
|
T23 |
32 |
|
T25 |
19 |
|
T27 |
495 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6708434 |
1 |
|
|
T22 |
410 |
|
T23 |
84 |
|
T24 |
1 |
| auto[1] |
4413571 |
1 |
|
|
T23 |
87 |
|
T25 |
86 |
|
T27 |
611 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1268223 |
1 |
|
|
T23 |
38 |
|
T25 |
12 |
|
T27 |
70 |
| auto[1] |
auto[0] |
auto[1] |
931423 |
1 |
|
|
T23 |
24 |
|
T27 |
256 |
|
T110 |
150 |
| auto[1] |
auto[1] |
auto[0] |
1279122 |
1 |
|
|
T23 |
17 |
|
T25 |
55 |
|
T27 |
46 |
| auto[1] |
auto[1] |
auto[1] |
934803 |
1 |
|
|
T23 |
8 |
|
T25 |
19 |
|
T27 |
239 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |