Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6740790 |
1 |
|
|
T22 |
410 |
|
T23 |
117 |
|
T24 |
1 |
| auto[1] |
4381215 |
1 |
|
|
T23 |
54 |
|
T25 |
78 |
|
T27 |
488 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
9274935 |
1 |
|
|
T22 |
410 |
|
T23 |
132 |
|
T24 |
1 |
| auto[1] |
1847070 |
1 |
|
|
T23 |
39 |
|
T25 |
50 |
|
T27 |
375 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6748253 |
1 |
|
|
T22 |
410 |
|
T23 |
112 |
|
T24 |
1 |
| auto[1] |
4373752 |
1 |
|
|
T23 |
59 |
|
T25 |
93 |
|
T27 |
515 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1273109 |
1 |
|
|
T23 |
18 |
|
T25 |
32 |
|
T27 |
74 |
| auto[1] |
auto[0] |
auto[1] |
930483 |
1 |
|
|
T23 |
31 |
|
T25 |
25 |
|
T27 |
220 |
| auto[1] |
auto[1] |
auto[0] |
1253573 |
1 |
|
|
T23 |
2 |
|
T25 |
11 |
|
T27 |
66 |
| auto[1] |
auto[1] |
auto[1] |
916587 |
1 |
|
|
T23 |
8 |
|
T25 |
25 |
|
T27 |
155 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |