Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6727471 |
1 |
|
|
T22 |
410 |
|
T23 |
114 |
|
T24 |
1 |
| auto[1] |
4394534 |
1 |
|
|
T23 |
57 |
|
T25 |
119 |
|
T27 |
516 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10558411 |
1 |
|
|
T22 |
410 |
|
T23 |
170 |
|
T24 |
1 |
| auto[1] |
563594 |
1 |
|
|
T23 |
1 |
|
T25 |
3 |
|
T27 |
17 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6720697 |
1 |
|
|
T22 |
410 |
|
T23 |
114 |
|
T24 |
1 |
| auto[1] |
4401308 |
1 |
|
|
T23 |
57 |
|
T25 |
68 |
|
T27 |
592 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1926015 |
1 |
|
|
T23 |
44 |
|
T25 |
27 |
|
T27 |
289 |
| auto[1] |
auto[0] |
auto[1] |
283260 |
1 |
|
|
T23 |
1 |
|
T25 |
1 |
|
T27 |
9 |
| auto[1] |
auto[1] |
auto[0] |
1911699 |
1 |
|
|
T23 |
12 |
|
T25 |
38 |
|
T27 |
286 |
| auto[1] |
auto[1] |
auto[1] |
280334 |
1 |
|
|
T25 |
2 |
|
T27 |
8 |
|
T110 |
59 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |