Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6728576 |
1 |
|
|
T22 |
410 |
|
T23 |
112 |
|
T24 |
1 |
| auto[1] |
4393429 |
1 |
|
|
T23 |
59 |
|
T25 |
102 |
|
T27 |
633 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10558462 |
1 |
|
|
T22 |
410 |
|
T23 |
169 |
|
T24 |
1 |
| auto[1] |
563543 |
1 |
|
|
T23 |
2 |
|
T25 |
8 |
|
T27 |
13 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6728445 |
1 |
|
|
T22 |
410 |
|
T23 |
118 |
|
T24 |
1 |
| auto[1] |
4393560 |
1 |
|
|
T23 |
53 |
|
T25 |
143 |
|
T27 |
445 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1929830 |
1 |
|
|
T23 |
36 |
|
T25 |
79 |
|
T27 |
139 |
| auto[1] |
auto[0] |
auto[1] |
283953 |
1 |
|
|
T25 |
5 |
|
T27 |
2 |
|
T110 |
59 |
| auto[1] |
auto[1] |
auto[0] |
1900187 |
1 |
|
|
T23 |
15 |
|
T25 |
56 |
|
T27 |
293 |
| auto[1] |
auto[1] |
auto[1] |
279590 |
1 |
|
|
T23 |
2 |
|
T25 |
3 |
|
T27 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |