Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6722512 |
1 |
|
|
T22 |
410 |
|
T23 |
112 |
|
T24 |
1 |
| auto[1] |
4399493 |
1 |
|
|
T23 |
59 |
|
T25 |
53 |
|
T27 |
304 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10553358 |
1 |
|
|
T22 |
410 |
|
T23 |
171 |
|
T24 |
1 |
| auto[1] |
568647 |
1 |
|
|
T25 |
4 |
|
T27 |
23 |
|
T110 |
110 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6698591 |
1 |
|
|
T22 |
410 |
|
T23 |
135 |
|
T24 |
1 |
| auto[1] |
4423414 |
1 |
|
|
T23 |
36 |
|
T25 |
90 |
|
T27 |
517 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1935720 |
1 |
|
|
T23 |
24 |
|
T25 |
67 |
|
T27 |
377 |
| auto[1] |
auto[0] |
auto[1] |
286383 |
1 |
|
|
T25 |
4 |
|
T27 |
18 |
|
T110 |
70 |
| auto[1] |
auto[1] |
auto[0] |
1919047 |
1 |
|
|
T23 |
12 |
|
T25 |
19 |
|
T27 |
117 |
| auto[1] |
auto[1] |
auto[1] |
282264 |
1 |
|
|
T27 |
5 |
|
T110 |
40 |
|
T112 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |