Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6694554 |
1 |
|
|
T22 |
410 |
|
T23 |
126 |
|
T24 |
1 |
| auto[1] |
4427451 |
1 |
|
|
T23 |
45 |
|
T25 |
111 |
|
T27 |
285 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
10553953 |
1 |
|
|
T22 |
410 |
|
T23 |
169 |
|
T24 |
1 |
| auto[1] |
568052 |
1 |
|
|
T23 |
2 |
|
T25 |
5 |
|
T27 |
21 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
6700014 |
1 |
|
|
T22 |
410 |
|
T23 |
90 |
|
T24 |
1 |
| auto[1] |
4421991 |
1 |
|
|
T23 |
81 |
|
T25 |
98 |
|
T27 |
501 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1924984 |
1 |
|
|
T23 |
61 |
|
T25 |
26 |
|
T27 |
373 |
| auto[1] |
auto[0] |
auto[1] |
283435 |
1 |
|
|
T23 |
2 |
|
T25 |
1 |
|
T27 |
17 |
| auto[1] |
auto[1] |
auto[0] |
1928955 |
1 |
|
|
T23 |
18 |
|
T25 |
67 |
|
T27 |
107 |
| auto[1] |
auto[1] |
auto[1] |
284617 |
1 |
|
|
T25 |
4 |
|
T27 |
4 |
|
T110 |
41 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |