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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.63 99.06 99.24 100.00 99.80 99.68 99.99


Total test records in report: 933
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T107 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.663238363 Jul 21 04:52:14 PM PDT 24 Jul 21 04:52:15 PM PDT 24 58960830 ps
T759 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3085208560 Jul 21 04:52:15 PM PDT 24 Jul 21 04:52:16 PM PDT 24 103641193 ps
T760 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3606806523 Jul 21 04:52:23 PM PDT 24 Jul 21 04:52:26 PM PDT 24 33485441 ps
T761 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2163158123 Jul 21 04:52:27 PM PDT 24 Jul 21 04:52:28 PM PDT 24 88595987 ps
T93 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2899974396 Jul 21 04:52:14 PM PDT 24 Jul 21 04:52:15 PM PDT 24 22149415 ps
T94 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3175045746 Jul 21 04:52:09 PM PDT 24 Jul 21 04:52:11 PM PDT 24 17098178 ps
T762 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1264746979 Jul 21 04:52:12 PM PDT 24 Jul 21 04:52:13 PM PDT 24 13973200 ps
T763 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3203595575 Jul 21 04:52:13 PM PDT 24 Jul 21 04:52:15 PM PDT 24 94012557 ps
T764 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2890067673 Jul 21 04:52:22 PM PDT 24 Jul 21 04:52:23 PM PDT 24 73891453 ps
T765 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3722292817 Jul 21 04:52:22 PM PDT 24 Jul 21 04:52:25 PM PDT 24 143990769 ps
T766 /workspace/coverage/cover_reg_top/42.gpio_intr_test.3239801979 Jul 21 04:52:39 PM PDT 24 Jul 21 04:52:40 PM PDT 24 63500995 ps
T767 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3238004918 Jul 21 04:52:09 PM PDT 24 Jul 21 04:52:10 PM PDT 24 10930180 ps
T95 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3630609753 Jul 21 04:52:23 PM PDT 24 Jul 21 04:52:25 PM PDT 24 143079826 ps
T768 /workspace/coverage/cover_reg_top/8.gpio_intr_test.20308058 Jul 21 04:52:11 PM PDT 24 Jul 21 04:52:12 PM PDT 24 17587468 ps
T769 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2649471851 Jul 21 04:52:18 PM PDT 24 Jul 21 04:52:19 PM PDT 24 107265281 ps
T770 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1394821599 Jul 21 04:52:15 PM PDT 24 Jul 21 04:52:16 PM PDT 24 32132641 ps
T771 /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.423728933 Jul 21 04:52:02 PM PDT 24 Jul 21 04:52:03 PM PDT 24 77618669 ps
T772 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2819593520 Jul 21 04:52:10 PM PDT 24 Jul 21 04:52:14 PM PDT 24 699181768 ps
T773 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3692175681 Jul 21 04:52:27 PM PDT 24 Jul 21 04:52:29 PM PDT 24 47459820 ps
T774 /workspace/coverage/cover_reg_top/9.gpio_intr_test.1934975102 Jul 21 04:52:04 PM PDT 24 Jul 21 04:52:05 PM PDT 24 10631798 ps
T775 /workspace/coverage/cover_reg_top/35.gpio_intr_test.533393172 Jul 21 04:52:29 PM PDT 24 Jul 21 04:52:30 PM PDT 24 65914447 ps
T99 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2535691830 Jul 21 04:52:13 PM PDT 24 Jul 21 04:52:14 PM PDT 24 67006778 ps
T776 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2221284164 Jul 21 04:52:19 PM PDT 24 Jul 21 04:52:21 PM PDT 24 390193654 ps
T777 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2159095048 Jul 21 04:52:16 PM PDT 24 Jul 21 04:52:17 PM PDT 24 39980231 ps
T778 /workspace/coverage/cover_reg_top/27.gpio_intr_test.1475689796 Jul 21 04:52:23 PM PDT 24 Jul 21 04:52:24 PM PDT 24 12379285 ps
T779 /workspace/coverage/cover_reg_top/4.gpio_intr_test.593387151 Jul 21 04:52:13 PM PDT 24 Jul 21 04:52:14 PM PDT 24 17888336 ps
T780 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.122804553 Jul 21 04:52:26 PM PDT 24 Jul 21 04:52:28 PM PDT 24 92659311 ps
T781 /workspace/coverage/cover_reg_top/36.gpio_intr_test.4043738518 Jul 21 04:52:27 PM PDT 24 Jul 21 04:52:28 PM PDT 24 38559845 ps
T782 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.630360689 Jul 21 04:52:16 PM PDT 24 Jul 21 04:52:18 PM PDT 24 66622773 ps
T783 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1650881503 Jul 21 04:52:05 PM PDT 24 Jul 21 04:52:06 PM PDT 24 24375740 ps
T784 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2434205764 Jul 21 04:52:22 PM PDT 24 Jul 21 04:52:24 PM PDT 24 43895792 ps
T785 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1404083371 Jul 21 04:52:17 PM PDT 24 Jul 21 04:52:19 PM PDT 24 45214826 ps
T786 /workspace/coverage/cover_reg_top/48.gpio_intr_test.1871017727 Jul 21 04:52:33 PM PDT 24 Jul 21 04:52:34 PM PDT 24 48755449 ps
T787 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.581077311 Jul 21 04:52:22 PM PDT 24 Jul 21 04:52:23 PM PDT 24 43395241 ps
T788 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1406297891 Jul 21 04:52:11 PM PDT 24 Jul 21 04:52:12 PM PDT 24 28353757 ps
T789 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3973429608 Jul 21 04:52:24 PM PDT 24 Jul 21 04:52:27 PM PDT 24 251533946 ps
T790 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.972787666 Jul 21 04:52:04 PM PDT 24 Jul 21 04:52:07 PM PDT 24 131994967 ps
T791 /workspace/coverage/cover_reg_top/24.gpio_intr_test.1962828316 Jul 21 04:52:30 PM PDT 24 Jul 21 04:52:31 PM PDT 24 16966696 ps
T792 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.443014725 Jul 21 04:52:25 PM PDT 24 Jul 21 04:52:26 PM PDT 24 13936647 ps
T793 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3390933790 Jul 21 04:52:04 PM PDT 24 Jul 21 04:52:05 PM PDT 24 90501096 ps
T794 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1439402091 Jul 21 04:52:16 PM PDT 24 Jul 21 04:52:18 PM PDT 24 16717229 ps
T795 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.146567442 Jul 21 04:52:22 PM PDT 24 Jul 21 04:52:24 PM PDT 24 34842650 ps
T796 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.263815177 Jul 21 04:52:13 PM PDT 24 Jul 21 04:52:14 PM PDT 24 109013259 ps
T797 /workspace/coverage/cover_reg_top/18.gpio_intr_test.3612288994 Jul 21 04:52:16 PM PDT 24 Jul 21 04:52:17 PM PDT 24 46558250 ps
T798 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.102186522 Jul 21 04:52:03 PM PDT 24 Jul 21 04:52:04 PM PDT 24 1031303936 ps
T799 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3887855112 Jul 21 04:52:15 PM PDT 24 Jul 21 04:52:16 PM PDT 24 118283178 ps
T800 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2456691242 Jul 21 04:52:05 PM PDT 24 Jul 21 04:52:06 PM PDT 24 37923635 ps
T801 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4225040039 Jul 21 04:52:11 PM PDT 24 Jul 21 04:52:14 PM PDT 24 204582562 ps
T802 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.735763361 Jul 21 04:52:29 PM PDT 24 Jul 21 04:52:30 PM PDT 24 40203956 ps
T803 /workspace/coverage/cover_reg_top/23.gpio_intr_test.263994853 Jul 21 04:52:24 PM PDT 24 Jul 21 04:52:25 PM PDT 24 14091482 ps
T804 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.72432191 Jul 21 04:52:10 PM PDT 24 Jul 21 04:52:11 PM PDT 24 14693291 ps
T805 /workspace/coverage/cover_reg_top/29.gpio_intr_test.2185269479 Jul 21 04:52:25 PM PDT 24 Jul 21 04:52:26 PM PDT 24 59795491 ps
T806 /workspace/coverage/cover_reg_top/2.gpio_intr_test.3181477290 Jul 21 04:52:09 PM PDT 24 Jul 21 04:52:10 PM PDT 24 50629631 ps
T807 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2140830633 Jul 21 04:52:34 PM PDT 24 Jul 21 04:52:35 PM PDT 24 57878186 ps
T808 /workspace/coverage/cover_reg_top/41.gpio_intr_test.1461215460 Jul 21 04:52:39 PM PDT 24 Jul 21 04:52:40 PM PDT 24 59381308 ps
T809 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.4040104970 Jul 21 04:52:20 PM PDT 24 Jul 21 04:52:21 PM PDT 24 119409096 ps
T810 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1755106882 Jul 21 04:52:15 PM PDT 24 Jul 21 04:52:16 PM PDT 24 140941201 ps
T97 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.963180103 Jul 21 04:52:22 PM PDT 24 Jul 21 04:52:23 PM PDT 24 74828706 ps
T811 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.913246285 Jul 21 04:52:11 PM PDT 24 Jul 21 04:52:12 PM PDT 24 71927580 ps
T812 /workspace/coverage/cover_reg_top/30.gpio_intr_test.3784608630 Jul 21 04:52:28 PM PDT 24 Jul 21 04:52:29 PM PDT 24 116925457 ps
T813 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2821353979 Jul 21 04:52:10 PM PDT 24 Jul 21 04:52:12 PM PDT 24 18587617 ps
T814 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2774847498 Jul 21 04:52:13 PM PDT 24 Jul 21 04:52:15 PM PDT 24 16076408 ps
T815 /workspace/coverage/cover_reg_top/17.gpio_intr_test.803012307 Jul 21 04:52:22 PM PDT 24 Jul 21 04:52:24 PM PDT 24 26961381 ps
T100 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3286730225 Jul 21 04:52:13 PM PDT 24 Jul 21 04:52:15 PM PDT 24 37803605 ps
T816 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3816040293 Jul 21 04:52:08 PM PDT 24 Jul 21 04:52:09 PM PDT 24 53325247 ps
T817 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.192042096 Jul 21 04:51:58 PM PDT 24 Jul 21 04:51:59 PM PDT 24 302815448 ps
T818 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.374597053 Jul 21 04:52:16 PM PDT 24 Jul 21 04:52:19 PM PDT 24 358088438 ps
T819 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2071956813 Jul 21 04:52:17 PM PDT 24 Jul 21 04:52:19 PM PDT 24 337223395 ps
T820 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3114256233 Jul 21 04:52:12 PM PDT 24 Jul 21 04:52:14 PM PDT 24 217041647 ps
T821 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1259409340 Jul 21 04:52:08 PM PDT 24 Jul 21 04:52:11 PM PDT 24 52088009 ps
T822 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2577087678 Jul 21 04:52:23 PM PDT 24 Jul 21 04:52:25 PM PDT 24 115185473 ps
T823 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.81293606 Jul 21 04:52:18 PM PDT 24 Jul 21 04:52:20 PM PDT 24 36947299 ps
T824 /workspace/coverage/cover_reg_top/5.gpio_intr_test.3473493170 Jul 21 04:52:10 PM PDT 24 Jul 21 04:52:11 PM PDT 24 10734530 ps
T825 /workspace/coverage/cover_reg_top/39.gpio_intr_test.2626003879 Jul 21 04:52:26 PM PDT 24 Jul 21 04:52:27 PM PDT 24 13160348 ps
T826 /workspace/coverage/cover_reg_top/28.gpio_intr_test.2471455868 Jul 21 04:52:22 PM PDT 24 Jul 21 04:52:23 PM PDT 24 192035043 ps
T827 /workspace/coverage/cover_reg_top/15.gpio_intr_test.3997141829 Jul 21 04:52:18 PM PDT 24 Jul 21 04:52:19 PM PDT 24 14394794 ps
T828 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2854942349 Jul 21 04:52:13 PM PDT 24 Jul 21 04:52:15 PM PDT 24 45829843 ps
T829 /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2630306294 Jul 21 04:52:22 PM PDT 24 Jul 21 04:52:23 PM PDT 24 38072254 ps
T830 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3452963140 Jul 21 04:52:19 PM PDT 24 Jul 21 04:52:20 PM PDT 24 14164116 ps
T98 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3914938879 Jul 21 04:52:04 PM PDT 24 Jul 21 04:52:05 PM PDT 24 17879393 ps
T831 /workspace/coverage/cover_reg_top/45.gpio_intr_test.884190016 Jul 21 04:52:28 PM PDT 24 Jul 21 04:52:30 PM PDT 24 55549888 ps
T832 /workspace/coverage/cover_reg_top/34.gpio_intr_test.3294992599 Jul 21 04:52:38 PM PDT 24 Jul 21 04:52:40 PM PDT 24 45798265 ps
T833 /workspace/coverage/cover_reg_top/11.gpio_intr_test.64658532 Jul 21 04:52:16 PM PDT 24 Jul 21 04:52:17 PM PDT 24 11525320 ps
T834 /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3289143683 Jul 21 04:20:38 PM PDT 24 Jul 21 04:20:39 PM PDT 24 104324139 ps
T835 /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2174443678 Jul 21 04:23:14 PM PDT 24 Jul 21 04:23:17 PM PDT 24 350546323 ps
T836 /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3672998401 Jul 21 04:21:51 PM PDT 24 Jul 21 04:21:53 PM PDT 24 47885192 ps
T837 /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.157924031 Jul 21 04:23:03 PM PDT 24 Jul 21 04:23:05 PM PDT 24 38154273 ps
T838 /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1718531222 Jul 21 04:19:01 PM PDT 24 Jul 21 04:19:03 PM PDT 24 40514058 ps
T839 /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.732878457 Jul 21 04:23:07 PM PDT 24 Jul 21 04:23:09 PM PDT 24 224159250 ps
T840 /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.415270809 Jul 21 04:20:28 PM PDT 24 Jul 21 04:20:29 PM PDT 24 69199971 ps
T841 /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3806925123 Jul 21 04:19:52 PM PDT 24 Jul 21 04:19:53 PM PDT 24 72649903 ps
T842 /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1990872217 Jul 21 04:23:18 PM PDT 24 Jul 21 04:23:20 PM PDT 24 50396909 ps
T843 /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1286844266 Jul 21 04:20:28 PM PDT 24 Jul 21 04:20:30 PM PDT 24 33308084 ps
T844 /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2541813946 Jul 21 04:23:47 PM PDT 24 Jul 21 04:23:48 PM PDT 24 65547879 ps
T845 /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3997616155 Jul 21 04:23:18 PM PDT 24 Jul 21 04:23:19 PM PDT 24 67977907 ps
T846 /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3476172622 Jul 21 04:18:50 PM PDT 24 Jul 21 04:18:52 PM PDT 24 62017054 ps
T847 /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2026373511 Jul 21 04:22:53 PM PDT 24 Jul 21 04:22:56 PM PDT 24 42895691 ps
T848 /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3024509703 Jul 21 04:23:01 PM PDT 24 Jul 21 04:23:03 PM PDT 24 598714049 ps
T849 /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.782342911 Jul 21 04:20:13 PM PDT 24 Jul 21 04:20:14 PM PDT 24 42461066 ps
T850 /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1463029991 Jul 21 04:23:18 PM PDT 24 Jul 21 04:23:20 PM PDT 24 61601363 ps
T851 /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1460061294 Jul 21 04:22:54 PM PDT 24 Jul 21 04:22:57 PM PDT 24 117120681 ps
T852 /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2110420684 Jul 21 04:23:40 PM PDT 24 Jul 21 04:23:42 PM PDT 24 796339493 ps
T853 /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1673708811 Jul 21 04:23:41 PM PDT 24 Jul 21 04:23:43 PM PDT 24 121815919 ps
T854 /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3451537308 Jul 21 04:23:55 PM PDT 24 Jul 21 04:23:57 PM PDT 24 274024704 ps
T855 /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1636976419 Jul 21 04:18:49 PM PDT 24 Jul 21 04:18:51 PM PDT 24 35210408 ps
T856 /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3287495735 Jul 21 04:22:37 PM PDT 24 Jul 21 04:22:39 PM PDT 24 31693966 ps
T857 /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3307921070 Jul 21 04:24:02 PM PDT 24 Jul 21 04:24:03 PM PDT 24 193000721 ps
T858 /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3404624349 Jul 21 04:22:53 PM PDT 24 Jul 21 04:22:56 PM PDT 24 69124140 ps
T859 /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2453376958 Jul 21 04:23:47 PM PDT 24 Jul 21 04:23:48 PM PDT 24 26184367 ps
T860 /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3804523791 Jul 21 04:21:19 PM PDT 24 Jul 21 04:21:21 PM PDT 24 81099256 ps
T861 /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.469397957 Jul 21 04:19:01 PM PDT 24 Jul 21 04:19:03 PM PDT 24 54809383 ps
T862 /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3205527255 Jul 21 04:23:48 PM PDT 24 Jul 21 04:23:50 PM PDT 24 32560548 ps
T863 /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1673375201 Jul 21 04:23:07 PM PDT 24 Jul 21 04:23:09 PM PDT 24 91155311 ps
T864 /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.51906916 Jul 21 04:22:35 PM PDT 24 Jul 21 04:22:37 PM PDT 24 26774697 ps
T865 /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1254642060 Jul 21 04:22:51 PM PDT 24 Jul 21 04:22:52 PM PDT 24 181935857 ps
T866 /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2152602806 Jul 21 04:23:57 PM PDT 24 Jul 21 04:23:59 PM PDT 24 56127174 ps
T867 /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1926595841 Jul 21 04:22:51 PM PDT 24 Jul 21 04:22:52 PM PDT 24 54049908 ps
T868 /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3262715488 Jul 21 04:23:42 PM PDT 24 Jul 21 04:23:44 PM PDT 24 38129180 ps
T869 /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2572469013 Jul 21 04:23:30 PM PDT 24 Jul 21 04:23:32 PM PDT 24 205810699 ps
T870 /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1298009879 Jul 21 04:20:16 PM PDT 24 Jul 21 04:20:18 PM PDT 24 230995937 ps
T871 /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1347518435 Jul 21 04:22:37 PM PDT 24 Jul 21 04:22:39 PM PDT 24 609032040 ps
T872 /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.630944830 Jul 21 04:23:49 PM PDT 24 Jul 21 04:23:51 PM PDT 24 33872028 ps
T873 /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4138837140 Jul 21 04:23:30 PM PDT 24 Jul 21 04:23:32 PM PDT 24 44491110 ps
T874 /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.837337181 Jul 21 04:23:56 PM PDT 24 Jul 21 04:23:58 PM PDT 24 46040525 ps
T875 /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.363097134 Jul 21 04:22:52 PM PDT 24 Jul 21 04:22:56 PM PDT 24 94251084 ps
T876 /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.157828386 Jul 21 04:22:53 PM PDT 24 Jul 21 04:22:56 PM PDT 24 49249704 ps
T877 /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3628870971 Jul 21 04:22:54 PM PDT 24 Jul 21 04:22:57 PM PDT 24 82319721 ps
T878 /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3535141114 Jul 21 04:20:39 PM PDT 24 Jul 21 04:20:40 PM PDT 24 23635826 ps
T879 /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2332167342 Jul 21 04:23:37 PM PDT 24 Jul 21 04:23:38 PM PDT 24 127711903 ps
T880 /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3258323366 Jul 21 04:22:36 PM PDT 24 Jul 21 04:22:38 PM PDT 24 62702586 ps
T881 /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2946559142 Jul 21 04:23:52 PM PDT 24 Jul 21 04:23:53 PM PDT 24 40826547 ps
T882 /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3947332721 Jul 21 04:22:50 PM PDT 24 Jul 21 04:22:52 PM PDT 24 133084713 ps
T883 /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2690107870 Jul 21 04:23:30 PM PDT 24 Jul 21 04:23:31 PM PDT 24 104817375 ps
T884 /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1069626967 Jul 21 04:23:57 PM PDT 24 Jul 21 04:23:58 PM PDT 24 120589300 ps
T885 /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1930178240 Jul 21 04:22:37 PM PDT 24 Jul 21 04:22:40 PM PDT 24 188767635 ps
T886 /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.964187839 Jul 21 04:23:29 PM PDT 24 Jul 21 04:23:31 PM PDT 24 60345343 ps
T887 /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.321653401 Jul 21 04:23:07 PM PDT 24 Jul 21 04:23:09 PM PDT 24 240885694 ps
T888 /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1499762882 Jul 21 04:18:58 PM PDT 24 Jul 21 04:19:00 PM PDT 24 94799930 ps
T889 /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2879695392 Jul 21 04:22:36 PM PDT 24 Jul 21 04:22:38 PM PDT 24 222107296 ps
T890 /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1105243424 Jul 21 04:19:45 PM PDT 24 Jul 21 04:19:47 PM PDT 24 49469452 ps
T891 /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.776382991 Jul 21 04:22:36 PM PDT 24 Jul 21 04:22:38 PM PDT 24 63519215 ps
T892 /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.57511245 Jul 21 04:18:49 PM PDT 24 Jul 21 04:18:51 PM PDT 24 984714019 ps
T893 /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1187776239 Jul 21 04:22:37 PM PDT 24 Jul 21 04:22:39 PM PDT 24 340925578 ps
T894 /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3334148941 Jul 21 04:22:50 PM PDT 24 Jul 21 04:22:52 PM PDT 24 29613827 ps
T895 /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3739165934 Jul 21 04:23:54 PM PDT 24 Jul 21 04:23:55 PM PDT 24 56923044 ps
T896 /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4170196945 Jul 21 04:20:05 PM PDT 24 Jul 21 04:20:06 PM PDT 24 179966075 ps
T897 /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1303551381 Jul 21 04:22:52 PM PDT 24 Jul 21 04:22:55 PM PDT 24 94814528 ps
T898 /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3975453891 Jul 21 04:22:37 PM PDT 24 Jul 21 04:22:39 PM PDT 24 50153180 ps
T899 /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2190668200 Jul 21 04:23:30 PM PDT 24 Jul 21 04:23:31 PM PDT 24 47664567 ps
T900 /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1544265961 Jul 21 04:23:07 PM PDT 24 Jul 21 04:23:08 PM PDT 24 29254944 ps
T901 /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1347563378 Jul 21 04:23:08 PM PDT 24 Jul 21 04:23:10 PM PDT 24 1152932373 ps
T902 /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.387219752 Jul 21 04:23:02 PM PDT 24 Jul 21 04:23:03 PM PDT 24 71644329 ps
T903 /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2002949835 Jul 21 04:21:21 PM PDT 24 Jul 21 04:21:22 PM PDT 24 127475126 ps
T904 /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.231563103 Jul 21 04:22:52 PM PDT 24 Jul 21 04:22:53 PM PDT 24 17337509 ps
T905 /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2744975254 Jul 21 04:23:21 PM PDT 24 Jul 21 04:23:23 PM PDT 24 32600111 ps
T906 /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.552557352 Jul 21 04:23:07 PM PDT 24 Jul 21 04:23:09 PM PDT 24 64049315 ps
T907 /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.769228184 Jul 21 04:20:25 PM PDT 24 Jul 21 04:20:26 PM PDT 24 39127799 ps
T908 /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2068561770 Jul 21 04:21:01 PM PDT 24 Jul 21 04:21:02 PM PDT 24 53315803 ps
T909 /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1900375373 Jul 21 04:23:57 PM PDT 24 Jul 21 04:23:59 PM PDT 24 191502077 ps
T910 /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.847084721 Jul 21 04:22:37 PM PDT 24 Jul 21 04:22:39 PM PDT 24 61678442 ps
T911 /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3537791562 Jul 21 04:22:53 PM PDT 24 Jul 21 04:22:56 PM PDT 24 336614910 ps
T912 /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4121158938 Jul 21 04:23:40 PM PDT 24 Jul 21 04:23:42 PM PDT 24 112627097 ps
T913 /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3242177113 Jul 21 04:22:36 PM PDT 24 Jul 21 04:22:38 PM PDT 24 207732306 ps
T914 /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.690800697 Jul 21 04:20:53 PM PDT 24 Jul 21 04:20:54 PM PDT 24 34330383 ps
T915 /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.173178295 Jul 21 04:23:08 PM PDT 24 Jul 21 04:23:10 PM PDT 24 69147568 ps
T916 /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3233469810 Jul 21 04:22:53 PM PDT 24 Jul 21 04:22:55 PM PDT 24 79953429 ps
T917 /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3504005250 Jul 21 04:19:41 PM PDT 24 Jul 21 04:19:43 PM PDT 24 47908828 ps
T918 /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3150511632 Jul 21 04:21:36 PM PDT 24 Jul 21 04:21:37 PM PDT 24 29476608 ps
T919 /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1388261201 Jul 21 04:23:08 PM PDT 24 Jul 21 04:23:10 PM PDT 24 87133991 ps
T920 /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3080492551 Jul 21 04:22:35 PM PDT 24 Jul 21 04:22:37 PM PDT 24 38945334 ps
T921 /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.390661270 Jul 21 04:22:52 PM PDT 24 Jul 21 04:22:55 PM PDT 24 297974578 ps
T922 /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.568217674 Jul 21 04:20:22 PM PDT 24 Jul 21 04:20:24 PM PDT 24 66283550 ps
T923 /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.535053093 Jul 21 04:23:30 PM PDT 24 Jul 21 04:23:32 PM PDT 24 298678813 ps
T924 /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1797559099 Jul 21 04:20:02 PM PDT 24 Jul 21 04:20:04 PM PDT 24 96492403 ps
T925 /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2358123726 Jul 21 04:23:51 PM PDT 24 Jul 21 04:23:52 PM PDT 24 125286407 ps
T926 /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.4136333599 Jul 21 04:23:56 PM PDT 24 Jul 21 04:23:57 PM PDT 24 65831923 ps
T927 /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3392433557 Jul 21 04:22:51 PM PDT 24 Jul 21 04:22:53 PM PDT 24 68455469 ps
T928 /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1076482786 Jul 21 04:19:48 PM PDT 24 Jul 21 04:19:50 PM PDT 24 87436947 ps
T929 /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1164502432 Jul 21 04:23:08 PM PDT 24 Jul 21 04:23:10 PM PDT 24 52147463 ps
T930 /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1191452696 Jul 21 04:22:53 PM PDT 24 Jul 21 04:22:56 PM PDT 24 54776565 ps
T931 /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.84739206 Jul 21 04:22:38 PM PDT 24 Jul 21 04:22:39 PM PDT 24 29138252 ps
T932 /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.963579094 Jul 21 04:22:53 PM PDT 24 Jul 21 04:22:56 PM PDT 24 186554113 ps
T933 /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.766936990 Jul 21 04:22:50 PM PDT 24 Jul 21 04:22:53 PM PDT 24 159223859 ps

Test location /workspace/coverage/default/44.gpio_full_random.1650485476
Short name T23
Test name
Test status
Simulation time 77226564 ps
CPU time 1.04 seconds
Started Jul 21 06:01:25 PM PDT 24
Finished Jul 21 06:01:27 PM PDT 24
Peak memory 198308 kb
Host smart-e2c983cb-bce2-4f55-a966-64fc6e272a64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650485476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1650485476
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1308755835
Short name T29
Test name
Test status
Simulation time 254780441 ps
CPU time 2.52 seconds
Started Jul 21 06:01:34 PM PDT 24
Finished Jul 21 06:01:37 PM PDT 24
Peak memory 198292 kb
Host smart-dce5b22e-6c84-4eac-a847-59fb60659db2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308755835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1308755835
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.538942107
Short name T32
Test name
Test status
Simulation time 32937611737 ps
CPU time 859.52 seconds
Started Jul 21 06:00:14 PM PDT 24
Finished Jul 21 06:14:35 PM PDT 24
Peak memory 198468 kb
Host smart-54a01d8f-1d15-4c49-a223-fa756848115a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=538942107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.538942107
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2244622721
Short name T35
Test name
Test status
Simulation time 332531986 ps
CPU time 1.06 seconds
Started Jul 21 04:52:22 PM PDT 24
Finished Jul 21 04:52:23 PM PDT 24
Peak memory 198148 kb
Host smart-578ce06e-e222-4df3-a66c-a609d0078446
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244622721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2244622721
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3670166862
Short name T60
Test name
Test status
Simulation time 140072448 ps
CPU time 1.18 seconds
Started Jul 21 06:00:58 PM PDT 24
Finished Jul 21 06:01:01 PM PDT 24
Peak memory 196796 kb
Host smart-ea6acfd1-f872-4ef3-b879-7bac60e3c58d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670166862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3670166862
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2675400299
Short name T91
Test name
Test status
Simulation time 70614335 ps
CPU time 0.67 seconds
Started Jul 21 04:52:09 PM PDT 24
Finished Jul 21 04:52:10 PM PDT 24
Peak memory 194560 kb
Host smart-d71a02a9-b07e-4cab-a02d-c32f826a322d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675400299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2675400299
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.676072215
Short name T2
Test name
Test status
Simulation time 139230853 ps
CPU time 1.82 seconds
Started Jul 21 06:00:20 PM PDT 24
Finished Jul 21 06:00:22 PM PDT 24
Peak memory 198252 kb
Host smart-22fd658b-360d-43dc-8bac-735fa1386573
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676072215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.676072215
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2637510106
Short name T42
Test name
Test status
Simulation time 13545061 ps
CPU time 0.59 seconds
Started Jul 21 06:00:09 PM PDT 24
Finished Jul 21 06:00:10 PM PDT 24
Peak memory 194948 kb
Host smart-3cb09257-abb8-4ffc-8387-f24cd6476d36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637510106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2637510106
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3997286664
Short name T82
Test name
Test status
Simulation time 23925386 ps
CPU time 0.7 seconds
Started Jul 21 04:52:10 PM PDT 24
Finished Jul 21 04:52:12 PM PDT 24
Peak memory 195304 kb
Host smart-43e7c8f6-67df-45cc-8720-9b4f52c089bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997286664 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3997286664
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2507204477
Short name T41
Test name
Test status
Simulation time 68293702 ps
CPU time 0.8 seconds
Started Jul 21 05:59:47 PM PDT 24
Finished Jul 21 05:59:49 PM PDT 24
Peak memory 214280 kb
Host smart-cc63fbf6-84f6-4d22-9159-9a99c6181bcc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507204477 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2507204477
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2221284164
Short name T776
Test name
Test status
Simulation time 390193654 ps
CPU time 1.42 seconds
Started Jul 21 04:52:19 PM PDT 24
Finished Jul 21 04:52:21 PM PDT 24
Peak memory 198112 kb
Host smart-b0e5f4d0-b2be-4f87-9239-e67551af6d96
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221284164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2221284164
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.4004778334
Short name T44
Test name
Test status
Simulation time 72643989 ps
CPU time 1.27 seconds
Started Jul 21 04:52:24 PM PDT 24
Finished Jul 21 04:52:26 PM PDT 24
Peak memory 197340 kb
Host smart-f1c6cd6d-98bd-4e25-b5b0-3c15e259f192
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004778334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.4004778334
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2456691242
Short name T800
Test name
Test status
Simulation time 37923635 ps
CPU time 0.63 seconds
Started Jul 21 04:52:05 PM PDT 24
Finished Jul 21 04:52:06 PM PDT 24
Peak memory 194704 kb
Host smart-14e05288-8e8f-402b-ade5-11284d1c6bfd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456691242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2456691242
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.3390933790
Short name T793
Test name
Test status
Simulation time 90501096 ps
CPU time 1.36 seconds
Started Jul 21 04:52:04 PM PDT 24
Finished Jul 21 04:52:05 PM PDT 24
Peak memory 197232 kb
Host smart-2b4fc6bb-9934-4345-9a75-6cbbc2e70bbf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390933790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.3390933790
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.1650881503
Short name T783
Test name
Test status
Simulation time 24375740 ps
CPU time 0.58 seconds
Started Jul 21 04:52:05 PM PDT 24
Finished Jul 21 04:52:06 PM PDT 24
Peak memory 194420 kb
Host smart-a77adbac-5bfd-441d-88b8-0c4776b3b4a3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650881503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.1650881503
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2581089754
Short name T744
Test name
Test status
Simulation time 42703858 ps
CPU time 0.96 seconds
Started Jul 21 04:51:53 PM PDT 24
Finished Jul 21 04:51:54 PM PDT 24
Peak memory 198000 kb
Host smart-66a7d80d-e00a-4338-a114-cac3384c6a83
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581089754 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2581089754
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.960666130
Short name T85
Test name
Test status
Simulation time 14200360 ps
CPU time 0.59 seconds
Started Jul 21 04:51:58 PM PDT 24
Finished Jul 21 04:51:59 PM PDT 24
Peak memory 194020 kb
Host smart-4b80ac05-5d0d-4b3b-b497-0b22bdf9996d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960666130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.960666130
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1406297891
Short name T788
Test name
Test status
Simulation time 28353757 ps
CPU time 0.59 seconds
Started Jul 21 04:52:11 PM PDT 24
Finished Jul 21 04:52:12 PM PDT 24
Peak memory 193956 kb
Host smart-494a414c-17ff-44a8-9d35-859f1c675062
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406297891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1406297891
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.663238363
Short name T107
Test name
Test status
Simulation time 58960830 ps
CPU time 0.73 seconds
Started Jul 21 04:52:14 PM PDT 24
Finished Jul 21 04:52:15 PM PDT 24
Peak memory 196816 kb
Host smart-32399e41-0b6a-4ca2-991d-d9bd98958c5b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663238363 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 0.gpio_same_csr_outstanding.663238363
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3978988691
Short name T728
Test name
Test status
Simulation time 217301713 ps
CPU time 2.51 seconds
Started Jul 21 04:52:08 PM PDT 24
Finished Jul 21 04:52:11 PM PDT 24
Peak memory 198156 kb
Host smart-a098b491-4763-4776-a801-586034668f16
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978988691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3978988691
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.4040104970
Short name T809
Test name
Test status
Simulation time 119409096 ps
CPU time 0.81 seconds
Started Jul 21 04:52:20 PM PDT 24
Finished Jul 21 04:52:21 PM PDT 24
Peak memory 196140 kb
Host smart-dfb6cc60-14bf-43e3-8419-18e5d6589c92
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040104970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.4040104970
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.3644186721
Short name T109
Test name
Test status
Simulation time 3059604721 ps
CPU time 3.16 seconds
Started Jul 21 04:52:20 PM PDT 24
Finished Jul 21 04:52:24 PM PDT 24
Peak memory 196604 kb
Host smart-fa513c11-c7bd-4741-be27-6d083120c9d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644186721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.3644186721
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.965695160
Short name T750
Test name
Test status
Simulation time 24768270 ps
CPU time 0.62 seconds
Started Jul 21 04:52:09 PM PDT 24
Finished Jul 21 04:52:11 PM PDT 24
Peak memory 194892 kb
Host smart-99f872cb-ac18-406e-83e6-8969d89735cd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965695160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.965695160
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.81293606
Short name T823
Test name
Test status
Simulation time 36947299 ps
CPU time 1.69 seconds
Started Jul 21 04:52:18 PM PDT 24
Finished Jul 21 04:52:20 PM PDT 24
Peak memory 198220 kb
Host smart-59766f5a-bd15-4e50-bb9b-38309801585f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81293606 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.81293606
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.2890847731
Short name T92
Test name
Test status
Simulation time 18384095 ps
CPU time 0.56 seconds
Started Jul 21 04:52:13 PM PDT 24
Finished Jul 21 04:52:14 PM PDT 24
Peak memory 193424 kb
Host smart-1a103180-de91-412e-b4f3-e68eda82f7d0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890847731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.2890847731
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.489720793
Short name T729
Test name
Test status
Simulation time 49784836 ps
CPU time 0.6 seconds
Started Jul 21 04:52:17 PM PDT 24
Finished Jul 21 04:52:18 PM PDT 24
Peak memory 193860 kb
Host smart-03163296-980f-436d-8a58-10649cd47d06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489720793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.489720793
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.3439157515
Short name T103
Test name
Test status
Simulation time 57680406 ps
CPU time 0.92 seconds
Started Jul 21 04:52:07 PM PDT 24
Finished Jul 21 04:52:08 PM PDT 24
Peak memory 197904 kb
Host smart-ffd65199-25e3-403e-9275-049942e4a9f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439157515 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 1.gpio_same_csr_outstanding.3439157515
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1259409340
Short name T821
Test name
Test status
Simulation time 52088009 ps
CPU time 2.55 seconds
Started Jul 21 04:52:08 PM PDT 24
Finished Jul 21 04:52:11 PM PDT 24
Peak memory 198176 kb
Host smart-0d6b6f7a-c971-4ff1-9baf-8707fb547427
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259409340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1259409340
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3467620438
Short name T38
Test name
Test status
Simulation time 71079932 ps
CPU time 1.15 seconds
Started Jul 21 04:52:09 PM PDT 24
Finished Jul 21 04:52:11 PM PDT 24
Peak memory 197784 kb
Host smart-17fc0091-9f0d-4e94-b1e3-39c241104e58
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467620438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3467620438
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.1537211234
Short name T736
Test name
Test status
Simulation time 66693011 ps
CPU time 0.67 seconds
Started Jul 21 04:52:13 PM PDT 24
Finished Jul 21 04:52:15 PM PDT 24
Peak memory 196956 kb
Host smart-2e03c523-984e-4228-8f0e-e369c9b0f87e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537211234 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.1537211234
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2865052488
Short name T89
Test name
Test status
Simulation time 20841966 ps
CPU time 0.59 seconds
Started Jul 21 04:52:16 PM PDT 24
Finished Jul 21 04:52:17 PM PDT 24
Peak memory 194064 kb
Host smart-2e84f3bf-4d3b-4ac3-94d8-ae058041b4f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865052488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2865052488
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1264746979
Short name T762
Test name
Test status
Simulation time 13973200 ps
CPU time 0.64 seconds
Started Jul 21 04:52:12 PM PDT 24
Finished Jul 21 04:52:13 PM PDT 24
Peak memory 193880 kb
Host smart-e719d4fc-2552-452e-bede-4851dea9f35f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264746979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1264746979
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.4225040039
Short name T801
Test name
Test status
Simulation time 204582562 ps
CPU time 1.92 seconds
Started Jul 21 04:52:11 PM PDT 24
Finished Jul 21 04:52:14 PM PDT 24
Peak memory 198140 kb
Host smart-c78c32a3-d7c7-495a-8198-5ce253d05f11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225040039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.4225040039
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.2769286618
Short name T753
Test name
Test status
Simulation time 89163037 ps
CPU time 1 seconds
Started Jul 21 04:52:11 PM PDT 24
Finished Jul 21 04:52:13 PM PDT 24
Peak memory 197972 kb
Host smart-34f6e5de-63d9-4e5a-9148-fdd5b03407c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769286618 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.2769286618
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3648023395
Short name T730
Test name
Test status
Simulation time 47468549 ps
CPU time 0.59 seconds
Started Jul 21 04:52:10 PM PDT 24
Finished Jul 21 04:52:11 PM PDT 24
Peak memory 195300 kb
Host smart-eda23df3-4d39-4366-ae4b-df0355ccee62
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648023395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3648023395
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.64658532
Short name T833
Test name
Test status
Simulation time 11525320 ps
CPU time 0.56 seconds
Started Jul 21 04:52:16 PM PDT 24
Finished Jul 21 04:52:17 PM PDT 24
Peak memory 193752 kb
Host smart-0e5d6340-7338-4547-877b-d9d20fa26269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64658532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.64658532
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.2140830633
Short name T807
Test name
Test status
Simulation time 57878186 ps
CPU time 0.59 seconds
Started Jul 21 04:52:34 PM PDT 24
Finished Jul 21 04:52:35 PM PDT 24
Peak memory 194348 kb
Host smart-24a453d7-e489-4230-a63a-1bf87ab8532c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140830633 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.2140830633
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.3203595575
Short name T763
Test name
Test status
Simulation time 94012557 ps
CPU time 1.27 seconds
Started Jul 21 04:52:13 PM PDT 24
Finished Jul 21 04:52:15 PM PDT 24
Peak memory 198196 kb
Host smart-14ddbc4d-383e-41a2-b894-e31c8e05694c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203595575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.3203595575
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.3833002382
Short name T748
Test name
Test status
Simulation time 165771669 ps
CPU time 0.89 seconds
Started Jul 21 04:52:12 PM PDT 24
Finished Jul 21 04:52:14 PM PDT 24
Peak memory 197092 kb
Host smart-108f4b72-e327-4848-9d4f-26c3a4a56a9b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833002382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.3833002382
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.536432539
Short name T725
Test name
Test status
Simulation time 133742191 ps
CPU time 0.67 seconds
Started Jul 21 04:52:12 PM PDT 24
Finished Jul 21 04:52:14 PM PDT 24
Peak memory 196712 kb
Host smart-bdb9c991-516f-4afa-bee2-98ac726c545f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536432539 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.536432539
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.581077311
Short name T787
Test name
Test status
Simulation time 43395241 ps
CPU time 0.62 seconds
Started Jul 21 04:52:22 PM PDT 24
Finished Jul 21 04:52:23 PM PDT 24
Peak memory 194808 kb
Host smart-48dc643f-cd91-4518-8c52-56d24762f0b7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581077311 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.581077311
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1331825400
Short name T735
Test name
Test status
Simulation time 30951338 ps
CPU time 0.61 seconds
Started Jul 21 04:52:23 PM PDT 24
Finished Jul 21 04:52:24 PM PDT 24
Peak memory 194516 kb
Host smart-b60f3467-5cb5-4137-91dd-e1d0b3abfa17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331825400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1331825400
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2927972946
Short name T106
Test name
Test status
Simulation time 130626125 ps
CPU time 0.86 seconds
Started Jul 21 04:52:23 PM PDT 24
Finished Jul 21 04:52:25 PM PDT 24
Peak memory 196364 kb
Host smart-161a8e91-35c3-4481-8096-3c7cdd8b2e6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927972946 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2927972946
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2143784394
Short name T756
Test name
Test status
Simulation time 104800847 ps
CPU time 1.57 seconds
Started Jul 21 04:52:15 PM PDT 24
Finished Jul 21 04:52:17 PM PDT 24
Peak memory 198208 kb
Host smart-de63d824-54a7-4294-8a86-d609dd5f18d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143784394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2143784394
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.1195193392
Short name T731
Test name
Test status
Simulation time 493905953 ps
CPU time 1.46 seconds
Started Jul 21 04:52:10 PM PDT 24
Finished Jul 21 04:52:13 PM PDT 24
Peak memory 198128 kb
Host smart-c08d7088-e440-4204-afda-cd891b768eb3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195193392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.1195193392
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.443014725
Short name T792
Test name
Test status
Simulation time 13936647 ps
CPU time 0.7 seconds
Started Jul 21 04:52:25 PM PDT 24
Finished Jul 21 04:52:26 PM PDT 24
Peak memory 197860 kb
Host smart-931c0776-cccf-4d64-b7b2-f99b94e0ada9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443014725 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.443014725
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3452963140
Short name T830
Test name
Test status
Simulation time 14164116 ps
CPU time 0.61 seconds
Started Jul 21 04:52:19 PM PDT 24
Finished Jul 21 04:52:20 PM PDT 24
Peak memory 194616 kb
Host smart-98471175-976c-4d5b-aa4f-3667832cce5d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452963140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3452963140
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.3767062375
Short name T734
Test name
Test status
Simulation time 81943675 ps
CPU time 0.59 seconds
Started Jul 21 04:52:20 PM PDT 24
Finished Jul 21 04:52:21 PM PDT 24
Peak memory 193924 kb
Host smart-ce1a8800-db19-4955-9401-27d6d554a89e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767062375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.3767062375
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.1440251362
Short name T105
Test name
Test status
Simulation time 185133984 ps
CPU time 0.83 seconds
Started Jul 21 04:52:13 PM PDT 24
Finished Jul 21 04:52:15 PM PDT 24
Peak memory 196488 kb
Host smart-72786795-f658-42bc-9a27-85c5c114645e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440251362 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.1440251362
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1654683085
Short name T742
Test name
Test status
Simulation time 262407416 ps
CPU time 3.08 seconds
Started Jul 21 04:52:21 PM PDT 24
Finished Jul 21 04:52:25 PM PDT 24
Peak memory 198480 kb
Host smart-53a4746a-0a91-4bd4-9295-7fc6c1b69ff8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654683085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1654683085
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1872315576
Short name T740
Test name
Test status
Simulation time 121671155 ps
CPU time 0.83 seconds
Started Jul 21 04:52:10 PM PDT 24
Finished Jul 21 04:52:12 PM PDT 24
Peak memory 197956 kb
Host smart-a48f397d-9f06-4c5f-8ef0-9de83b4af880
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872315576 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1872315576
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.2535691830
Short name T99
Test name
Test status
Simulation time 67006778 ps
CPU time 0.6 seconds
Started Jul 21 04:52:13 PM PDT 24
Finished Jul 21 04:52:14 PM PDT 24
Peak memory 195156 kb
Host smart-3750ec84-47b6-4ffe-aff6-29b0b77993c7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535691830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.2535691830
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2869696449
Short name T727
Test name
Test status
Simulation time 31594240 ps
CPU time 0.6 seconds
Started Jul 21 04:52:25 PM PDT 24
Finished Jul 21 04:52:27 PM PDT 24
Peak memory 193864 kb
Host smart-9d402916-df87-4f84-922a-53199b527b7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869696449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2869696449
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.2691873086
Short name T101
Test name
Test status
Simulation time 105271869 ps
CPU time 0.77 seconds
Started Jul 21 04:52:19 PM PDT 24
Finished Jul 21 04:52:20 PM PDT 24
Peak memory 196088 kb
Host smart-cf81d71d-6e37-4f6d-9f31-297061e8d672
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691873086 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.2691873086
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.1755106882
Short name T810
Test name
Test status
Simulation time 140941201 ps
CPU time 0.92 seconds
Started Jul 21 04:52:15 PM PDT 24
Finished Jul 21 04:52:16 PM PDT 24
Peak memory 197904 kb
Host smart-b598b410-3edb-4755-8f49-973806222b17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755106882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.1755106882
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.3114256233
Short name T820
Test name
Test status
Simulation time 217041647 ps
CPU time 1.36 seconds
Started Jul 21 04:52:12 PM PDT 24
Finished Jul 21 04:52:14 PM PDT 24
Peak memory 198164 kb
Host smart-cb28c872-67f8-4352-979f-e33e0d0dce05
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114256233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.3114256233
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.1860558379
Short name T746
Test name
Test status
Simulation time 41731177 ps
CPU time 1.86 seconds
Started Jul 21 04:52:34 PM PDT 24
Finished Jul 21 04:52:36 PM PDT 24
Peak memory 198220 kb
Host smart-d004ef1f-c0ca-4a18-92f9-a9ba828f8df8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860558379 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.1860558379
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.912577571
Short name T83
Test name
Test status
Simulation time 57912492 ps
CPU time 0.6 seconds
Started Jul 21 04:52:18 PM PDT 24
Finished Jul 21 04:52:19 PM PDT 24
Peak memory 194652 kb
Host smart-f3809294-2b71-4689-aad6-f40d32c414a8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912577571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.912577571
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3997141829
Short name T827
Test name
Test status
Simulation time 14394794 ps
CPU time 0.6 seconds
Started Jul 21 04:52:18 PM PDT 24
Finished Jul 21 04:52:19 PM PDT 24
Peak memory 193752 kb
Host smart-15dffec0-bf78-48fe-ac7f-8f6a8fb7c07d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997141829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3997141829
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2434205764
Short name T784
Test name
Test status
Simulation time 43895792 ps
CPU time 0.95 seconds
Started Jul 21 04:52:22 PM PDT 24
Finished Jul 21 04:52:24 PM PDT 24
Peak memory 197500 kb
Host smart-cbe906c8-42e0-41f6-be49-740bc62533e0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434205764 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2434205764
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.630360689
Short name T782
Test name
Test status
Simulation time 66622773 ps
CPU time 1.37 seconds
Started Jul 21 04:52:16 PM PDT 24
Finished Jul 21 04:52:18 PM PDT 24
Peak memory 198172 kb
Host smart-e6c06ed3-1b82-479f-9afc-a7d26c932741
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630360689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.630360689
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3085208560
Short name T759
Test name
Test status
Simulation time 103641193 ps
CPU time 1.22 seconds
Started Jul 21 04:52:15 PM PDT 24
Finished Jul 21 04:52:16 PM PDT 24
Peak memory 198144 kb
Host smart-bef1f86c-44cc-4fdd-9b3b-6ac105769ba8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085208560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3085208560
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2163158123
Short name T761
Test name
Test status
Simulation time 88595987 ps
CPU time 0.77 seconds
Started Jul 21 04:52:27 PM PDT 24
Finished Jul 21 04:52:28 PM PDT 24
Peak memory 198028 kb
Host smart-caae3c71-4b35-4566-9892-0747947cd69f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163158123 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2163158123
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.963180103
Short name T97
Test name
Test status
Simulation time 74828706 ps
CPU time 0.63 seconds
Started Jul 21 04:52:22 PM PDT 24
Finished Jul 21 04:52:23 PM PDT 24
Peak memory 195564 kb
Host smart-27204def-8578-4735-b1e3-251bef646333
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963180103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio
_csr_rw.963180103
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1493431366
Short name T709
Test name
Test status
Simulation time 195025176 ps
CPU time 0.6 seconds
Started Jul 21 04:52:19 PM PDT 24
Finished Jul 21 04:52:20 PM PDT 24
Peak memory 194196 kb
Host smart-eb1a2941-bfac-4493-8a49-814118f2de47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493431366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1493431366
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.1439402091
Short name T794
Test name
Test status
Simulation time 16717229 ps
CPU time 0.75 seconds
Started Jul 21 04:52:16 PM PDT 24
Finished Jul 21 04:52:18 PM PDT 24
Peak memory 196212 kb
Host smart-64cc3110-2348-4a7e-bfcd-f23e088f6cb9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439402091 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.1439402091
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3722292817
Short name T765
Test name
Test status
Simulation time 143990769 ps
CPU time 1.98 seconds
Started Jul 21 04:52:22 PM PDT 24
Finished Jul 21 04:52:25 PM PDT 24
Peak memory 198144 kb
Host smart-b78950ae-ee3d-4e50-b5ff-e334b587db54
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722292817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3722292817
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.1961084976
Short name T749
Test name
Test status
Simulation time 121306699 ps
CPU time 0.87 seconds
Started Jul 21 04:52:26 PM PDT 24
Finished Jul 21 04:52:27 PM PDT 24
Peak memory 196976 kb
Host smart-667e3199-5b89-498c-b5a3-81b19eb963f8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961084976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.1961084976
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.146567442
Short name T795
Test name
Test status
Simulation time 34842650 ps
CPU time 0.77 seconds
Started Jul 21 04:52:22 PM PDT 24
Finished Jul 21 04:52:24 PM PDT 24
Peak memory 197724 kb
Host smart-2076f8c4-bc2b-4299-8880-f670fcdb5e24
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146567442 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.146567442
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.122804553
Short name T780
Test name
Test status
Simulation time 92659311 ps
CPU time 0.63 seconds
Started Jul 21 04:52:26 PM PDT 24
Finished Jul 21 04:52:28 PM PDT 24
Peak memory 195308 kb
Host smart-3d135941-3e61-48f5-a5e8-ed7315f28054
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122804553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.122804553
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.803012307
Short name T815
Test name
Test status
Simulation time 26961381 ps
CPU time 0.61 seconds
Started Jul 21 04:52:22 PM PDT 24
Finished Jul 21 04:52:24 PM PDT 24
Peak memory 193888 kb
Host smart-3206fcaa-3d68-4a94-b387-ab6208657709
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803012307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.803012307
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.497046846
Short name T87
Test name
Test status
Simulation time 18212556 ps
CPU time 0.77 seconds
Started Jul 21 04:52:26 PM PDT 24
Finished Jul 21 04:52:28 PM PDT 24
Peak memory 196160 kb
Host smart-3d1ead1b-ec6c-439f-87ed-94f6a1cd793f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497046846 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.497046846
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.3973429608
Short name T789
Test name
Test status
Simulation time 251533946 ps
CPU time 2.51 seconds
Started Jul 21 04:52:24 PM PDT 24
Finished Jul 21 04:52:27 PM PDT 24
Peak memory 198204 kb
Host smart-d450e33a-ea1a-4d88-9752-8b3c02c2acd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973429608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.3973429608
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.560626573
Short name T37
Test name
Test status
Simulation time 154819182 ps
CPU time 0.84 seconds
Started Jul 21 04:52:23 PM PDT 24
Finished Jul 21 04:52:25 PM PDT 24
Peak memory 197316 kb
Host smart-65c87674-3de4-455b-b618-7fee0c778538
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560626573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.560626573
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2099641177
Short name T713
Test name
Test status
Simulation time 21298118 ps
CPU time 0.98 seconds
Started Jul 21 04:52:31 PM PDT 24
Finished Jul 21 04:52:33 PM PDT 24
Peak memory 198048 kb
Host smart-c6e5608f-c362-4714-b6d9-7e08feb2ceb8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099641177 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2099641177
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.2834659359
Short name T751
Test name
Test status
Simulation time 14994778 ps
CPU time 0.62 seconds
Started Jul 21 04:52:16 PM PDT 24
Finished Jul 21 04:52:18 PM PDT 24
Peak memory 194524 kb
Host smart-b8aa3621-b6ab-4a2a-8458-9702e5dd797d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834659359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.2834659359
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.3612288994
Short name T797
Test name
Test status
Simulation time 46558250 ps
CPU time 0.62 seconds
Started Jul 21 04:52:16 PM PDT 24
Finished Jul 21 04:52:17 PM PDT 24
Peak memory 193780 kb
Host smart-cb91e285-5092-4cda-a757-899640522d49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612288994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.3612288994
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3887855112
Short name T799
Test name
Test status
Simulation time 118283178 ps
CPU time 0.85 seconds
Started Jul 21 04:52:15 PM PDT 24
Finished Jul 21 04:52:16 PM PDT 24
Peak memory 197160 kb
Host smart-873988ea-9e5b-4bc4-9301-a1a7b9a85fb3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887855112 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3887855112
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.2071956813
Short name T819
Test name
Test status
Simulation time 337223395 ps
CPU time 2.07 seconds
Started Jul 21 04:52:17 PM PDT 24
Finished Jul 21 04:52:19 PM PDT 24
Peak memory 198176 kb
Host smart-b90bbccb-a97c-45b3-862e-06708107f9f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071956813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.2071956813
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3290335079
Short name T49
Test name
Test status
Simulation time 119746935 ps
CPU time 1.41 seconds
Started Jul 21 04:52:23 PM PDT 24
Finished Jul 21 04:52:25 PM PDT 24
Peak memory 198216 kb
Host smart-aefa8dfe-bae3-40d2-9464-728426a1764a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290335079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3290335079
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.2580394347
Short name T716
Test name
Test status
Simulation time 36850209 ps
CPU time 0.89 seconds
Started Jul 21 04:52:16 PM PDT 24
Finished Jul 21 04:52:17 PM PDT 24
Peak memory 198024 kb
Host smart-82820a36-07d9-487c-9f84-0568c353557e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580394347 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.2580394347
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.3286730225
Short name T100
Test name
Test status
Simulation time 37803605 ps
CPU time 0.59 seconds
Started Jul 21 04:52:13 PM PDT 24
Finished Jul 21 04:52:15 PM PDT 24
Peak memory 195320 kb
Host smart-57839353-27b9-4bd6-992b-2c736aa9c220
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286730225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.3286730225
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.301620814
Short name T715
Test name
Test status
Simulation time 100260352 ps
CPU time 0.58 seconds
Started Jul 21 04:52:25 PM PDT 24
Finished Jul 21 04:52:27 PM PDT 24
Peak memory 194504 kb
Host smart-00941a05-962e-4a36-b122-8408505d2498
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301620814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.301620814
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.735763361
Short name T802
Test name
Test status
Simulation time 40203956 ps
CPU time 0.72 seconds
Started Jul 21 04:52:29 PM PDT 24
Finished Jul 21 04:52:30 PM PDT 24
Peak memory 195748 kb
Host smart-433612fa-df63-4c05-9845-d2b3d2cd6a2e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735763361 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 19.gpio_same_csr_outstanding.735763361
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1404083371
Short name T785
Test name
Test status
Simulation time 45214826 ps
CPU time 1.47 seconds
Started Jul 21 04:52:17 PM PDT 24
Finished Jul 21 04:52:19 PM PDT 24
Peak memory 198220 kb
Host smart-3564bc92-6767-44be-8ac6-4f66f61efdcd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404083371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1404083371
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3445803921
Short name T47
Test name
Test status
Simulation time 65623573 ps
CPU time 0.88 seconds
Started Jul 21 04:52:17 PM PDT 24
Finished Jul 21 04:52:18 PM PDT 24
Peak memory 197172 kb
Host smart-bd3bc2da-88eb-490c-9a6d-eb95d5cc09a5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445803921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3445803921
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.2571864747
Short name T108
Test name
Test status
Simulation time 119378867 ps
CPU time 2.24 seconds
Started Jul 21 04:52:15 PM PDT 24
Finished Jul 21 04:52:18 PM PDT 24
Peak memory 198124 kb
Host smart-6ca6ec70-262d-44b8-98e6-07481e9f38d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571864747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.2571864747
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.3356793859
Short name T81
Test name
Test status
Simulation time 25753951 ps
CPU time 0.64 seconds
Started Jul 21 04:52:10 PM PDT 24
Finished Jul 21 04:52:11 PM PDT 24
Peak memory 194720 kb
Host smart-e8ea17e6-adee-4a2a-8a69-d01b3a228ac8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356793859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.3356793859
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2577087678
Short name T822
Test name
Test status
Simulation time 115185473 ps
CPU time 0.87 seconds
Started Jul 21 04:52:23 PM PDT 24
Finished Jul 21 04:52:25 PM PDT 24
Peak memory 197980 kb
Host smart-e1ccd3d0-dd4b-404e-b3ea-c9768982c268
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577087678 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2577087678
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.46360007
Short name T88
Test name
Test status
Simulation time 43836274 ps
CPU time 0.61 seconds
Started Jul 21 04:52:18 PM PDT 24
Finished Jul 21 04:52:19 PM PDT 24
Peak memory 194784 kb
Host smart-24785d66-51a0-4c41-a14f-7e9ba734c1c6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46360007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_c
sr_rw.46360007
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3181477290
Short name T806
Test name
Test status
Simulation time 50629631 ps
CPU time 0.6 seconds
Started Jul 21 04:52:09 PM PDT 24
Finished Jul 21 04:52:10 PM PDT 24
Peak memory 193900 kb
Host smart-67b01ec0-661e-442f-ad3b-2ebd67a74b8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181477290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3181477290
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3447090957
Short name T102
Test name
Test status
Simulation time 108719655 ps
CPU time 0.84 seconds
Started Jul 21 04:52:09 PM PDT 24
Finished Jul 21 04:52:10 PM PDT 24
Peak memory 196388 kb
Host smart-59f64061-7bbf-4dc4-be7c-7467a81f904b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447090957 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3447090957
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2195959656
Short name T723
Test name
Test status
Simulation time 271387435 ps
CPU time 2.48 seconds
Started Jul 21 04:52:01 PM PDT 24
Finished Jul 21 04:52:04 PM PDT 24
Peak memory 198176 kb
Host smart-d59efc0a-44b5-4315-a499-e772136e9758
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195959656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2195959656
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1619755430
Short name T46
Test name
Test status
Simulation time 45738328 ps
CPU time 0.87 seconds
Started Jul 21 04:52:25 PM PDT 24
Finished Jul 21 04:52:26 PM PDT 24
Peak memory 197840 kb
Host smart-f2a2301d-5f98-4e00-aa14-24930ca3dddf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619755430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1619755430
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2890857334
Short name T745
Test name
Test status
Simulation time 26202217 ps
CPU time 0.57 seconds
Started Jul 21 04:52:39 PM PDT 24
Finished Jul 21 04:52:40 PM PDT 24
Peak memory 193752 kb
Host smart-4bfd9f47-edd7-4b8f-8b69-293f1c03dc6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890857334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2890857334
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.4275187887
Short name T712
Test name
Test status
Simulation time 75535197 ps
CPU time 0.64 seconds
Started Jul 21 04:52:29 PM PDT 24
Finished Jul 21 04:52:30 PM PDT 24
Peak memory 193884 kb
Host smart-5123d68b-0863-419f-a169-fa41c587de9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275187887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.4275187887
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.51269992
Short name T726
Test name
Test status
Simulation time 23858295 ps
CPU time 0.63 seconds
Started Jul 21 04:52:19 PM PDT 24
Finished Jul 21 04:52:20 PM PDT 24
Peak memory 193804 kb
Host smart-ee9ca85c-d4f8-4bd9-86a7-025ba25856f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51269992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.51269992
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.263994853
Short name T803
Test name
Test status
Simulation time 14091482 ps
CPU time 0.66 seconds
Started Jul 21 04:52:24 PM PDT 24
Finished Jul 21 04:52:25 PM PDT 24
Peak memory 194464 kb
Host smart-1dc78a14-e696-4133-9a14-c8464aae8ffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263994853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.263994853
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.1962828316
Short name T791
Test name
Test status
Simulation time 16966696 ps
CPU time 0.62 seconds
Started Jul 21 04:52:30 PM PDT 24
Finished Jul 21 04:52:31 PM PDT 24
Peak memory 194620 kb
Host smart-e9da7c48-219a-428a-b406-1f8b3abc2d1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962828316 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.1962828316
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.757472137
Short name T711
Test name
Test status
Simulation time 68765339 ps
CPU time 0.59 seconds
Started Jul 21 04:52:25 PM PDT 24
Finished Jul 21 04:52:27 PM PDT 24
Peak memory 194460 kb
Host smart-ec60153e-ac3d-40e1-864f-08efd7f6ad9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757472137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.757472137
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.4160374392
Short name T710
Test name
Test status
Simulation time 14850128 ps
CPU time 0.67 seconds
Started Jul 21 04:52:24 PM PDT 24
Finished Jul 21 04:52:25 PM PDT 24
Peak memory 193824 kb
Host smart-5571fd02-503f-4545-8455-0f4fa9f758b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160374392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.4160374392
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1475689796
Short name T778
Test name
Test status
Simulation time 12379285 ps
CPU time 0.62 seconds
Started Jul 21 04:52:23 PM PDT 24
Finished Jul 21 04:52:24 PM PDT 24
Peak memory 194460 kb
Host smart-dea774eb-488a-45d9-bb56-10fa550016dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475689796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1475689796
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.2471455868
Short name T826
Test name
Test status
Simulation time 192035043 ps
CPU time 0.61 seconds
Started Jul 21 04:52:22 PM PDT 24
Finished Jul 21 04:52:23 PM PDT 24
Peak memory 194496 kb
Host smart-5303e266-9e74-4cd4-a4ed-a06220f42781
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471455868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.2471455868
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.2185269479
Short name T805
Test name
Test status
Simulation time 59795491 ps
CPU time 0.6 seconds
Started Jul 21 04:52:25 PM PDT 24
Finished Jul 21 04:52:26 PM PDT 24
Peak memory 193808 kb
Host smart-67df9a41-e920-4e2c-8692-430aed7a5548
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185269479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.2185269479
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2899974396
Short name T93
Test name
Test status
Simulation time 22149415 ps
CPU time 0.65 seconds
Started Jul 21 04:52:14 PM PDT 24
Finished Jul 21 04:52:15 PM PDT 24
Peak memory 194812 kb
Host smart-79084012-ca29-40e4-92b8-2fae8dc378d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899974396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2899974396
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2819593520
Short name T772
Test name
Test status
Simulation time 699181768 ps
CPU time 2.31 seconds
Started Jul 21 04:52:10 PM PDT 24
Finished Jul 21 04:52:14 PM PDT 24
Peak memory 197484 kb
Host smart-aad34f61-7dfa-4ce0-8a89-b55b1c937e6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819593520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2819593520
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2127593299
Short name T752
Test name
Test status
Simulation time 46589813 ps
CPU time 0.57 seconds
Started Jul 21 04:52:24 PM PDT 24
Finished Jul 21 04:52:26 PM PDT 24
Peak memory 194700 kb
Host smart-388fdc4b-39ee-4e77-bf79-bf60409037f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127593299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2127593299
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.423728933
Short name T771
Test name
Test status
Simulation time 77618669 ps
CPU time 0.74 seconds
Started Jul 21 04:52:02 PM PDT 24
Finished Jul 21 04:52:03 PM PDT 24
Peak memory 197976 kb
Host smart-acba2b48-3f1c-4952-a6b1-06086f933b13
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423728933 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.423728933
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3175045746
Short name T94
Test name
Test status
Simulation time 17098178 ps
CPU time 0.61 seconds
Started Jul 21 04:52:09 PM PDT 24
Finished Jul 21 04:52:11 PM PDT 24
Peak memory 194896 kb
Host smart-933efcdb-ac72-4151-ba25-c2a094cb024c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175045746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3175045746
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1394821599
Short name T770
Test name
Test status
Simulation time 32132641 ps
CPU time 0.58 seconds
Started Jul 21 04:52:15 PM PDT 24
Finished Jul 21 04:52:16 PM PDT 24
Peak memory 193896 kb
Host smart-1aeb49d7-f82e-420c-b2bf-860db043753c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394821599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1394821599
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.192042096
Short name T817
Test name
Test status
Simulation time 302815448 ps
CPU time 0.79 seconds
Started Jul 21 04:51:58 PM PDT 24
Finished Jul 21 04:51:59 PM PDT 24
Peak memory 196904 kb
Host smart-fa819731-2a11-4ddc-8dde-ce2485ee0aee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192042096 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 3.gpio_same_csr_outstanding.192042096
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.972787666
Short name T790
Test name
Test status
Simulation time 131994967 ps
CPU time 2.67 seconds
Started Jul 21 04:52:04 PM PDT 24
Finished Jul 21 04:52:07 PM PDT 24
Peak memory 198456 kb
Host smart-c7cab7bb-2c81-4749-8516-d0f9223b19cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972787666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.972787666
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.102186522
Short name T798
Test name
Test status
Simulation time 1031303936 ps
CPU time 1.22 seconds
Started Jul 21 04:52:03 PM PDT 24
Finished Jul 21 04:52:04 PM PDT 24
Peak memory 198164 kb
Host smart-2005b0dc-391f-4b0e-9472-07853dc3e503
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102186522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 3.gpio_tl_intg_err.102186522
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.3784608630
Short name T812
Test name
Test status
Simulation time 116925457 ps
CPU time 0.65 seconds
Started Jul 21 04:52:28 PM PDT 24
Finished Jul 21 04:52:29 PM PDT 24
Peak memory 193824 kb
Host smart-59804d16-e191-4c67-a31f-9e106b4f3675
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784608630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.3784608630
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.459487480
Short name T724
Test name
Test status
Simulation time 42542957 ps
CPU time 0.6 seconds
Started Jul 21 04:52:26 PM PDT 24
Finished Jul 21 04:52:28 PM PDT 24
Peak memory 193948 kb
Host smart-f385ed56-6c2e-400e-8f55-fc1b33c258f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459487480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.459487480
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3672528174
Short name T758
Test name
Test status
Simulation time 10645481 ps
CPU time 0.58 seconds
Started Jul 21 04:52:33 PM PDT 24
Finished Jul 21 04:52:34 PM PDT 24
Peak memory 193436 kb
Host smart-20d32dca-c80a-49fb-980f-e0b3eee6a088
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672528174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3672528174
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.4841187
Short name T755
Test name
Test status
Simulation time 26322194 ps
CPU time 0.6 seconds
Started Jul 21 04:52:38 PM PDT 24
Finished Jul 21 04:52:39 PM PDT 24
Peak memory 194536 kb
Host smart-3c41be21-025e-4c06-bfab-adf5985dcc8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4841187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.4841187
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.3294992599
Short name T832
Test name
Test status
Simulation time 45798265 ps
CPU time 0.64 seconds
Started Jul 21 04:52:38 PM PDT 24
Finished Jul 21 04:52:40 PM PDT 24
Peak memory 194428 kb
Host smart-f0490867-60d0-4228-b591-19dc961ae3e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294992599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.3294992599
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.533393172
Short name T775
Test name
Test status
Simulation time 65914447 ps
CPU time 0.64 seconds
Started Jul 21 04:52:29 PM PDT 24
Finished Jul 21 04:52:30 PM PDT 24
Peak memory 193920 kb
Host smart-1e9e8212-8efb-4c7a-9a9f-712a2ea24413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533393172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.533393172
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.4043738518
Short name T781
Test name
Test status
Simulation time 38559845 ps
CPU time 0.59 seconds
Started Jul 21 04:52:27 PM PDT 24
Finished Jul 21 04:52:28 PM PDT 24
Peak memory 193800 kb
Host smart-df423e69-cb19-4630-a881-e99b195bf334
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043738518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.4043738518
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.1650510008
Short name T717
Test name
Test status
Simulation time 46598050 ps
CPU time 0.61 seconds
Started Jul 21 04:52:26 PM PDT 24
Finished Jul 21 04:52:27 PM PDT 24
Peak memory 194016 kb
Host smart-4c4276a7-d2bd-4e21-8124-e0d7d579cea2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650510008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.1650510008
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.3860049690
Short name T737
Test name
Test status
Simulation time 14852570 ps
CPU time 0.64 seconds
Started Jul 21 04:52:28 PM PDT 24
Finished Jul 21 04:52:30 PM PDT 24
Peak memory 193816 kb
Host smart-24a81ac3-a932-48bd-993f-535a881548c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860049690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.3860049690
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.2626003879
Short name T825
Test name
Test status
Simulation time 13160348 ps
CPU time 0.6 seconds
Started Jul 21 04:52:26 PM PDT 24
Finished Jul 21 04:52:27 PM PDT 24
Peak memory 194428 kb
Host smart-79aec63f-0b44-4c7d-8c83-4afe3ff7ada8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626003879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.2626003879
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3630609753
Short name T95
Test name
Test status
Simulation time 143079826 ps
CPU time 0.82 seconds
Started Jul 21 04:52:23 PM PDT 24
Finished Jul 21 04:52:25 PM PDT 24
Peak memory 196092 kb
Host smart-d804b225-a673-42ed-a999-7a763aab1ffe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630609753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3630609753
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.640743718
Short name T96
Test name
Test status
Simulation time 112135455 ps
CPU time 2.18 seconds
Started Jul 21 04:52:13 PM PDT 24
Finished Jul 21 04:52:15 PM PDT 24
Peak memory 196880 kb
Host smart-fcac319d-cc14-4efa-a9d9-c7a7fa89c019
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640743718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.640743718
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.2897370122
Short name T84
Test name
Test status
Simulation time 202989579 ps
CPU time 0.66 seconds
Started Jul 21 04:52:10 PM PDT 24
Finished Jul 21 04:52:11 PM PDT 24
Peak memory 194900 kb
Host smart-f5b0bdc6-61d3-4cef-a786-74c86598a1b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897370122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.2897370122
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2159095048
Short name T777
Test name
Test status
Simulation time 39980231 ps
CPU time 0.67 seconds
Started Jul 21 04:52:16 PM PDT 24
Finished Jul 21 04:52:17 PM PDT 24
Peak memory 197244 kb
Host smart-78e618a2-b53c-4974-87da-a03d336cecc3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159095048 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2159095048
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3238004918
Short name T767
Test name
Test status
Simulation time 10930180 ps
CPU time 0.59 seconds
Started Jul 21 04:52:09 PM PDT 24
Finished Jul 21 04:52:10 PM PDT 24
Peak memory 194480 kb
Host smart-1bd4d5d8-f4a4-4844-b631-b70bf864b9e9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238004918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3238004918
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.593387151
Short name T779
Test name
Test status
Simulation time 17888336 ps
CPU time 0.61 seconds
Started Jul 21 04:52:13 PM PDT 24
Finished Jul 21 04:52:14 PM PDT 24
Peak memory 194472 kb
Host smart-692ef955-6b3a-46ee-a0dc-07380ba45f0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593387151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.593387151
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.2774847498
Short name T814
Test name
Test status
Simulation time 16076408 ps
CPU time 0.63 seconds
Started Jul 21 04:52:13 PM PDT 24
Finished Jul 21 04:52:15 PM PDT 24
Peak memory 195332 kb
Host smart-67d3e8a3-c7e4-406d-8be9-58fbaa300d7d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774847498 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.2774847498
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3606806523
Short name T760
Test name
Test status
Simulation time 33485441 ps
CPU time 1.82 seconds
Started Jul 21 04:52:23 PM PDT 24
Finished Jul 21 04:52:26 PM PDT 24
Peak memory 198160 kb
Host smart-54494f6c-27d0-43aa-89cc-bf8e654a5c5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606806523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3606806523
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.2824069026
Short name T733
Test name
Test status
Simulation time 371659692 ps
CPU time 1.15 seconds
Started Jul 21 04:52:10 PM PDT 24
Finished Jul 21 04:52:12 PM PDT 24
Peak memory 197900 kb
Host smart-3c9ddc5d-889b-4b7e-a5b6-7b9a8ee89641
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824069026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.2824069026
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3184891832
Short name T719
Test name
Test status
Simulation time 17540535 ps
CPU time 0.6 seconds
Started Jul 21 04:52:34 PM PDT 24
Finished Jul 21 04:52:36 PM PDT 24
Peak memory 194512 kb
Host smart-b4bc43e5-54bd-455b-8257-f8570bf65ad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184891832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3184891832
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.1461215460
Short name T808
Test name
Test status
Simulation time 59381308 ps
CPU time 0.62 seconds
Started Jul 21 04:52:39 PM PDT 24
Finished Jul 21 04:52:40 PM PDT 24
Peak memory 194600 kb
Host smart-568e7016-7baf-4722-a3bb-c88b380620de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461215460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.1461215460
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3239801979
Short name T766
Test name
Test status
Simulation time 63500995 ps
CPU time 0.61 seconds
Started Jul 21 04:52:39 PM PDT 24
Finished Jul 21 04:52:40 PM PDT 24
Peak memory 193920 kb
Host smart-5cf3fabb-0ae6-4e78-ac48-80992bdbb267
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239801979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3239801979
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.2976656523
Short name T714
Test name
Test status
Simulation time 13620529 ps
CPU time 0.54 seconds
Started Jul 21 04:52:36 PM PDT 24
Finished Jul 21 04:52:37 PM PDT 24
Peak memory 193772 kb
Host smart-425e1611-886d-4a12-a08f-2a0057f11b3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976656523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.2976656523
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.884217995
Short name T718
Test name
Test status
Simulation time 59952708 ps
CPU time 0.63 seconds
Started Jul 21 04:52:37 PM PDT 24
Finished Jul 21 04:52:38 PM PDT 24
Peak memory 194600 kb
Host smart-f791583c-a766-4aa5-9259-63186aedfe90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884217995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.884217995
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.884190016
Short name T831
Test name
Test status
Simulation time 55549888 ps
CPU time 0.62 seconds
Started Jul 21 04:52:28 PM PDT 24
Finished Jul 21 04:52:30 PM PDT 24
Peak memory 194624 kb
Host smart-21d703d8-2c8d-47cf-8653-4b37c8a391dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884190016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.884190016
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1151220373
Short name T722
Test name
Test status
Simulation time 37975808 ps
CPU time 0.58 seconds
Started Jul 21 04:52:28 PM PDT 24
Finished Jul 21 04:52:29 PM PDT 24
Peak memory 193772 kb
Host smart-a7b3277c-c804-42e9-9e99-b6ef5c1fdd6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151220373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1151220373
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3596577378
Short name T720
Test name
Test status
Simulation time 12321265 ps
CPU time 0.6 seconds
Started Jul 21 04:52:42 PM PDT 24
Finished Jul 21 04:52:43 PM PDT 24
Peak memory 193876 kb
Host smart-a159327c-139b-4791-970d-7dd8eba161b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596577378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3596577378
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.1871017727
Short name T786
Test name
Test status
Simulation time 48755449 ps
CPU time 0.6 seconds
Started Jul 21 04:52:33 PM PDT 24
Finished Jul 21 04:52:34 PM PDT 24
Peak memory 194016 kb
Host smart-78a34145-1cb4-45f9-a195-998111541774
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871017727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.1871017727
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3240243686
Short name T732
Test name
Test status
Simulation time 30269087 ps
CPU time 0.65 seconds
Started Jul 21 04:52:28 PM PDT 24
Finished Jul 21 04:52:29 PM PDT 24
Peak memory 193948 kb
Host smart-eec337ae-2789-4263-ab21-e3d6f6b77495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240243686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3240243686
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.2630306294
Short name T829
Test name
Test status
Simulation time 38072254 ps
CPU time 1.12 seconds
Started Jul 21 04:52:22 PM PDT 24
Finished Jul 21 04:52:23 PM PDT 24
Peak memory 198068 kb
Host smart-232aa2d5-2904-40ff-997f-63879fbca99d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630306294 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.2630306294
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.263815177
Short name T796
Test name
Test status
Simulation time 109013259 ps
CPU time 0.57 seconds
Started Jul 21 04:52:13 PM PDT 24
Finished Jul 21 04:52:14 PM PDT 24
Peak memory 193448 kb
Host smart-4e18c130-2e6c-46c7-a364-740151cf20f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263815177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.263815177
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.3473493170
Short name T824
Test name
Test status
Simulation time 10734530 ps
CPU time 0.61 seconds
Started Jul 21 04:52:10 PM PDT 24
Finished Jul 21 04:52:11 PM PDT 24
Peak memory 194456 kb
Host smart-bf452140-eea2-475a-a083-d0c7c3b842a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473493170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.3473493170
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.3816040293
Short name T816
Test name
Test status
Simulation time 53325247 ps
CPU time 0.7 seconds
Started Jul 21 04:52:08 PM PDT 24
Finished Jul 21 04:52:09 PM PDT 24
Peak memory 195992 kb
Host smart-2488b17d-76ae-4ab1-a557-62514bb62d2a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816040293 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.3816040293
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.347148020
Short name T721
Test name
Test status
Simulation time 121696989 ps
CPU time 1.39 seconds
Started Jul 21 04:52:10 PM PDT 24
Finished Jul 21 04:52:13 PM PDT 24
Peak memory 197972 kb
Host smart-aaec6b1f-e95a-434e-bd5e-0a561c99b14c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347148020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.347148020
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.645083676
Short name T43
Test name
Test status
Simulation time 1210639044 ps
CPU time 1.5 seconds
Started Jul 21 04:52:11 PM PDT 24
Finished Jul 21 04:52:13 PM PDT 24
Peak memory 198168 kb
Host smart-068c5991-3ab1-4b11-978b-c4bb239e31f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645083676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.645083676
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2821353979
Short name T813
Test name
Test status
Simulation time 18587617 ps
CPU time 0.67 seconds
Started Jul 21 04:52:10 PM PDT 24
Finished Jul 21 04:52:12 PM PDT 24
Peak memory 196692 kb
Host smart-3ec6e192-535b-4852-8aa6-8b307c579634
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821353979 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2821353979
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3914938879
Short name T98
Test name
Test status
Simulation time 17879393 ps
CPU time 0.61 seconds
Started Jul 21 04:52:04 PM PDT 24
Finished Jul 21 04:52:05 PM PDT 24
Peak memory 194828 kb
Host smart-3924761a-9040-4d9a-80a0-ac20c6e24591
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914938879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3914938879
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1935926478
Short name T757
Test name
Test status
Simulation time 17034200 ps
CPU time 0.64 seconds
Started Jul 21 04:52:19 PM PDT 24
Finished Jul 21 04:52:20 PM PDT 24
Peak memory 193948 kb
Host smart-4f713f69-e10a-4a02-8da4-207f83ec6cb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935926478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1935926478
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.913246285
Short name T811
Test name
Test status
Simulation time 71927580 ps
CPU time 0.82 seconds
Started Jul 21 04:52:11 PM PDT 24
Finished Jul 21 04:52:12 PM PDT 24
Peak memory 196988 kb
Host smart-c26bd1d2-5069-4727-9c73-424a97d17546
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913246285 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 6.gpio_same_csr_outstanding.913246285
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.374597053
Short name T818
Test name
Test status
Simulation time 358088438 ps
CPU time 3.03 seconds
Started Jul 21 04:52:16 PM PDT 24
Finished Jul 21 04:52:19 PM PDT 24
Peak memory 198096 kb
Host smart-c85e91af-621c-4ef4-b6bd-d3ffce9464b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374597053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.374597053
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3601582253
Short name T741
Test name
Test status
Simulation time 905695489 ps
CPU time 1.12 seconds
Started Jul 21 04:52:25 PM PDT 24
Finished Jul 21 04:52:27 PM PDT 24
Peak memory 198192 kb
Host smart-7e2fa43f-7ffc-448a-95ac-4c75316f7544
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601582253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3601582253
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.591611758
Short name T739
Test name
Test status
Simulation time 20688922 ps
CPU time 1 seconds
Started Jul 21 04:52:18 PM PDT 24
Finished Jul 21 04:52:19 PM PDT 24
Peak memory 197936 kb
Host smart-62f344e5-2297-4464-9e91-1a830fbfe6d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591611758 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.591611758
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2890067673
Short name T764
Test name
Test status
Simulation time 73891453 ps
CPU time 0.55 seconds
Started Jul 21 04:52:22 PM PDT 24
Finished Jul 21 04:52:23 PM PDT 24
Peak memory 193388 kb
Host smart-dc720b32-0704-491f-b625-1da6bf83c332
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890067673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2890067673
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2854942349
Short name T828
Test name
Test status
Simulation time 45829843 ps
CPU time 0.57 seconds
Started Jul 21 04:52:13 PM PDT 24
Finished Jul 21 04:52:15 PM PDT 24
Peak memory 193828 kb
Host smart-1a64cd3d-cdd1-43ac-878b-5eb487957217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854942349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2854942349
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.284930914
Short name T104
Test name
Test status
Simulation time 61132015 ps
CPU time 0.64 seconds
Started Jul 21 04:52:12 PM PDT 24
Finished Jul 21 04:52:13 PM PDT 24
Peak memory 194796 kb
Host smart-a2cef1c2-fbd9-44c0-b9d2-95a2bd60966f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284930914 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.284930914
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.584521966
Short name T738
Test name
Test status
Simulation time 174951553 ps
CPU time 3.04 seconds
Started Jul 21 04:52:27 PM PDT 24
Finished Jul 21 04:52:31 PM PDT 24
Peak memory 198096 kb
Host smart-23205f0a-b203-4129-b664-23c975dbc38a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584521966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.584521966
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.1882523779
Short name T36
Test name
Test status
Simulation time 102995164 ps
CPU time 1.3 seconds
Started Jul 21 04:52:24 PM PDT 24
Finished Jul 21 04:52:26 PM PDT 24
Peak memory 198052 kb
Host smart-8b71beec-fd21-4cfa-94c0-0c0e65d9dfea
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882523779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.1882523779
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.3692175681
Short name T773
Test name
Test status
Simulation time 47459820 ps
CPU time 1.26 seconds
Started Jul 21 04:52:27 PM PDT 24
Finished Jul 21 04:52:29 PM PDT 24
Peak memory 198180 kb
Host smart-20c817c0-2350-4fb2-89f1-1c2fd8eed3d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692175681 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.3692175681
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1454426900
Short name T743
Test name
Test status
Simulation time 57199741 ps
CPU time 0.61 seconds
Started Jul 21 04:52:05 PM PDT 24
Finished Jul 21 04:52:06 PM PDT 24
Peak memory 195196 kb
Host smart-d7f06bac-c3fa-4639-89ec-08cad1c4b120
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454426900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1454426900
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.20308058
Short name T768
Test name
Test status
Simulation time 17587468 ps
CPU time 0.62 seconds
Started Jul 21 04:52:11 PM PDT 24
Finished Jul 21 04:52:12 PM PDT 24
Peak memory 193828 kb
Host smart-8e0e0e13-2408-4e45-8030-3c7688a1ac11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20308058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.20308058
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.72432191
Short name T804
Test name
Test status
Simulation time 14693291 ps
CPU time 0.74 seconds
Started Jul 21 04:52:10 PM PDT 24
Finished Jul 21 04:52:11 PM PDT 24
Peak memory 195656 kb
Host smart-31d412cc-297e-4641-bb43-e22eff3ac74e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72432191 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.gpio_same_csr_outstanding.72432191
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1556450665
Short name T754
Test name
Test status
Simulation time 39645203 ps
CPU time 2.12 seconds
Started Jul 21 04:52:05 PM PDT 24
Finished Jul 21 04:52:07 PM PDT 24
Peak memory 198288 kb
Host smart-89172c3f-78c3-4712-a795-e22eb4027f21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556450665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1556450665
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3120852565
Short name T48
Test name
Test status
Simulation time 107745387 ps
CPU time 1.31 seconds
Started Jul 21 04:52:09 PM PDT 24
Finished Jul 21 04:52:11 PM PDT 24
Peak memory 198148 kb
Host smart-1c780fbc-820b-45f4-b686-7844f7a97fd5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120852565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3120852565
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2649471851
Short name T769
Test name
Test status
Simulation time 107265281 ps
CPU time 0.9 seconds
Started Jul 21 04:52:18 PM PDT 24
Finished Jul 21 04:52:19 PM PDT 24
Peak memory 198116 kb
Host smart-e62b6a0d-e832-4206-9898-a4a97db4b490
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649471851 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2649471851
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2682864502
Short name T90
Test name
Test status
Simulation time 51107272 ps
CPU time 0.6 seconds
Started Jul 21 04:52:21 PM PDT 24
Finished Jul 21 04:52:22 PM PDT 24
Peak memory 194448 kb
Host smart-854b2933-b3d2-4036-a882-37b725af56d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682864502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2682864502
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.1934975102
Short name T774
Test name
Test status
Simulation time 10631798 ps
CPU time 0.6 seconds
Started Jul 21 04:52:04 PM PDT 24
Finished Jul 21 04:52:05 PM PDT 24
Peak memory 194508 kb
Host smart-bd885b24-4633-4837-bc8e-00f49c5f8c03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934975102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.1934975102
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2977845926
Short name T86
Test name
Test status
Simulation time 112431851 ps
CPU time 0.74 seconds
Started Jul 21 04:52:12 PM PDT 24
Finished Jul 21 04:52:13 PM PDT 24
Peak memory 196272 kb
Host smart-7d3b45c4-473c-4d25-9e29-e8af486939aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977845926 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2977845926
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.4220401838
Short name T747
Test name
Test status
Simulation time 398261044 ps
CPU time 2.3 seconds
Started Jul 21 04:52:20 PM PDT 24
Finished Jul 21 04:52:23 PM PDT 24
Peak memory 198068 kb
Host smart-73e94c43-bca3-4371-b424-636f110c226e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220401838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.4220401838
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3044372148
Short name T45
Test name
Test status
Simulation time 284643335 ps
CPU time 1.1 seconds
Started Jul 21 04:52:10 PM PDT 24
Finished Jul 21 04:52:12 PM PDT 24
Peak memory 198096 kb
Host smart-42403f9c-31da-4093-bdd6-156ab163b383
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044372148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3044372148
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1946162510
Short name T435
Test name
Test status
Simulation time 19439953 ps
CPU time 0.59 seconds
Started Jul 21 05:59:44 PM PDT 24
Finished Jul 21 05:59:46 PM PDT 24
Peak memory 194268 kb
Host smart-3c9c902a-6ec1-4c0e-9999-ded643e2763e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946162510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1946162510
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.921654429
Short name T601
Test name
Test status
Simulation time 53140961 ps
CPU time 0.68 seconds
Started Jul 21 05:59:40 PM PDT 24
Finished Jul 21 05:59:41 PM PDT 24
Peak memory 195492 kb
Host smart-81c119cd-3dd2-4db9-9382-c252eed7058d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921654429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.921654429
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2928871167
Short name T528
Test name
Test status
Simulation time 2365616061 ps
CPU time 24.85 seconds
Started Jul 21 05:59:40 PM PDT 24
Finished Jul 21 06:00:05 PM PDT 24
Peak memory 198368 kb
Host smart-d1a8c835-93c2-4174-ade3-8d902095bbca
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928871167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2928871167
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3872589037
Short name T657
Test name
Test status
Simulation time 31930007 ps
CPU time 0.61 seconds
Started Jul 21 05:59:36 PM PDT 24
Finished Jul 21 05:59:37 PM PDT 24
Peak memory 194552 kb
Host smart-7264b2c4-a623-467b-b387-0367f8238418
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872589037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3872589037
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2123835528
Short name T193
Test name
Test status
Simulation time 412106864 ps
CPU time 1.23 seconds
Started Jul 21 05:59:41 PM PDT 24
Finished Jul 21 05:59:43 PM PDT 24
Peak memory 196360 kb
Host smart-20be9108-1c58-4a8b-acc9-3069b54093de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123835528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2123835528
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3582060859
Short name T375
Test name
Test status
Simulation time 81958707 ps
CPU time 3.38 seconds
Started Jul 21 05:59:39 PM PDT 24
Finished Jul 21 05:59:42 PM PDT 24
Peak memory 198176 kb
Host smart-c33523f9-f7af-459f-b8b2-bd986fb70c15
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582060859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3582060859
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.1277235786
Short name T612
Test name
Test status
Simulation time 470584507 ps
CPU time 1.86 seconds
Started Jul 21 05:59:38 PM PDT 24
Finished Jul 21 05:59:41 PM PDT 24
Peak memory 197192 kb
Host smart-92c5fac5-4ce0-4a23-81a4-73d50a649cfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277235786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
1277235786
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.210514501
Short name T376
Test name
Test status
Simulation time 99952712 ps
CPU time 0.8 seconds
Started Jul 21 05:59:37 PM PDT 24
Finished Jul 21 05:59:38 PM PDT 24
Peak memory 197308 kb
Host smart-062e6273-caf3-4966-94de-68b98d2143f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210514501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.210514501
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3757966868
Short name T289
Test name
Test status
Simulation time 53752475 ps
CPU time 0.7 seconds
Started Jul 21 05:59:38 PM PDT 24
Finished Jul 21 05:59:39 PM PDT 24
Peak memory 195268 kb
Host smart-dc83b6c1-813c-4966-88d1-a9f2bc47eeb9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757966868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3757966868
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.594427277
Short name T27
Test name
Test status
Simulation time 999766953 ps
CPU time 3.04 seconds
Started Jul 21 05:59:38 PM PDT 24
Finished Jul 21 05:59:42 PM PDT 24
Peak memory 198220 kb
Host smart-cbd16eb8-8a02-4084-a96a-687a8acd7abd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594427277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand
om_long_reg_writes_reg_reads.594427277
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.2308705907
Short name T157
Test name
Test status
Simulation time 279374917 ps
CPU time 1.49 seconds
Started Jul 21 05:59:38 PM PDT 24
Finished Jul 21 05:59:40 PM PDT 24
Peak memory 197136 kb
Host smart-77c3aae2-8452-48ff-8642-8fd97c5502fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308705907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2308705907
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1079811561
Short name T286
Test name
Test status
Simulation time 58015145 ps
CPU time 1.26 seconds
Started Jul 21 05:59:39 PM PDT 24
Finished Jul 21 05:59:41 PM PDT 24
Peak memory 196768 kb
Host smart-304c7cfe-d3a2-4701-b905-ce83dc4e9143
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079811561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1079811561
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1059285028
Short name T322
Test name
Test status
Simulation time 3470702509 ps
CPU time 95.7 seconds
Started Jul 21 05:59:41 PM PDT 24
Finished Jul 21 06:01:17 PM PDT 24
Peak memory 198312 kb
Host smart-09d159e3-309f-4ec8-ae9e-9f9b05a22126
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059285028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1059285028
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.2811572358
Short name T63
Test name
Test status
Simulation time 594579078313 ps
CPU time 1010.83 seconds
Started Jul 21 05:59:44 PM PDT 24
Finished Jul 21 06:16:37 PM PDT 24
Peak memory 198444 kb
Host smart-8a7de78d-da2c-4dbe-bfdf-d9836786407b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2811572358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.2811572358
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.3988243654
Short name T224
Test name
Test status
Simulation time 14201668 ps
CPU time 0.58 seconds
Started Jul 21 05:59:46 PM PDT 24
Finished Jul 21 05:59:48 PM PDT 24
Peak memory 194176 kb
Host smart-7b2ee0d2-a6ed-40fe-91cf-8c0426c62174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988243654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.3988243654
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.580702874
Short name T572
Test name
Test status
Simulation time 21923931 ps
CPU time 0.7 seconds
Started Jul 21 05:59:43 PM PDT 24
Finished Jul 21 05:59:44 PM PDT 24
Peak memory 194212 kb
Host smart-be9d0157-fa76-48f8-b028-5cf6b385c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580702874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.580702874
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1888826652
Short name T596
Test name
Test status
Simulation time 218186395 ps
CPU time 7.29 seconds
Started Jul 21 05:59:45 PM PDT 24
Finished Jul 21 05:59:53 PM PDT 24
Peak memory 198268 kb
Host smart-aa124e49-1247-41b2-8877-c7f1a6d344df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888826652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1888826652
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1002461866
Short name T338
Test name
Test status
Simulation time 47907865 ps
CPU time 0.73 seconds
Started Jul 21 05:59:45 PM PDT 24
Finished Jul 21 05:59:47 PM PDT 24
Peak memory 195516 kb
Host smart-9c346177-42db-46e5-9587-62e8b08d8800
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002461866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1002461866
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.296075152
Short name T134
Test name
Test status
Simulation time 133665552 ps
CPU time 1.13 seconds
Started Jul 21 05:59:47 PM PDT 24
Finished Jul 21 05:59:49 PM PDT 24
Peak memory 196224 kb
Host smart-44bc6c9d-d746-40d1-89fa-3f4cfaa5760c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296075152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.296075152
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.1109598056
Short name T113
Test name
Test status
Simulation time 25120839 ps
CPU time 1.08 seconds
Started Jul 21 05:59:46 PM PDT 24
Finished Jul 21 05:59:48 PM PDT 24
Peak memory 196124 kb
Host smart-d1c28839-8303-4429-b264-d968a4d45069
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109598056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.1109598056
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3552292679
Short name T162
Test name
Test status
Simulation time 95968522 ps
CPU time 1.64 seconds
Started Jul 21 05:59:47 PM PDT 24
Finished Jul 21 05:59:50 PM PDT 24
Peak memory 196316 kb
Host smart-2a4da0df-c3e4-471f-bb80-221ae310aac0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552292679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3552292679
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.384072516
Short name T531
Test name
Test status
Simulation time 58893728 ps
CPU time 0.85 seconds
Started Jul 21 05:59:44 PM PDT 24
Finished Jul 21 05:59:46 PM PDT 24
Peak memory 196460 kb
Host smart-fad412b1-d5f4-44c6-98c8-9d0efd6e1577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384072516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.384072516
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.2447264470
Short name T176
Test name
Test status
Simulation time 21219472 ps
CPU time 0.84 seconds
Started Jul 21 05:59:44 PM PDT 24
Finished Jul 21 05:59:46 PM PDT 24
Peak memory 196828 kb
Host smart-356782bc-31c1-4520-88a3-90e11639863b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447264470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.2447264470
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.868262784
Short name T458
Test name
Test status
Simulation time 152764770 ps
CPU time 1.65 seconds
Started Jul 21 05:59:42 PM PDT 24
Finished Jul 21 05:59:45 PM PDT 24
Peak memory 198176 kb
Host smart-50cee78f-2e85-41da-9426-51f577262df6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868262784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand
om_long_reg_writes_reg_reads.868262784
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3025706132
Short name T39
Test name
Test status
Simulation time 141758853 ps
CPU time 0.87 seconds
Started Jul 21 05:59:44 PM PDT 24
Finished Jul 21 05:59:46 PM PDT 24
Peak memory 214316 kb
Host smart-3dbcb87e-3e0c-45ac-91da-b8948098d38b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025706132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3025706132
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.455092998
Short name T618
Test name
Test status
Simulation time 60398870 ps
CPU time 0.88 seconds
Started Jul 21 05:59:44 PM PDT 24
Finished Jul 21 05:59:46 PM PDT 24
Peak memory 195576 kb
Host smart-d67fb97b-ed8d-4be9-ba4f-bc5363b35f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455092998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.455092998
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1380714659
Short name T508
Test name
Test status
Simulation time 109487525 ps
CPU time 0.89 seconds
Started Jul 21 05:59:47 PM PDT 24
Finished Jul 21 05:59:49 PM PDT 24
Peak memory 195320 kb
Host smart-4c1adc0b-bc29-49f1-b23e-b510e96999fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380714659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1380714659
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.848509579
Short name T372
Test name
Test status
Simulation time 3151286963 ps
CPU time 34.36 seconds
Started Jul 21 05:59:43 PM PDT 24
Finished Jul 21 06:00:18 PM PDT 24
Peak memory 198328 kb
Host smart-aa947f71-94a0-4c91-adad-03fdba657557
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848509579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gp
io_stress_all.848509579
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2116504342
Short name T365
Test name
Test status
Simulation time 164364533 ps
CPU time 0.59 seconds
Started Jul 21 06:00:00 PM PDT 24
Finished Jul 21 06:00:02 PM PDT 24
Peak memory 194196 kb
Host smart-9df41d2d-ae92-403f-bda0-f49c27c14bc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116504342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2116504342
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.3001287656
Short name T489
Test name
Test status
Simulation time 54590711 ps
CPU time 0.84 seconds
Started Jul 21 05:59:59 PM PDT 24
Finished Jul 21 06:00:01 PM PDT 24
Peak memory 196152 kb
Host smart-52bed936-be89-4382-a657-59eac1c3d5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001287656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.3001287656
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.393345235
Short name T670
Test name
Test status
Simulation time 813505698 ps
CPU time 20.8 seconds
Started Jul 21 06:00:01 PM PDT 24
Finished Jul 21 06:00:22 PM PDT 24
Peak memory 198280 kb
Host smart-7becff09-932b-4bb7-a38d-843016e2be34
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393345235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.393345235
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3041473558
Short name T494
Test name
Test status
Simulation time 26205724 ps
CPU time 0.66 seconds
Started Jul 21 06:00:00 PM PDT 24
Finished Jul 21 06:00:02 PM PDT 24
Peak memory 194752 kb
Host smart-f964389a-c2a5-45ea-af2c-ef6cd3c83e2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041473558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3041473558
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.1587850037
Short name T370
Test name
Test status
Simulation time 157746079 ps
CPU time 1.24 seconds
Started Jul 21 06:00:01 PM PDT 24
Finished Jul 21 06:00:04 PM PDT 24
Peak memory 196464 kb
Host smart-8302484d-0488-4717-acb1-cc629e70bb98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587850037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.1587850037
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3566091689
Short name T170
Test name
Test status
Simulation time 22355281 ps
CPU time 1.04 seconds
Started Jul 21 06:00:01 PM PDT 24
Finished Jul 21 06:00:03 PM PDT 24
Peak memory 196472 kb
Host smart-f728b048-af11-4ec2-90f2-c8c91a614bb9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566091689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3566091689
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1137082420
Short name T178
Test name
Test status
Simulation time 166991148 ps
CPU time 2.15 seconds
Started Jul 21 06:00:05 PM PDT 24
Finished Jul 21 06:00:07 PM PDT 24
Peak memory 198288 kb
Host smart-84ffb67e-15d9-487a-8f44-32edc4003f4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137082420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1137082420
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.2629141490
Short name T446
Test name
Test status
Simulation time 95628992 ps
CPU time 0.81 seconds
Started Jul 21 05:59:59 PM PDT 24
Finished Jul 21 06:00:01 PM PDT 24
Peak memory 196396 kb
Host smart-68bfc389-4a41-4896-b129-9bd4d2989248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629141490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.2629141490
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.821893455
Short name T237
Test name
Test status
Simulation time 68557014 ps
CPU time 0.9 seconds
Started Jul 21 06:00:05 PM PDT 24
Finished Jul 21 06:00:06 PM PDT 24
Peak memory 196904 kb
Host smart-c0912a12-5eca-480d-b3e2-e0f62bb753f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821893455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullup
_pulldown.821893455
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.4218708977
Short name T440
Test name
Test status
Simulation time 1137074853 ps
CPU time 4.41 seconds
Started Jul 21 06:00:02 PM PDT 24
Finished Jul 21 06:00:07 PM PDT 24
Peak memory 198200 kb
Host smart-9eb86211-b332-4a3e-b52e-04df93203577
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218708977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.4218708977
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.917909323
Short name T296
Test name
Test status
Simulation time 24841469 ps
CPU time 0.76 seconds
Started Jul 21 06:00:00 PM PDT 24
Finished Jul 21 06:00:02 PM PDT 24
Peak memory 194396 kb
Host smart-378874b4-02f2-48ed-aefe-40ea16866012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917909323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.917909323
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1508960048
Short name T438
Test name
Test status
Simulation time 49057491 ps
CPU time 0.96 seconds
Started Jul 21 06:00:05 PM PDT 24
Finished Jul 21 06:00:06 PM PDT 24
Peak memory 195552 kb
Host smart-408bcfec-4be4-4d40-8202-fab3ede5d950
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508960048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1508960048
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.2951436516
Short name T283
Test name
Test status
Simulation time 3111932113 ps
CPU time 86.99 seconds
Started Jul 21 06:00:06 PM PDT 24
Finished Jul 21 06:01:33 PM PDT 24
Peak memory 198352 kb
Host smart-e624d82b-4c88-4b5f-9ef5-e385a07844c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951436516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.2951436516
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2068867824
Short name T234
Test name
Test status
Simulation time 33575858 ps
CPU time 0.76 seconds
Started Jul 21 06:00:03 PM PDT 24
Finished Jul 21 06:00:05 PM PDT 24
Peak memory 196068 kb
Host smart-56b156fb-c8bb-4433-8122-212132074259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068867824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2068867824
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2229568963
Short name T206
Test name
Test status
Simulation time 1564665876 ps
CPU time 22.75 seconds
Started Jul 21 06:00:11 PM PDT 24
Finished Jul 21 06:00:34 PM PDT 24
Peak memory 197072 kb
Host smart-e95344d2-b00a-4c26-8196-1c21669def56
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229568963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2229568963
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3517741464
Short name T76
Test name
Test status
Simulation time 467143205 ps
CPU time 0.85 seconds
Started Jul 21 06:00:08 PM PDT 24
Finished Jul 21 06:00:10 PM PDT 24
Peak memory 196144 kb
Host smart-ad7bf0d2-03b7-4d8b-9fea-9e8379e24678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517741464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3517741464
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.135549759
Short name T299
Test name
Test status
Simulation time 56883690 ps
CPU time 1.02 seconds
Started Jul 21 06:00:01 PM PDT 24
Finished Jul 21 06:00:02 PM PDT 24
Peak memory 196748 kb
Host smart-9fda6449-8100-474b-9f04-eb6cfa2f4099
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135549759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.135549759
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.877991640
Short name T306
Test name
Test status
Simulation time 61628192 ps
CPU time 2.54 seconds
Started Jul 21 06:00:07 PM PDT 24
Finished Jul 21 06:00:10 PM PDT 24
Peak memory 198348 kb
Host smart-dec1f188-5d0a-46e6-bad2-a9f5d0b86c34
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877991640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 11.gpio_intr_with_filter_rand_intr_event.877991640
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.4096850525
Short name T502
Test name
Test status
Simulation time 566462046 ps
CPU time 3.7 seconds
Started Jul 21 05:59:59 PM PDT 24
Finished Jul 21 06:00:03 PM PDT 24
Peak memory 196752 kb
Host smart-b7292d58-4e43-4672-87bb-c47350418890
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096850525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.4096850525
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.704359848
Short name T117
Test name
Test status
Simulation time 207102617 ps
CPU time 0.83 seconds
Started Jul 21 06:00:00 PM PDT 24
Finished Jul 21 06:00:01 PM PDT 24
Peak memory 195540 kb
Host smart-a0707d47-7b43-4aee-8703-7ed596243bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704359848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.704359848
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3754959840
Short name T330
Test name
Test status
Simulation time 66897454 ps
CPU time 1.23 seconds
Started Jul 21 06:00:02 PM PDT 24
Finished Jul 21 06:00:04 PM PDT 24
Peak memory 198208 kb
Host smart-b26d055d-cd0a-4123-9fa8-f99de21ec53e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754959840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3754959840
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.3968428829
Short name T384
Test name
Test status
Simulation time 59178840 ps
CPU time 1.6 seconds
Started Jul 21 06:00:09 PM PDT 24
Finished Jul 21 06:00:11 PM PDT 24
Peak memory 198292 kb
Host smart-522c96ec-b0b1-4346-9618-955044ec27e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968428829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.3968428829
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1218686516
Short name T549
Test name
Test status
Simulation time 54408991 ps
CPU time 1.12 seconds
Started Jul 21 05:59:59 PM PDT 24
Finished Jul 21 06:00:01 PM PDT 24
Peak memory 196648 kb
Host smart-9a66d09d-3d9f-4df5-ac5e-5d38b86247c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218686516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1218686516
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2005004268
Short name T211
Test name
Test status
Simulation time 43534871 ps
CPU time 0.84 seconds
Started Jul 21 06:00:03 PM PDT 24
Finished Jul 21 06:00:05 PM PDT 24
Peak memory 196424 kb
Host smart-84e2fc0f-f561-41ec-a937-79c5a65563df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005004268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2005004268
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.3739848153
Short name T295
Test name
Test status
Simulation time 13965417883 ps
CPU time 193.69 seconds
Started Jul 21 06:00:22 PM PDT 24
Finished Jul 21 06:03:47 PM PDT 24
Peak memory 198356 kb
Host smart-970b9a86-199c-4018-bd62-9a6c3431eb0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739848153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.3739848153
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_alert_test.2415889490
Short name T667
Test name
Test status
Simulation time 22606840 ps
CPU time 0.57 seconds
Started Jul 21 06:00:09 PM PDT 24
Finished Jul 21 06:00:11 PM PDT 24
Peak memory 194884 kb
Host smart-e335295b-6833-4e70-836b-c0e567402f23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415889490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.2415889490
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.3153697664
Short name T425
Test name
Test status
Simulation time 43760229 ps
CPU time 0.99 seconds
Started Jul 21 06:00:06 PM PDT 24
Finished Jul 21 06:00:08 PM PDT 24
Peak memory 196028 kb
Host smart-53bfe299-68aa-418d-942f-df75353d8ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153697664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.3153697664
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.917281340
Short name T504
Test name
Test status
Simulation time 3367140051 ps
CPU time 20.18 seconds
Started Jul 21 06:00:08 PM PDT 24
Finished Jul 21 06:00:30 PM PDT 24
Peak memory 197168 kb
Host smart-408d0b9d-c1ad-45b8-8775-e3bffaae104d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917281340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stres
s.917281340
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1089602469
Short name T292
Test name
Test status
Simulation time 69643971 ps
CPU time 0.81 seconds
Started Jul 21 06:00:07 PM PDT 24
Finished Jul 21 06:00:09 PM PDT 24
Peak memory 196148 kb
Host smart-5688cdb9-d239-4d37-90dd-6119ebbfc7c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089602469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1089602469
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.998008942
Short name T232
Test name
Test status
Simulation time 51138663 ps
CPU time 1.32 seconds
Started Jul 21 06:00:09 PM PDT 24
Finished Jul 21 06:00:12 PM PDT 24
Peak memory 196016 kb
Host smart-a35bf4e3-f26a-459b-afcf-47aca02c3254
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998008942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.998008942
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.1822988393
Short name T605
Test name
Test status
Simulation time 46119562 ps
CPU time 1.13 seconds
Started Jul 21 06:00:12 PM PDT 24
Finished Jul 21 06:00:14 PM PDT 24
Peak memory 198092 kb
Host smart-f27ef18a-9247-42e3-b26c-9b7a9eeaeae7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822988393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.gpio_intr_with_filter_rand_intr_event.1822988393
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.646908334
Short name T472
Test name
Test status
Simulation time 279541696 ps
CPU time 2.26 seconds
Started Jul 21 06:00:12 PM PDT 24
Finished Jul 21 06:00:15 PM PDT 24
Peak memory 197296 kb
Host smart-01f28034-44a4-494a-9d07-6a496bd70733
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646908334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
646908334
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.3810516217
Short name T255
Test name
Test status
Simulation time 135318302 ps
CPU time 0.68 seconds
Started Jul 21 06:00:10 PM PDT 24
Finished Jul 21 06:00:11 PM PDT 24
Peak memory 195272 kb
Host smart-fa625225-29b2-453f-b27a-840c531f7adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810516217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.3810516217
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2211291516
Short name T114
Test name
Test status
Simulation time 15260410 ps
CPU time 0.64 seconds
Started Jul 21 06:00:08 PM PDT 24
Finished Jul 21 06:00:10 PM PDT 24
Peak memory 194408 kb
Host smart-87e0c6b5-a583-4496-a68a-3430189d9d67
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211291516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2211291516
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.2846578573
Short name T204
Test name
Test status
Simulation time 162492660 ps
CPU time 2.29 seconds
Started Jul 21 06:00:11 PM PDT 24
Finished Jul 21 06:00:14 PM PDT 24
Peak memory 198284 kb
Host smart-4b9890e9-0443-4fe3-86e3-e730c0272fb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846578573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.2846578573
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.3814840489
Short name T159
Test name
Test status
Simulation time 39198152 ps
CPU time 0.77 seconds
Started Jul 21 06:00:08 PM PDT 24
Finished Jul 21 06:00:10 PM PDT 24
Peak memory 195520 kb
Host smart-cf7b09f9-affd-489c-b88e-248701988d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814840489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.3814840489
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.1191643383
Short name T79
Test name
Test status
Simulation time 36125301 ps
CPU time 1.18 seconds
Started Jul 21 06:00:13 PM PDT 24
Finished Jul 21 06:00:15 PM PDT 24
Peak memory 196688 kb
Host smart-60b67145-9f22-4e39-9188-820f52619c4f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191643383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.1191643383
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.2452732146
Short name T432
Test name
Test status
Simulation time 2853764699 ps
CPU time 37.24 seconds
Started Jul 21 06:00:08 PM PDT 24
Finished Jul 21 06:00:46 PM PDT 24
Peak memory 198336 kb
Host smart-65f346a4-f874-4eb5-bbfc-951556d4e866
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452732146 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.2452732146
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1120211947
Short name T314
Test name
Test status
Simulation time 58833212 ps
CPU time 0.59 seconds
Started Jul 21 06:00:10 PM PDT 24
Finished Jul 21 06:00:11 PM PDT 24
Peak memory 195224 kb
Host smart-0ad12c6c-02b8-4f39-8b1a-e4a7133f9835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120211947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1120211947
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.944852080
Short name T71
Test name
Test status
Simulation time 62497131 ps
CPU time 0.82 seconds
Started Jul 21 06:00:07 PM PDT 24
Finished Jul 21 06:00:09 PM PDT 24
Peak memory 195464 kb
Host smart-42d80124-16f8-4094-93c0-0206d22426df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944852080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.944852080
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.2545679942
Short name T205
Test name
Test status
Simulation time 8486184941 ps
CPU time 21.25 seconds
Started Jul 21 06:00:07 PM PDT 24
Finished Jul 21 06:00:28 PM PDT 24
Peak memory 197208 kb
Host smart-f9be5266-8bb3-4d1e-ae8f-5c646dd7fbb7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545679942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.2545679942
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.465370175
Short name T10
Test name
Test status
Simulation time 103339312 ps
CPU time 1.01 seconds
Started Jul 21 06:00:22 PM PDT 24
Finished Jul 21 06:00:23 PM PDT 24
Peak memory 196904 kb
Host smart-1e8df5a6-b2ca-41b5-ab85-3d7150d18cf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465370175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.465370175
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.4245720030
Short name T132
Test name
Test status
Simulation time 238644892 ps
CPU time 1.13 seconds
Started Jul 21 06:00:10 PM PDT 24
Finished Jul 21 06:00:12 PM PDT 24
Peak memory 196064 kb
Host smart-25f02929-c1d3-4bac-8404-67ac0de8f3a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245720030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.4245720030
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3219715549
Short name T431
Test name
Test status
Simulation time 89968812 ps
CPU time 3.29 seconds
Started Jul 21 06:00:09 PM PDT 24
Finished Jul 21 06:00:13 PM PDT 24
Peak memory 198320 kb
Host smart-9d34f4da-5f39-44d7-bbce-8adcaf2606c9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219715549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3219715549
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.759532456
Short name T219
Test name
Test status
Simulation time 152276043 ps
CPU time 3.08 seconds
Started Jul 21 06:00:08 PM PDT 24
Finished Jul 21 06:00:12 PM PDT 24
Peak memory 198336 kb
Host smart-ea0d3ea8-b123-4843-9f58-292e1b5518aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759532456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
759532456
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.2832865851
Short name T541
Test name
Test status
Simulation time 39236613 ps
CPU time 0.85 seconds
Started Jul 21 06:00:07 PM PDT 24
Finished Jul 21 06:00:09 PM PDT 24
Peak memory 196008 kb
Host smart-6013f4ec-c071-4c40-8a1c-5879d3e46da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832865851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.2832865851
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.3364162534
Short name T340
Test name
Test status
Simulation time 26059434 ps
CPU time 0.71 seconds
Started Jul 21 06:00:07 PM PDT 24
Finished Jul 21 06:00:09 PM PDT 24
Peak memory 195692 kb
Host smart-6886dec1-a8ff-4da5-8474-d8ccf89697c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364162534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.3364162534
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2583037920
Short name T143
Test name
Test status
Simulation time 346472719 ps
CPU time 4.75 seconds
Started Jul 21 06:00:08 PM PDT 24
Finished Jul 21 06:00:14 PM PDT 24
Peak memory 198236 kb
Host smart-f89b45b4-07be-4018-bb54-71ec216992ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583037920 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2583037920
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.1212181529
Short name T173
Test name
Test status
Simulation time 122537185 ps
CPU time 1.08 seconds
Started Jul 21 06:00:07 PM PDT 24
Finished Jul 21 06:00:09 PM PDT 24
Peak memory 196736 kb
Host smart-50291052-1307-415e-a8a9-36fad6a241d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212181529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.1212181529
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.582832637
Short name T524
Test name
Test status
Simulation time 32162853 ps
CPU time 0.98 seconds
Started Jul 21 06:00:22 PM PDT 24
Finished Jul 21 06:00:23 PM PDT 24
Peak memory 195748 kb
Host smart-4c38535d-4b62-4521-b820-78454b6d6c8d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582832637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.582832637
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.286507948
Short name T288
Test name
Test status
Simulation time 31895620849 ps
CPU time 108.91 seconds
Started Jul 21 06:00:12 PM PDT 24
Finished Jul 21 06:02:02 PM PDT 24
Peak memory 198200 kb
Host smart-b8e532db-30ca-42b8-bfd1-37dfc2016678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286507948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.286507948
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_alert_test.558147314
Short name T222
Test name
Test status
Simulation time 18929896 ps
CPU time 0.57 seconds
Started Jul 21 06:00:12 PM PDT 24
Finished Jul 21 06:00:13 PM PDT 24
Peak memory 194884 kb
Host smart-f08e1d3a-3ffa-4ef0-9eee-0de216d87474
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558147314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.558147314
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.2231635156
Short name T484
Test name
Test status
Simulation time 71800441 ps
CPU time 0.82 seconds
Started Jul 21 06:00:08 PM PDT 24
Finished Jul 21 06:00:09 PM PDT 24
Peak memory 195432 kb
Host smart-0b6058a7-e217-43af-a101-7ca42b0c655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231635156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.2231635156
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.769790181
Short name T519
Test name
Test status
Simulation time 5214652060 ps
CPU time 27.07 seconds
Started Jul 21 06:00:14 PM PDT 24
Finished Jul 21 06:00:42 PM PDT 24
Peak memory 196972 kb
Host smart-35bb3626-e347-4750-855a-6707c5e23e1f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769790181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stres
s.769790181
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.710424422
Short name T633
Test name
Test status
Simulation time 186336164 ps
CPU time 0.82 seconds
Started Jul 21 06:00:07 PM PDT 24
Finished Jul 21 06:00:09 PM PDT 24
Peak memory 196128 kb
Host smart-71366508-a214-40f5-bad6-9c7f16a498eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710424422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.710424422
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.103860023
Short name T589
Test name
Test status
Simulation time 89770077 ps
CPU time 0.91 seconds
Started Jul 21 06:00:12 PM PDT 24
Finished Jul 21 06:00:13 PM PDT 24
Peak memory 196692 kb
Host smart-715b8f27-5734-4e62-a934-8d2dfa0322d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103860023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.103860023
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.2526051370
Short name T244
Test name
Test status
Simulation time 40267924 ps
CPU time 1.7 seconds
Started Jul 21 06:00:12 PM PDT 24
Finished Jul 21 06:00:15 PM PDT 24
Peak memory 197120 kb
Host smart-d5125f12-bd71-4333-be02-ea97d0902a2c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526051370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.2526051370
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2042803009
Short name T465
Test name
Test status
Simulation time 39408581 ps
CPU time 1.05 seconds
Started Jul 21 06:00:13 PM PDT 24
Finished Jul 21 06:00:15 PM PDT 24
Peak memory 195776 kb
Host smart-a66dd049-fd93-4320-9c23-e3710ffec899
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042803009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2042803009
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.1294225936
Short name T277
Test name
Test status
Simulation time 24538828 ps
CPU time 0.72 seconds
Started Jul 21 06:00:08 PM PDT 24
Finished Jul 21 06:00:09 PM PDT 24
Peak memory 194468 kb
Host smart-c627b8bd-0823-48ff-a0a4-a2c0a1348b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294225936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.1294225936
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.1897209657
Short name T284
Test name
Test status
Simulation time 123515704 ps
CPU time 0.79 seconds
Started Jul 21 06:00:11 PM PDT 24
Finished Jul 21 06:00:12 PM PDT 24
Peak memory 195740 kb
Host smart-6aa62c69-3f8c-4ebc-9786-d239a49b07cd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897209657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.1897209657
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.2246131688
Short name T361
Test name
Test status
Simulation time 1193036556 ps
CPU time 5.8 seconds
Started Jul 21 06:00:07 PM PDT 24
Finished Jul 21 06:00:14 PM PDT 24
Peak memory 198164 kb
Host smart-3a78889d-3bd6-4739-9e9a-3e584d9a72c3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246131688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.2246131688
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.412488118
Short name T152
Test name
Test status
Simulation time 309011721 ps
CPU time 1.4 seconds
Started Jul 21 06:00:10 PM PDT 24
Finished Jul 21 06:00:13 PM PDT 24
Peak memory 196536 kb
Host smart-830356a1-ea1a-4ede-8ccd-2b4da26091cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412488118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.412488118
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.691652832
Short name T642
Test name
Test status
Simulation time 68957145 ps
CPU time 0.85 seconds
Started Jul 21 06:00:08 PM PDT 24
Finished Jul 21 06:00:10 PM PDT 24
Peak memory 196176 kb
Host smart-61b236e0-7a0b-46f7-81f7-06c78c9e8150
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691652832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.691652832
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.90279089
Short name T643
Test name
Test status
Simulation time 15898542637 ps
CPU time 185.67 seconds
Started Jul 21 06:00:10 PM PDT 24
Finished Jul 21 06:03:16 PM PDT 24
Peak memory 198288 kb
Host smart-9729ddff-436a-434a-82a5-c9056f73f6c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90279089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gp
io_stress_all.90279089
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_alert_test.980287779
Short name T216
Test name
Test status
Simulation time 21103957 ps
CPU time 0.56 seconds
Started Jul 21 06:00:15 PM PDT 24
Finished Jul 21 06:00:16 PM PDT 24
Peak memory 194900 kb
Host smart-95ac6ea5-8ba3-4547-a341-98527f488baa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980287779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.980287779
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3831846142
Short name T539
Test name
Test status
Simulation time 167007735 ps
CPU time 0.92 seconds
Started Jul 21 06:00:07 PM PDT 24
Finished Jul 21 06:00:08 PM PDT 24
Peak memory 196688 kb
Host smart-fb75b852-03da-4451-8bdd-1cd98f95a959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831846142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3831846142
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2351640742
Short name T198
Test name
Test status
Simulation time 146525161 ps
CPU time 4.19 seconds
Started Jul 21 06:00:12 PM PDT 24
Finished Jul 21 06:00:17 PM PDT 24
Peak memory 196188 kb
Host smart-51d51d7f-1682-445a-ae30-2d2eafe8b0bf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351640742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2351640742
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3500331432
Short name T651
Test name
Test status
Simulation time 46020844 ps
CPU time 0.8 seconds
Started Jul 21 06:00:14 PM PDT 24
Finished Jul 21 06:00:15 PM PDT 24
Peak memory 196140 kb
Host smart-548bbd01-953e-4af6-bc64-583319af337c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500331432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3500331432
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3893745852
Short name T594
Test name
Test status
Simulation time 136715579 ps
CPU time 1.01 seconds
Started Jul 21 06:00:25 PM PDT 24
Finished Jul 21 06:00:27 PM PDT 24
Peak memory 196728 kb
Host smart-496c3043-39d7-49fb-9c8d-3f717b487179
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893745852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3893745852
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1274078241
Short name T681
Test name
Test status
Simulation time 342147419 ps
CPU time 3.33 seconds
Started Jul 21 06:00:08 PM PDT 24
Finished Jul 21 06:00:12 PM PDT 24
Peak memory 198240 kb
Host smart-66b4ac5b-0a30-4f70-a990-c1ae79c0ed25
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274078241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1274078241
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.4037783754
Short name T635
Test name
Test status
Simulation time 451557945 ps
CPU time 2.29 seconds
Started Jul 21 06:00:10 PM PDT 24
Finished Jul 21 06:00:13 PM PDT 24
Peak memory 197508 kb
Host smart-05c12115-c5a3-46bd-96b5-d14376a8b216
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037783754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.4037783754
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1856407410
Short name T588
Test name
Test status
Simulation time 134612155 ps
CPU time 0.9 seconds
Started Jul 21 06:00:08 PM PDT 24
Finished Jul 21 06:00:11 PM PDT 24
Peak memory 196064 kb
Host smart-c933135b-dbc0-467f-9817-9c22f6daf437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856407410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1856407410
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.3869265593
Short name T671
Test name
Test status
Simulation time 100076145 ps
CPU time 1.19 seconds
Started Jul 21 06:00:10 PM PDT 24
Finished Jul 21 06:00:12 PM PDT 24
Peak memory 196780 kb
Host smart-b4d6338a-47cd-4ab4-8d6e-5acc2033a0c4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869265593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.3869265593
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1081552264
Short name T574
Test name
Test status
Simulation time 150958211 ps
CPU time 1.94 seconds
Started Jul 21 06:00:10 PM PDT 24
Finished Jul 21 06:00:13 PM PDT 24
Peak memory 198192 kb
Host smart-92aad6dc-6110-45b7-8392-db472fee9585
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081552264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1081552264
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2928659616
Short name T311
Test name
Test status
Simulation time 441571052 ps
CPU time 1.17 seconds
Started Jul 21 06:00:09 PM PDT 24
Finished Jul 21 06:00:12 PM PDT 24
Peak memory 196784 kb
Host smart-f94266c4-d64b-44f6-96b7-927dd4478935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928659616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2928659616
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.852226340
Short name T30
Test name
Test status
Simulation time 43985703 ps
CPU time 0.99 seconds
Started Jul 21 06:00:12 PM PDT 24
Finished Jul 21 06:00:13 PM PDT 24
Peak memory 196600 kb
Host smart-ed09ffcc-9f7a-41c8-afde-5210759e2951
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852226340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.852226340
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.528880154
Short name T19
Test name
Test status
Simulation time 12640632665 ps
CPU time 137.16 seconds
Started Jul 21 06:00:13 PM PDT 24
Finished Jul 21 06:02:31 PM PDT 24
Peak memory 198344 kb
Host smart-bb95aaff-4e3f-4ea7-bb41-9a0b945feb4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528880154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.528880154
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.2309878431
Short name T317
Test name
Test status
Simulation time 13974598 ps
CPU time 0.59 seconds
Started Jul 21 06:00:14 PM PDT 24
Finished Jul 21 06:00:16 PM PDT 24
Peak memory 194188 kb
Host smart-4a5d3bc9-8268-491b-8193-e55cb836fd35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309878431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.2309878431
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2530106759
Short name T672
Test name
Test status
Simulation time 70115747 ps
CPU time 0.72 seconds
Started Jul 21 06:00:17 PM PDT 24
Finished Jul 21 06:00:19 PM PDT 24
Peak memory 194404 kb
Host smart-1bb6226f-8c73-4878-a561-30b6fa025a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530106759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2530106759
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.543823873
Short name T185
Test name
Test status
Simulation time 704746050 ps
CPU time 19.94 seconds
Started Jul 21 06:00:14 PM PDT 24
Finished Jul 21 06:00:34 PM PDT 24
Peak memory 196996 kb
Host smart-0a5c8d9d-6c53-4100-b3e5-27701c9b16d3
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543823873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stres
s.543823873
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.4222174604
Short name T14
Test name
Test status
Simulation time 67842688 ps
CPU time 0.94 seconds
Started Jul 21 06:00:23 PM PDT 24
Finished Jul 21 06:00:24 PM PDT 24
Peak memory 195180 kb
Host smart-ecffffa4-d938-4c87-9c35-7a885ac33ae8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222174604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.4222174604
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.684311083
Short name T303
Test name
Test status
Simulation time 114938714 ps
CPU time 0.95 seconds
Started Jul 21 06:00:19 PM PDT 24
Finished Jul 21 06:00:20 PM PDT 24
Peak memory 196248 kb
Host smart-029e2c68-ca0f-4167-8bf3-122de863f0ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684311083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.684311083
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2168872221
Short name T646
Test name
Test status
Simulation time 72902963 ps
CPU time 2.76 seconds
Started Jul 21 06:00:19 PM PDT 24
Finished Jul 21 06:00:23 PM PDT 24
Peak memory 198236 kb
Host smart-526cc0bc-1fc9-458e-bd28-30fd4f36527b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168872221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2168872221
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.480709921
Short name T389
Test name
Test status
Simulation time 26187602 ps
CPU time 1.04 seconds
Started Jul 21 06:00:15 PM PDT 24
Finished Jul 21 06:00:17 PM PDT 24
Peak memory 195828 kb
Host smart-e418d3b6-3cf6-4c3a-a7b1-0748ab295196
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480709921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger.
480709921
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1214016362
Short name T164
Test name
Test status
Simulation time 22263853 ps
CPU time 0.75 seconds
Started Jul 21 06:00:14 PM PDT 24
Finished Jul 21 06:00:16 PM PDT 24
Peak memory 195656 kb
Host smart-aae4b64d-61f7-42f7-83cf-e2b4f1e80ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214016362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1214016362
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.1154362434
Short name T78
Test name
Test status
Simulation time 106768073 ps
CPU time 0.87 seconds
Started Jul 21 06:00:17 PM PDT 24
Finished Jul 21 06:00:18 PM PDT 24
Peak memory 196804 kb
Host smart-2a7aed64-e195-41a5-9b07-d8a8fef9fb79
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154362434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.1154362434
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.383709838
Short name T623
Test name
Test status
Simulation time 420740906 ps
CPU time 4.67 seconds
Started Jul 21 06:00:28 PM PDT 24
Finished Jul 21 06:00:34 PM PDT 24
Peak memory 198280 kb
Host smart-7d27b27b-2383-41d5-bc02-70715b288b0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383709838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ran
dom_long_reg_writes_reg_reads.383709838
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2868685304
Short name T239
Test name
Test status
Simulation time 101215401 ps
CPU time 0.99 seconds
Started Jul 21 06:00:14 PM PDT 24
Finished Jul 21 06:00:15 PM PDT 24
Peak memory 197472 kb
Host smart-4633a1a9-d38c-46e0-9362-3bdd61832a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868685304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2868685304
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.3799172243
Short name T344
Test name
Test status
Simulation time 289517941 ps
CPU time 1.14 seconds
Started Jul 21 06:00:23 PM PDT 24
Finished Jul 21 06:00:24 PM PDT 24
Peak memory 196796 kb
Host smart-954d03e5-6f47-4527-8101-e3afe8e6c5a6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799172243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.3799172243
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.1259491040
Short name T517
Test name
Test status
Simulation time 8325375007 ps
CPU time 55.35 seconds
Started Jul 21 06:00:18 PM PDT 24
Finished Jul 21 06:01:13 PM PDT 24
Peak memory 198408 kb
Host smart-e01df3b2-4bb2-405d-99c9-f50377d03186
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259491040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.1259491040
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2357949089
Short name T391
Test name
Test status
Simulation time 11519024 ps
CPU time 0.58 seconds
Started Jul 21 06:00:16 PM PDT 24
Finished Jul 21 06:00:17 PM PDT 24
Peak memory 194248 kb
Host smart-248b0a71-df46-4a66-aef6-c49b9ebe35da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357949089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2357949089
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.4290546005
Short name T450
Test name
Test status
Simulation time 25811821 ps
CPU time 0.66 seconds
Started Jul 21 06:00:17 PM PDT 24
Finished Jul 21 06:00:18 PM PDT 24
Peak memory 194364 kb
Host smart-51e04de2-44d7-4d0b-9015-8a61b467d75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290546005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.4290546005
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2092684810
Short name T436
Test name
Test status
Simulation time 2018736448 ps
CPU time 26.29 seconds
Started Jul 21 06:00:16 PM PDT 24
Finished Jul 21 06:00:43 PM PDT 24
Peak memory 195656 kb
Host smart-27e58c0d-92a5-4017-8115-88106c6ce038
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092684810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2092684810
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.2322542672
Short name T21
Test name
Test status
Simulation time 39368178 ps
CPU time 0.75 seconds
Started Jul 21 06:00:12 PM PDT 24
Finished Jul 21 06:00:13 PM PDT 24
Peak memory 195916 kb
Host smart-9fabba22-870e-4a61-86d0-4b2057b33941
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322542672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.2322542672
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.2758173691
Short name T393
Test name
Test status
Simulation time 77828580 ps
CPU time 0.89 seconds
Started Jul 21 06:00:17 PM PDT 24
Finished Jul 21 06:00:18 PM PDT 24
Peak memory 197092 kb
Host smart-03f3dd15-bac1-47c3-be6c-d7b6ef4935fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758173691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.2758173691
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3696910604
Short name T336
Test name
Test status
Simulation time 70043776 ps
CPU time 2.99 seconds
Started Jul 21 06:00:28 PM PDT 24
Finished Jul 21 06:00:32 PM PDT 24
Peak memory 198212 kb
Host smart-f002169d-ff46-4440-b397-fa9b56a5aec5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696910604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3696910604
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1109802501
Short name T415
Test name
Test status
Simulation time 114677725 ps
CPU time 0.99 seconds
Started Jul 21 06:00:21 PM PDT 24
Finished Jul 21 06:00:22 PM PDT 24
Peak memory 195668 kb
Host smart-7ae94b5b-b777-4811-ab2f-04e3cde7013a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109802501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1109802501
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3342788655
Short name T227
Test name
Test status
Simulation time 51403843 ps
CPU time 1.29 seconds
Started Jul 21 06:00:23 PM PDT 24
Finished Jul 21 06:00:25 PM PDT 24
Peak memory 197352 kb
Host smart-c594cbb2-6719-45b1-a763-addb139c13d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342788655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3342788655
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1976237585
Short name T369
Test name
Test status
Simulation time 29834078 ps
CPU time 0.81 seconds
Started Jul 21 06:00:27 PM PDT 24
Finished Jul 21 06:00:28 PM PDT 24
Peak memory 195660 kb
Host smart-1dfc47cd-aee9-4a6a-ab1f-7a8d9e683a6f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976237585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1976237585
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2957655513
Short name T280
Test name
Test status
Simulation time 378932454 ps
CPU time 5.95 seconds
Started Jul 21 06:00:19 PM PDT 24
Finished Jul 21 06:00:25 PM PDT 24
Peak memory 198160 kb
Host smart-1a21bb48-1b18-473a-abb5-d3ec6dcf87ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957655513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2957655513
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.2726284204
Short name T74
Test name
Test status
Simulation time 151151834 ps
CPU time 0.82 seconds
Started Jul 21 06:00:21 PM PDT 24
Finished Jul 21 06:00:23 PM PDT 24
Peak memory 195452 kb
Host smart-c5935da7-bdc2-4dbe-b3a0-c89fd3952722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726284204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.2726284204
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.3944466368
Short name T383
Test name
Test status
Simulation time 66619085 ps
CPU time 1.35 seconds
Started Jul 21 06:00:23 PM PDT 24
Finished Jul 21 06:00:25 PM PDT 24
Peak memory 198240 kb
Host smart-176395b4-0084-4051-95d2-b766b302a8f6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944466368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.3944466368
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2908719386
Short name T399
Test name
Test status
Simulation time 8122016738 ps
CPU time 221.94 seconds
Started Jul 21 06:00:23 PM PDT 24
Finished Jul 21 06:04:05 PM PDT 24
Peak memory 197212 kb
Host smart-f203921d-458a-4d24-95d0-bbd7182c05ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908719386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2908719386
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_alert_test.290017576
Short name T645
Test name
Test status
Simulation time 82667909 ps
CPU time 0.56 seconds
Started Jul 21 06:00:19 PM PDT 24
Finished Jul 21 06:00:20 PM PDT 24
Peak memory 194844 kb
Host smart-082d8c06-9f00-4906-848d-edc209d78de4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290017576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.290017576
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.384233526
Short name T177
Test name
Test status
Simulation time 162216858 ps
CPU time 0.66 seconds
Started Jul 21 06:00:24 PM PDT 24
Finished Jul 21 06:00:25 PM PDT 24
Peak memory 194236 kb
Host smart-7684b8fb-45e8-453e-afe9-443ddb08c110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384233526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.384233526
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2151556635
Short name T675
Test name
Test status
Simulation time 545205128 ps
CPU time 10.1 seconds
Started Jul 21 06:00:19 PM PDT 24
Finished Jul 21 06:00:30 PM PDT 24
Peak memory 197228 kb
Host smart-912eb823-6d41-4803-a868-9f4343fbb823
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151556635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2151556635
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3989523013
Short name T410
Test name
Test status
Simulation time 94393861 ps
CPU time 0.68 seconds
Started Jul 21 06:00:19 PM PDT 24
Finished Jul 21 06:00:21 PM PDT 24
Peak memory 194728 kb
Host smart-26b5f0ab-7f0c-40ed-8694-c7256bd70efc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989523013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3989523013
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.887989140
Short name T25
Test name
Test status
Simulation time 108733322 ps
CPU time 1.01 seconds
Started Jul 21 06:00:25 PM PDT 24
Finished Jul 21 06:00:27 PM PDT 24
Peak memory 196060 kb
Host smart-35904b54-c593-4f9d-aa00-eda934c916ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887989140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.887989140
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.747706198
Short name T608
Test name
Test status
Simulation time 395299574 ps
CPU time 1.96 seconds
Started Jul 21 06:00:19 PM PDT 24
Finished Jul 21 06:00:22 PM PDT 24
Peak memory 198260 kb
Host smart-9a5d4fb9-36ce-4a0e-af1c-a5d11fd897cb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747706198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.747706198
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3310044160
Short name T674
Test name
Test status
Simulation time 191805577 ps
CPU time 1.49 seconds
Started Jul 21 06:00:17 PM PDT 24
Finished Jul 21 06:00:19 PM PDT 24
Peak memory 196364 kb
Host smart-211b6549-be05-484a-a2b2-7a4d0e0b8497
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310044160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3310044160
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3653579301
Short name T307
Test name
Test status
Simulation time 98198525 ps
CPU time 1.25 seconds
Started Jul 21 06:00:17 PM PDT 24
Finished Jul 21 06:00:19 PM PDT 24
Peak memory 197076 kb
Host smart-11df06f8-0949-462e-a020-3ff5c9d3c798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653579301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3653579301
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.802242243
Short name T111
Test name
Test status
Simulation time 17249125 ps
CPU time 0.71 seconds
Started Jul 21 06:00:31 PM PDT 24
Finished Jul 21 06:00:33 PM PDT 24
Peak memory 195592 kb
Host smart-bee5f441-982f-4dcb-8a93-9aff1c96bf69
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802242243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.802242243
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.1940425231
Short name T544
Test name
Test status
Simulation time 979500478 ps
CPU time 3.78 seconds
Started Jul 21 06:00:14 PM PDT 24
Finished Jul 21 06:00:19 PM PDT 24
Peak memory 198160 kb
Host smart-6dd0ec9f-89c7-4c3b-8f13-1bba2ad2c430
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940425231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.1940425231
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.3425442423
Short name T174
Test name
Test status
Simulation time 302642383 ps
CPU time 1.4 seconds
Started Jul 21 06:00:19 PM PDT 24
Finished Jul 21 06:00:21 PM PDT 24
Peak memory 196524 kb
Host smart-440d60a4-d653-40e1-a806-9ed0bcb9f727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425442423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.3425442423
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2534975502
Short name T663
Test name
Test status
Simulation time 308523620 ps
CPU time 1.23 seconds
Started Jul 21 06:00:17 PM PDT 24
Finished Jul 21 06:00:19 PM PDT 24
Peak memory 195952 kb
Host smart-8a778a1a-eb5d-4bdd-9854-85b04d232f91
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534975502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2534975502
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3572695252
Short name T345
Test name
Test status
Simulation time 3675168717 ps
CPU time 111.2 seconds
Started Jul 21 06:00:18 PM PDT 24
Finished Jul 21 06:02:10 PM PDT 24
Peak memory 198284 kb
Host smart-630071ef-a821-471b-90c3-50910f119c35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572695252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3572695252
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_alert_test.4166645231
Short name T210
Test name
Test status
Simulation time 32654046 ps
CPU time 0.55 seconds
Started Jul 21 06:00:26 PM PDT 24
Finished Jul 21 06:00:27 PM PDT 24
Peak memory 194176 kb
Host smart-a8cce69e-4a4b-4767-bb27-21545f7b5d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166645231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.4166645231
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.4235316808
Short name T420
Test name
Test status
Simulation time 76314036 ps
CPU time 0.67 seconds
Started Jul 21 06:00:22 PM PDT 24
Finished Jul 21 06:00:23 PM PDT 24
Peak memory 194368 kb
Host smart-e463c0fc-1c41-4a0a-b5fb-a8cac5890f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235316808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.4235316808
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.861876309
Short name T240
Test name
Test status
Simulation time 397700357 ps
CPU time 19.62 seconds
Started Jul 21 06:00:18 PM PDT 24
Finished Jul 21 06:00:38 PM PDT 24
Peak memory 197148 kb
Host smart-78f9ab6e-aebc-4d8e-b2e6-c76b21ef0053
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861876309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.861876309
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.1705317694
Short name T453
Test name
Test status
Simulation time 481138724 ps
CPU time 0.97 seconds
Started Jul 21 06:00:41 PM PDT 24
Finished Jul 21 06:00:43 PM PDT 24
Peak memory 197952 kb
Host smart-009cbab5-9387-489a-9261-187f2e7ec7a3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705317694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.1705317694
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1361897937
Short name T547
Test name
Test status
Simulation time 32584362 ps
CPU time 0.82 seconds
Started Jul 21 06:00:25 PM PDT 24
Finished Jul 21 06:00:26 PM PDT 24
Peak memory 195612 kb
Host smart-0829c718-5b37-4078-8bbf-2307d833e2c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361897937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1361897937
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2392580990
Short name T53
Test name
Test status
Simulation time 97467554 ps
CPU time 2.12 seconds
Started Jul 21 06:00:30 PM PDT 24
Finished Jul 21 06:00:32 PM PDT 24
Peak memory 198296 kb
Host smart-c3f71f32-221a-41e6-8efc-2ec10d551a30
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392580990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2392580990
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.1698872549
Short name T493
Test name
Test status
Simulation time 280070844 ps
CPU time 2.98 seconds
Started Jul 21 06:00:37 PM PDT 24
Finished Jul 21 06:00:41 PM PDT 24
Peak memory 198276 kb
Host smart-898f7eed-6b7c-480e-bcc7-5fedc90e1a22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698872549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.1698872549
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.807332784
Short name T405
Test name
Test status
Simulation time 80791848 ps
CPU time 0.92 seconds
Started Jul 21 06:00:23 PM PDT 24
Finished Jul 21 06:00:25 PM PDT 24
Peak memory 196176 kb
Host smart-24b61e51-ff07-4f4c-be2b-aa410e73aa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807332784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.807332784
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.3468335412
Short name T183
Test name
Test status
Simulation time 16509545 ps
CPU time 0.64 seconds
Started Jul 21 06:00:32 PM PDT 24
Finished Jul 21 06:00:33 PM PDT 24
Peak memory 194456 kb
Host smart-b1f5e0c8-1a36-4e77-adfd-f327136204da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468335412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.3468335412
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2012604168
Short name T644
Test name
Test status
Simulation time 158102642 ps
CPU time 1.81 seconds
Started Jul 21 06:00:25 PM PDT 24
Finished Jul 21 06:00:28 PM PDT 24
Peak memory 198232 kb
Host smart-0952c2b9-c07a-4f74-9d35-c53a2850a83b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012604168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2012604168
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1939678912
Short name T586
Test name
Test status
Simulation time 195344105 ps
CPU time 1.2 seconds
Started Jul 21 06:00:20 PM PDT 24
Finished Jul 21 06:00:22 PM PDT 24
Peak memory 196072 kb
Host smart-4d1c805d-c4c4-472c-9599-4b5c33e9d6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939678912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1939678912
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1141127912
Short name T704
Test name
Test status
Simulation time 133178170 ps
CPU time 1.3 seconds
Started Jul 21 06:00:14 PM PDT 24
Finished Jul 21 06:00:16 PM PDT 24
Peak memory 197096 kb
Host smart-b95b4552-c1d8-48d6-bbf2-196814aa7122
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141127912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1141127912
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3648425546
Short name T678
Test name
Test status
Simulation time 12212020386 ps
CPU time 170.33 seconds
Started Jul 21 06:00:25 PM PDT 24
Finished Jul 21 06:03:15 PM PDT 24
Peak memory 198304 kb
Host smart-f4cdeaa8-82d7-47db-ba31-59cbac2daa7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648425546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3648425546
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_alert_test.2686165220
Short name T483
Test name
Test status
Simulation time 17705569 ps
CPU time 0.56 seconds
Started Jul 21 05:59:44 PM PDT 24
Finished Jul 21 05:59:45 PM PDT 24
Peak memory 194272 kb
Host smart-ef4934db-e5e9-415e-8bc8-d5ea3094f0d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686165220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.2686165220
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.898395738
Short name T606
Test name
Test status
Simulation time 31461602 ps
CPU time 0.89 seconds
Started Jul 21 05:59:47 PM PDT 24
Finished Jul 21 05:59:48 PM PDT 24
Peak memory 195952 kb
Host smart-cc984e94-35d7-48d8-8de3-ee3347c78596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898395738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.898395738
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1400936497
Short name T333
Test name
Test status
Simulation time 261240265 ps
CPU time 3.26 seconds
Started Jul 21 05:59:46 PM PDT 24
Finished Jul 21 05:59:50 PM PDT 24
Peak memory 195984 kb
Host smart-7a03b3b0-afcc-4410-b387-bf14840efdfa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400936497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1400936497
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1314365026
Short name T327
Test name
Test status
Simulation time 23848523 ps
CPU time 0.66 seconds
Started Jul 21 05:59:46 PM PDT 24
Finished Jul 21 05:59:48 PM PDT 24
Peak memory 194584 kb
Host smart-a4184d5b-2de6-4772-a312-f1a7369c6387
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314365026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1314365026
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.3309937858
Short name T236
Test name
Test status
Simulation time 36091218 ps
CPU time 0.88 seconds
Started Jul 21 05:59:51 PM PDT 24
Finished Jul 21 05:59:52 PM PDT 24
Peak memory 195888 kb
Host smart-bb49bdf7-911b-44c0-8d71-ef2691fa35aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309937858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.3309937858
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1849321703
Short name T476
Test name
Test status
Simulation time 282917389 ps
CPU time 3 seconds
Started Jul 21 05:59:43 PM PDT 24
Finished Jul 21 05:59:46 PM PDT 24
Peak memory 198288 kb
Host smart-0377a4a5-81e9-41cf-9a4c-94d9e0683b48
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849321703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1849321703
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.1309646008
Short name T471
Test name
Test status
Simulation time 648622363 ps
CPU time 3.36 seconds
Started Jul 21 05:59:44 PM PDT 24
Finished Jul 21 05:59:48 PM PDT 24
Peak memory 197300 kb
Host smart-3214f4db-ecfb-4175-a371-a1ee72c4724a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309646008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
1309646008
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.1815172336
Short name T313
Test name
Test status
Simulation time 23608873 ps
CPU time 0.8 seconds
Started Jul 21 05:59:42 PM PDT 24
Finished Jul 21 05:59:43 PM PDT 24
Peak memory 196512 kb
Host smart-a176ec0c-e51f-4aaf-95ef-cfe8542acc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815172336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.1815172336
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1968923053
Short name T454
Test name
Test status
Simulation time 68409523 ps
CPU time 1.29 seconds
Started Jul 21 05:59:46 PM PDT 24
Finished Jul 21 05:59:48 PM PDT 24
Peak memory 196776 kb
Host smart-c24b57d7-cd7f-47a1-9530-5fc62aa89c87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968923053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1968923053
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.3993198445
Short name T512
Test name
Test status
Simulation time 266009187 ps
CPU time 3.24 seconds
Started Jul 21 05:59:44 PM PDT 24
Finished Jul 21 05:59:48 PM PDT 24
Peak memory 198284 kb
Host smart-5fd3297d-090a-426a-bb8d-81eff20dc0a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993198445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.3993198445
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.280517639
Short name T50
Test name
Test status
Simulation time 136910464 ps
CPU time 0.82 seconds
Started Jul 21 05:59:48 PM PDT 24
Finished Jul 21 05:59:49 PM PDT 24
Peak memory 214284 kb
Host smart-e9871892-c5cd-4d97-a839-1598a7dc967e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280517639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.280517639
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.1745309421
Short name T339
Test name
Test status
Simulation time 70720118 ps
CPU time 1.34 seconds
Started Jul 21 05:59:42 PM PDT 24
Finished Jul 21 05:59:43 PM PDT 24
Peak memory 196460 kb
Host smart-d891d0b1-807e-4226-836f-faf9d7a2930b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745309421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.1745309421
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.275967212
Short name T515
Test name
Test status
Simulation time 80957737 ps
CPU time 1.3 seconds
Started Jul 21 05:59:43 PM PDT 24
Finished Jul 21 05:59:45 PM PDT 24
Peak memory 197012 kb
Host smart-4ba8ee5b-f1fd-4fb7-a3fb-64f15eab90d6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275967212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.275967212
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.1091568283
Short name T213
Test name
Test status
Simulation time 50502089611 ps
CPU time 184.95 seconds
Started Jul 21 05:59:51 PM PDT 24
Finished Jul 21 06:02:57 PM PDT 24
Peak memory 198276 kb
Host smart-4d786b81-e9c7-4b32-985d-92d29a079b8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091568283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.1091568283
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1386473390
Short name T194
Test name
Test status
Simulation time 39229748 ps
CPU time 0.58 seconds
Started Jul 21 06:00:34 PM PDT 24
Finished Jul 21 06:00:36 PM PDT 24
Peak memory 194456 kb
Host smart-dbe96d66-065b-4b84-b4e0-49c812167546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386473390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1386473390
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.2542508670
Short name T561
Test name
Test status
Simulation time 49743591 ps
CPU time 0.68 seconds
Started Jul 21 06:00:23 PM PDT 24
Finished Jul 21 06:00:24 PM PDT 24
Peak memory 194244 kb
Host smart-6f1144fe-7583-4b9a-a433-16c00501224b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542508670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.2542508670
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.222541966
Short name T530
Test name
Test status
Simulation time 396464962 ps
CPU time 20.71 seconds
Started Jul 21 06:00:34 PM PDT 24
Finished Jul 21 06:00:55 PM PDT 24
Peak memory 197268 kb
Host smart-85f4c7bf-34de-4f31-8202-cd28e5f90d7f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222541966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.222541966
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.2046939473
Short name T20
Test name
Test status
Simulation time 24923958 ps
CPU time 0.66 seconds
Started Jul 21 06:00:40 PM PDT 24
Finished Jul 21 06:00:41 PM PDT 24
Peak memory 194656 kb
Host smart-8074026e-f9a6-4abe-af39-8f9a5f6813c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046939473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.2046939473
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.4014400805
Short name T272
Test name
Test status
Simulation time 57114956 ps
CPU time 1.01 seconds
Started Jul 21 06:00:25 PM PDT 24
Finished Jul 21 06:00:27 PM PDT 24
Peak memory 196080 kb
Host smart-c67e9381-16c1-49b7-a164-05ac9d384c15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014400805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.4014400805
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.235587838
Short name T320
Test name
Test status
Simulation time 158689638 ps
CPU time 1.73 seconds
Started Jul 21 06:00:28 PM PDT 24
Finished Jul 21 06:00:30 PM PDT 24
Peak memory 197136 kb
Host smart-16725b3c-da6f-4567-9f0b-87e32ab94716
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235587838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.235587838
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3664525645
Short name T566
Test name
Test status
Simulation time 157293860 ps
CPU time 3.3 seconds
Started Jul 21 06:00:26 PM PDT 24
Finished Jul 21 06:00:30 PM PDT 24
Peak memory 197148 kb
Host smart-47c4b505-d4c7-4319-bdf5-4d1f3ed20ac8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664525645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3664525645
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2365263689
Short name T655
Test name
Test status
Simulation time 127286957 ps
CPU time 1.33 seconds
Started Jul 21 06:00:26 PM PDT 24
Finished Jul 21 06:00:28 PM PDT 24
Peak memory 197016 kb
Host smart-64c9d9a1-8d51-4765-92fd-874b76480e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365263689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2365263689
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.2583577112
Short name T139
Test name
Test status
Simulation time 47982133 ps
CPU time 0.82 seconds
Started Jul 21 06:00:35 PM PDT 24
Finished Jul 21 06:00:36 PM PDT 24
Peak memory 195636 kb
Host smart-606a0cbe-1b56-4a32-8810-150d4b030b26
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583577112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.2583577112
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_smoke.245844104
Short name T358
Test name
Test status
Simulation time 29541665 ps
CPU time 0.72 seconds
Started Jul 21 06:00:32 PM PDT 24
Finished Jul 21 06:00:34 PM PDT 24
Peak memory 195272 kb
Host smart-ed1ca040-2b15-4bf0-8028-f4ffec375928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245844104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.245844104
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.4206339083
Short name T692
Test name
Test status
Simulation time 95574556 ps
CPU time 0.81 seconds
Started Jul 21 06:00:27 PM PDT 24
Finished Jul 21 06:00:28 PM PDT 24
Peak memory 195404 kb
Host smart-c2756b2b-5645-436a-8979-f9bc14b943d1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206339083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.4206339083
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3491874069
Short name T532
Test name
Test status
Simulation time 14852978888 ps
CPU time 93.64 seconds
Started Jul 21 06:00:18 PM PDT 24
Finished Jul 21 06:01:52 PM PDT 24
Peak memory 198292 kb
Host smart-88970814-b2bc-4b24-98be-355dcc89f242
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491874069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3491874069
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_alert_test.3218586140
Short name T80
Test name
Test status
Simulation time 31200212 ps
CPU time 0.59 seconds
Started Jul 21 06:00:26 PM PDT 24
Finished Jul 21 06:00:27 PM PDT 24
Peak memory 195036 kb
Host smart-90ec0f32-ace7-448f-9fe6-c28f1643fdfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218586140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.3218586140
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2748722224
Short name T121
Test name
Test status
Simulation time 27279300 ps
CPU time 0.74 seconds
Started Jul 21 06:00:28 PM PDT 24
Finished Jul 21 06:00:30 PM PDT 24
Peak memory 195400 kb
Host smart-d51cdf65-a18c-4ea6-baef-b83e6aaf6c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748722224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2748722224
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3190309923
Short name T490
Test name
Test status
Simulation time 326692634 ps
CPU time 9.06 seconds
Started Jul 21 06:00:36 PM PDT 24
Finished Jul 21 06:00:46 PM PDT 24
Peak memory 197104 kb
Host smart-42a6d4c6-b830-4e3a-ab18-260574372c27
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190309923 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3190309923
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1504567972
Short name T622
Test name
Test status
Simulation time 100779196 ps
CPU time 0.85 seconds
Started Jul 21 06:00:23 PM PDT 24
Finished Jul 21 06:00:24 PM PDT 24
Peak memory 196988 kb
Host smart-39c34050-a032-4df6-860b-7a5395b61a0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504567972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1504567972
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.3210743331
Short name T17
Test name
Test status
Simulation time 155796911 ps
CPU time 1.24 seconds
Started Jul 21 06:00:26 PM PDT 24
Finished Jul 21 06:00:28 PM PDT 24
Peak memory 196804 kb
Host smart-417861bb-0cb3-4ced-bdd8-e759f30e8208
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210743331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.3210743331
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3353240679
Short name T698
Test name
Test status
Simulation time 1278189095 ps
CPU time 2.79 seconds
Started Jul 21 06:00:19 PM PDT 24
Finished Jul 21 06:00:22 PM PDT 24
Peak memory 198288 kb
Host smart-96cebfb2-8876-43f1-8ff5-7141a812d405
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353240679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3353240679
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1965804707
Short name T491
Test name
Test status
Simulation time 321432003 ps
CPU time 3.47 seconds
Started Jul 21 06:00:21 PM PDT 24
Finished Jul 21 06:00:25 PM PDT 24
Peak memory 196656 kb
Host smart-e2d84775-b13e-40df-8b73-913fc1931a3a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965804707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1965804707
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3170411282
Short name T209
Test name
Test status
Simulation time 128350213 ps
CPU time 0.87 seconds
Started Jul 21 06:00:25 PM PDT 24
Finished Jul 21 06:00:27 PM PDT 24
Peak memory 197600 kb
Host smart-943fb90b-80bd-41c0-b055-02b94acf9ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170411282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3170411282
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1404101758
Short name T402
Test name
Test status
Simulation time 83258302 ps
CPU time 0.74 seconds
Started Jul 21 06:00:33 PM PDT 24
Finished Jul 21 06:00:35 PM PDT 24
Peak memory 195576 kb
Host smart-ac5244d2-b0c7-48c9-b7e3-890959bc4ae3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404101758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1404101758
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.4224468757
Short name T352
Test name
Test status
Simulation time 357142386 ps
CPU time 4.11 seconds
Started Jul 21 06:00:32 PM PDT 24
Finished Jul 21 06:00:37 PM PDT 24
Peak memory 198208 kb
Host smart-3f403b80-a170-47fd-999c-dc8ae71cb295
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224468757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.4224468757
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.3236164439
Short name T653
Test name
Test status
Simulation time 58737754 ps
CPU time 1.21 seconds
Started Jul 21 06:00:20 PM PDT 24
Finished Jul 21 06:00:22 PM PDT 24
Peak memory 195964 kb
Host smart-6a6a2dd7-9021-4dd3-9aa1-5a5f6f8efc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236164439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.3236164439
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.399420935
Short name T257
Test name
Test status
Simulation time 270477628 ps
CPU time 1.37 seconds
Started Jul 21 06:00:22 PM PDT 24
Finished Jul 21 06:00:24 PM PDT 24
Peak memory 195780 kb
Host smart-10c08f74-1b58-452c-bc1c-352859f0fef4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399420935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.399420935
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.597623819
Short name T308
Test name
Test status
Simulation time 3756111606 ps
CPU time 87.77 seconds
Started Jul 21 06:00:23 PM PDT 24
Finished Jul 21 06:01:52 PM PDT 24
Peak memory 198340 kb
Host smart-1718e051-79ce-4c56-97bd-8d26622020e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597623819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.g
pio_stress_all.597623819
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_alert_test.839354566
Short name T434
Test name
Test status
Simulation time 43112766 ps
CPU time 0.59 seconds
Started Jul 21 06:00:31 PM PDT 24
Finished Jul 21 06:00:33 PM PDT 24
Peak memory 194400 kb
Host smart-bf2b9baf-0633-4052-8b9c-d4237cfa273d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839354566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.839354566
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.1066223609
Short name T140
Test name
Test status
Simulation time 20632636 ps
CPU time 0.69 seconds
Started Jul 21 06:00:27 PM PDT 24
Finished Jul 21 06:00:28 PM PDT 24
Peak memory 194240 kb
Host smart-58331abc-a557-4940-bfa7-b47287fe63b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066223609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.1066223609
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.366938346
Short name T624
Test name
Test status
Simulation time 407280147 ps
CPU time 20.15 seconds
Started Jul 21 06:00:31 PM PDT 24
Finished Jul 21 06:00:52 PM PDT 24
Peak memory 196940 kb
Host smart-64bd9572-803d-4fb7-bb51-38f47beccb21
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366938346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.366938346
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.2748887685
Short name T367
Test name
Test status
Simulation time 175465586 ps
CPU time 0.78 seconds
Started Jul 21 06:00:33 PM PDT 24
Finished Jul 21 06:00:35 PM PDT 24
Peak memory 196140 kb
Host smart-f7cb35cd-c239-4042-ae59-dc33760cc39d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748887685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.2748887685
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3287449565
Short name T195
Test name
Test status
Simulation time 148905472 ps
CPU time 0.93 seconds
Started Jul 21 06:00:20 PM PDT 24
Finished Jul 21 06:00:22 PM PDT 24
Peak memory 197532 kb
Host smart-26428b9a-9801-4be6-916f-2c31337faab0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287449565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3287449565
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.1268572529
Short name T510
Test name
Test status
Simulation time 67495745 ps
CPU time 1.47 seconds
Started Jul 21 06:00:19 PM PDT 24
Finished Jul 21 06:00:21 PM PDT 24
Peak memory 196896 kb
Host smart-b4c23082-5471-4863-8095-914bf00c16e5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268572529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.1268572529
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2807083012
Short name T373
Test name
Test status
Simulation time 160738058 ps
CPU time 2.83 seconds
Started Jul 21 06:00:28 PM PDT 24
Finished Jul 21 06:00:31 PM PDT 24
Peak memory 197480 kb
Host smart-805847a3-0ef2-4817-8a65-596afec6f310
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807083012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2807083012
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2526033273
Short name T302
Test name
Test status
Simulation time 360636724 ps
CPU time 1.01 seconds
Started Jul 21 06:00:25 PM PDT 24
Finished Jul 21 06:00:26 PM PDT 24
Peak memory 196696 kb
Host smart-6566c15a-4812-4fd6-9d92-7c555d691994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526033273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2526033273
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.2268369510
Short name T673
Test name
Test status
Simulation time 90075850 ps
CPU time 1.05 seconds
Started Jul 21 06:00:20 PM PDT 24
Finished Jul 21 06:00:22 PM PDT 24
Peak memory 196956 kb
Host smart-4793494c-8a51-4988-9247-878a85016dad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268369510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.2268369510
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.3012962341
Short name T542
Test name
Test status
Simulation time 90515964 ps
CPU time 1.28 seconds
Started Jul 21 06:00:25 PM PDT 24
Finished Jul 21 06:00:27 PM PDT 24
Peak memory 198124 kb
Host smart-81822bfe-5985-4834-b3b7-e30a67c638f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012962341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.3012962341
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.2461329366
Short name T488
Test name
Test status
Simulation time 346771849 ps
CPU time 1.38 seconds
Started Jul 21 06:00:22 PM PDT 24
Finished Jul 21 06:00:24 PM PDT 24
Peak memory 195816 kb
Host smart-01e7591c-10e9-43cb-a632-77053bb21127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461329366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.2461329366
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.4271463097
Short name T626
Test name
Test status
Simulation time 77327046 ps
CPU time 1.28 seconds
Started Jul 21 06:00:25 PM PDT 24
Finished Jul 21 06:00:27 PM PDT 24
Peak memory 196780 kb
Host smart-29c0eacd-60ec-484d-8f97-5402f98ba0ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271463097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.4271463097
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3532473441
Short name T144
Test name
Test status
Simulation time 7546475004 ps
CPU time 104.53 seconds
Started Jul 21 06:00:36 PM PDT 24
Finished Jul 21 06:02:21 PM PDT 24
Peak memory 198272 kb
Host smart-b62fa31d-088c-43bc-9374-a727b5ab9788
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532473441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3532473441
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1718216134
Short name T56
Test name
Test status
Simulation time 16091472 ps
CPU time 0.57 seconds
Started Jul 21 06:00:40 PM PDT 24
Finished Jul 21 06:00:41 PM PDT 24
Peak memory 194204 kb
Host smart-79b5314b-b218-4a68-b8ad-205861a5023f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718216134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1718216134
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.690243461
Short name T158
Test name
Test status
Simulation time 79616464 ps
CPU time 0.93 seconds
Started Jul 21 06:00:44 PM PDT 24
Finished Jul 21 06:00:46 PM PDT 24
Peak memory 196140 kb
Host smart-02b941f8-78b0-4eb0-a9b8-2a6999fa578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690243461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.690243461
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.173624678
Short name T571
Test name
Test status
Simulation time 612440003 ps
CPU time 26.22 seconds
Started Jul 21 06:00:27 PM PDT 24
Finished Jul 21 06:00:54 PM PDT 24
Peak memory 195660 kb
Host smart-ab7d4d43-978c-4fc5-a8cd-fc134b246cba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173624678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.173624678
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.3908204841
Short name T501
Test name
Test status
Simulation time 64606026 ps
CPU time 0.94 seconds
Started Jul 21 06:00:40 PM PDT 24
Finished Jul 21 06:00:41 PM PDT 24
Peak memory 196824 kb
Host smart-5baf2a74-938f-4e22-b755-1121adae7bb4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908204841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.3908204841
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.1022985729
Short name T133
Test name
Test status
Simulation time 31223896 ps
CPU time 0.72 seconds
Started Jul 21 06:00:45 PM PDT 24
Finished Jul 21 06:00:47 PM PDT 24
Peak memory 195552 kb
Host smart-038fc568-b8bb-45f8-b08c-9814e241cfc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022985729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.1022985729
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.3900399929
Short name T380
Test name
Test status
Simulation time 68093898 ps
CPU time 2.87 seconds
Started Jul 21 06:00:36 PM PDT 24
Finished Jul 21 06:00:39 PM PDT 24
Peak memory 198300 kb
Host smart-47fac812-793c-4d2a-abe1-e75547d19f5f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900399929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.3900399929
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.3639513367
Short name T537
Test name
Test status
Simulation time 223391609 ps
CPU time 2.7 seconds
Started Jul 21 06:00:31 PM PDT 24
Finished Jul 21 06:00:35 PM PDT 24
Peak memory 198224 kb
Host smart-53d85c93-9806-45c8-a8cf-cb810fa33ecd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639513367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.3639513367
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.4043543799
Short name T115
Test name
Test status
Simulation time 50488997 ps
CPU time 1.14 seconds
Started Jul 21 06:00:46 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 196264 kb
Host smart-261dc5bf-8c6b-40fe-be68-efa89eed8000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043543799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.4043543799
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.1104742410
Short name T247
Test name
Test status
Simulation time 298586093 ps
CPU time 0.84 seconds
Started Jul 21 06:00:30 PM PDT 24
Finished Jul 21 06:00:31 PM PDT 24
Peak memory 195740 kb
Host smart-c8f9e6a9-a5ca-4f6d-93fd-b657137348b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104742410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.1104742410
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3500400893
Short name T381
Test name
Test status
Simulation time 1410705094 ps
CPU time 5.48 seconds
Started Jul 21 06:00:30 PM PDT 24
Finished Jul 21 06:00:36 PM PDT 24
Peak memory 198424 kb
Host smart-4c2d7e07-b16f-458d-bbe2-954d35d8ddd2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500400893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3500400893
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2157067337
Short name T555
Test name
Test status
Simulation time 1551671043 ps
CPU time 1.73 seconds
Started Jul 21 06:00:26 PM PDT 24
Finished Jul 21 06:00:29 PM PDT 24
Peak memory 197040 kb
Host smart-4fc0bb23-279b-4979-8d86-27051152e221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157067337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2157067337
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.4053176632
Short name T459
Test name
Test status
Simulation time 96546074 ps
CPU time 0.98 seconds
Started Jul 21 06:00:43 PM PDT 24
Finished Jul 21 06:00:45 PM PDT 24
Peak memory 195812 kb
Host smart-9ca67f9b-7381-4ea4-9de9-76f0e0bc2263
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053176632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.4053176632
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.951261744
Short name T165
Test name
Test status
Simulation time 31202714162 ps
CPU time 117.56 seconds
Started Jul 21 06:00:34 PM PDT 24
Finished Jul 21 06:02:32 PM PDT 24
Peak memory 198424 kb
Host smart-25c692c1-a50a-433d-9b90-eaf4a563ae52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951261744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.g
pio_stress_all.951261744
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_alert_test.157134907
Short name T578
Test name
Test status
Simulation time 51220891 ps
CPU time 0.58 seconds
Started Jul 21 06:00:33 PM PDT 24
Finished Jul 21 06:00:34 PM PDT 24
Peak memory 194208 kb
Host smart-ee5e24d1-cdc7-47fa-bcd7-72dec80a0058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157134907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.157134907
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.1025528642
Short name T567
Test name
Test status
Simulation time 39313861 ps
CPU time 0.88 seconds
Started Jul 21 06:00:40 PM PDT 24
Finished Jul 21 06:00:41 PM PDT 24
Peak memory 197492 kb
Host smart-0cab7f56-8058-4060-8f92-043888cb375a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025528642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.1025528642
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.465346651
Short name T26
Test name
Test status
Simulation time 3262712961 ps
CPU time 5 seconds
Started Jul 21 06:00:40 PM PDT 24
Finished Jul 21 06:00:46 PM PDT 24
Peak memory 196356 kb
Host smart-51f413fa-13df-4d1b-b182-a515b006b6a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465346651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stres
s.465346651
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3999985889
Short name T179
Test name
Test status
Simulation time 123071617 ps
CPU time 0.89 seconds
Started Jul 21 06:00:42 PM PDT 24
Finished Jul 21 06:00:44 PM PDT 24
Peak memory 196236 kb
Host smart-becc978e-ed4a-44eb-8a24-c76f232898db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999985889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3999985889
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.3273011362
Short name T301
Test name
Test status
Simulation time 106796315 ps
CPU time 1.12 seconds
Started Jul 21 06:00:42 PM PDT 24
Finished Jul 21 06:00:44 PM PDT 24
Peak memory 197056 kb
Host smart-67391a48-864b-46d9-9673-4bccab3c5caa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273011362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.3273011362
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.235406577
Short name T287
Test name
Test status
Simulation time 382574590 ps
CPU time 3.62 seconds
Started Jul 21 06:00:44 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 196704 kb
Host smart-0b1ce2d3-9122-465d-be85-92c89b564931
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235406577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.235406577
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1398507174
Short name T701
Test name
Test status
Simulation time 150994702 ps
CPU time 3.5 seconds
Started Jul 21 06:00:32 PM PDT 24
Finished Jul 21 06:00:36 PM PDT 24
Peak memory 197132 kb
Host smart-4fd23369-2c37-4de2-9664-5dbf68836e7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398507174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1398507174
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.4178802528
Short name T279
Test name
Test status
Simulation time 42385413 ps
CPU time 0.66 seconds
Started Jul 21 06:00:29 PM PDT 24
Finished Jul 21 06:00:31 PM PDT 24
Peak memory 195236 kb
Host smart-86e60bc9-a8e2-492b-8bc0-fc79d3acc860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178802528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.4178802528
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2209794488
Short name T266
Test name
Test status
Simulation time 114449724 ps
CPU time 1.24 seconds
Started Jul 21 06:00:31 PM PDT 24
Finished Jul 21 06:00:33 PM PDT 24
Peak memory 196752 kb
Host smart-dc1a46c2-6692-41bf-aa04-36318ca762ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209794488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2209794488
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.406040371
Short name T304
Test name
Test status
Simulation time 186649760 ps
CPU time 1.6 seconds
Started Jul 21 06:00:33 PM PDT 24
Finished Jul 21 06:00:35 PM PDT 24
Peak memory 198136 kb
Host smart-92224af5-59cb-4937-a1cc-57834360775e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406040371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.406040371
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2620381566
Short name T171
Test name
Test status
Simulation time 54975981 ps
CPU time 1.38 seconds
Started Jul 21 06:00:28 PM PDT 24
Finished Jul 21 06:00:30 PM PDT 24
Peak memory 198232 kb
Host smart-d0a2674a-4178-4c23-8232-54029c26c403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620381566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2620381566
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.3552405687
Short name T687
Test name
Test status
Simulation time 29640408 ps
CPU time 0.77 seconds
Started Jul 21 06:00:37 PM PDT 24
Finished Jul 21 06:00:39 PM PDT 24
Peak memory 194356 kb
Host smart-ff314183-8f68-4f26-b44c-0e378a360f36
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552405687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.3552405687
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.1213940119
Short name T4
Test name
Test status
Simulation time 72224130507 ps
CPU time 199.35 seconds
Started Jul 21 06:00:30 PM PDT 24
Finished Jul 21 06:03:50 PM PDT 24
Peak memory 198296 kb
Host smart-0f94dc9c-d189-4ecc-ace8-c33b63aca70c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213940119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.1213940119
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_alert_test.1917812869
Short name T258
Test name
Test status
Simulation time 28115310 ps
CPU time 0.58 seconds
Started Jul 21 06:00:43 PM PDT 24
Finished Jul 21 06:00:44 PM PDT 24
Peak memory 194812 kb
Host smart-b02dccda-1e15-4e82-99e0-f095eb4fa3f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917812869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.1917812869
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.214627904
Short name T172
Test name
Test status
Simulation time 115485288 ps
CPU time 0.8 seconds
Started Jul 21 06:00:42 PM PDT 24
Finished Jul 21 06:00:44 PM PDT 24
Peak memory 196760 kb
Host smart-940308a7-9528-4a9c-ac8b-00e4122c934c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214627904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.214627904
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.2561660018
Short name T506
Test name
Test status
Simulation time 1659922640 ps
CPU time 18.35 seconds
Started Jul 21 06:00:32 PM PDT 24
Finished Jul 21 06:00:51 PM PDT 24
Peak memory 196876 kb
Host smart-3bdcbd92-a1d1-4671-8d1c-cb26ae4f1451
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561660018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.2561660018
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.782212464
Short name T208
Test name
Test status
Simulation time 160538416 ps
CPU time 0.84 seconds
Started Jul 21 06:00:35 PM PDT 24
Finished Jul 21 06:00:37 PM PDT 24
Peak memory 196156 kb
Host smart-110cd2a9-fce1-495a-b328-7d0660a413ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782212464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.782212464
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2367726476
Short name T699
Test name
Test status
Simulation time 83443050 ps
CPU time 0.89 seconds
Started Jul 21 06:00:30 PM PDT 24
Finished Jul 21 06:00:31 PM PDT 24
Peak memory 195808 kb
Host smart-06e3ab80-be8b-425a-a7fa-37b1a027f6a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367726476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2367726476
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.4122854231
Short name T414
Test name
Test status
Simulation time 66058468 ps
CPU time 2.62 seconds
Started Jul 21 06:00:44 PM PDT 24
Finished Jul 21 06:00:47 PM PDT 24
Peak memory 198196 kb
Host smart-f597c9b4-f7d2-4276-9d9a-644b3768fb43
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122854231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.4122854231
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1104028189
Short name T614
Test name
Test status
Simulation time 358018986 ps
CPU time 2 seconds
Started Jul 21 06:00:29 PM PDT 24
Finished Jul 21 06:00:31 PM PDT 24
Peak memory 196372 kb
Host smart-a395bbff-be84-47e5-833d-05c17e0d4d9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104028189 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1104028189
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1224851761
Short name T559
Test name
Test status
Simulation time 91494912 ps
CPU time 0.82 seconds
Started Jul 21 06:00:32 PM PDT 24
Finished Jul 21 06:00:34 PM PDT 24
Peak memory 196384 kb
Host smart-1ff2c9e7-1b99-40f3-90b2-c9b12e4ed2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224851761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1224851761
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.2505920235
Short name T441
Test name
Test status
Simulation time 81552803 ps
CPU time 1.38 seconds
Started Jul 21 06:00:32 PM PDT 24
Finished Jul 21 06:00:34 PM PDT 24
Peak memory 197148 kb
Host smart-48519f38-143e-4c40-bfad-98e340fe5010
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505920235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.2505920235
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3005320919
Short name T629
Test name
Test status
Simulation time 3055659699 ps
CPU time 3.45 seconds
Started Jul 21 06:00:39 PM PDT 24
Finished Jul 21 06:00:43 PM PDT 24
Peak memory 198040 kb
Host smart-e6eee4c4-fc72-43c6-a00d-5d5fa18f54d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005320919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3005320919
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.462385223
Short name T253
Test name
Test status
Simulation time 164980576 ps
CPU time 1.6 seconds
Started Jul 21 06:00:41 PM PDT 24
Finished Jul 21 06:00:44 PM PDT 24
Peak memory 198208 kb
Host smart-1a635276-4c34-4612-a2ae-226f659eae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462385223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.462385223
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.398615575
Short name T553
Test name
Test status
Simulation time 24742800 ps
CPU time 0.75 seconds
Started Jul 21 06:00:39 PM PDT 24
Finished Jul 21 06:00:40 PM PDT 24
Peak memory 195412 kb
Host smart-600e6c86-c9da-4a9c-9300-b9d17877de99
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398615575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.398615575
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.3402618939
Short name T259
Test name
Test status
Simulation time 8776304232 ps
CPU time 32.63 seconds
Started Jul 21 06:00:29 PM PDT 24
Finished Jul 21 06:01:02 PM PDT 24
Peak memory 198360 kb
Host smart-36a38fda-d5d9-4d31-ac74-77898d662b83
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402618939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.3402618939
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1034977635
Short name T278
Test name
Test status
Simulation time 12644047 ps
CPU time 0.56 seconds
Started Jul 21 06:00:41 PM PDT 24
Finished Jul 21 06:00:43 PM PDT 24
Peak memory 194188 kb
Host smart-b2b4c4e8-753d-45a3-a0df-a398a2f51a57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034977635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1034977635
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.2516050794
Short name T349
Test name
Test status
Simulation time 31085984 ps
CPU time 0.95 seconds
Started Jul 21 06:00:33 PM PDT 24
Finished Jul 21 06:00:35 PM PDT 24
Peak memory 196272 kb
Host smart-e4e64c13-a7a6-45c5-93a7-f671681bf2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516050794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.2516050794
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1943646149
Short name T226
Test name
Test status
Simulation time 888499930 ps
CPU time 22.44 seconds
Started Jul 21 06:00:40 PM PDT 24
Finished Jul 21 06:01:03 PM PDT 24
Peak memory 195784 kb
Host smart-55314662-4766-4371-9358-ddcac93824c6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943646149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1943646149
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.2037285301
Short name T359
Test name
Test status
Simulation time 189028882 ps
CPU time 0.8 seconds
Started Jul 21 06:00:45 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 196772 kb
Host smart-37931d65-7bf8-4ac1-b599-e65146bced4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037285301 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2037285301
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2421972536
Short name T256
Test name
Test status
Simulation time 177300167 ps
CPU time 0.87 seconds
Started Jul 21 06:00:33 PM PDT 24
Finished Jul 21 06:00:34 PM PDT 24
Peak memory 195916 kb
Host smart-50967c5b-06d1-438b-be76-827afe74bb66
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421972536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2421972536
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3617758939
Short name T248
Test name
Test status
Simulation time 153862148 ps
CPU time 3.01 seconds
Started Jul 21 06:00:43 PM PDT 24
Finished Jul 21 06:00:47 PM PDT 24
Peak memory 198220 kb
Host smart-50c13e12-1691-4ca4-8364-fef08c8d3ab9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617758939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3617758939
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.320194587
Short name T590
Test name
Test status
Simulation time 125429885 ps
CPU time 2.1 seconds
Started Jul 21 06:00:39 PM PDT 24
Finished Jul 21 06:00:41 PM PDT 24
Peak memory 198332 kb
Host smart-76cc8ccf-3b66-43f1-845d-fbcbaec82e0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320194587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
320194587
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.996362934
Short name T72
Test name
Test status
Simulation time 105081606 ps
CPU time 1.09 seconds
Started Jul 21 06:00:28 PM PDT 24
Finished Jul 21 06:00:30 PM PDT 24
Peak memory 196344 kb
Host smart-c146e22f-c35f-4b10-a481-d69c1e1c6376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996362934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.996362934
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.2397116811
Short name T558
Test name
Test status
Simulation time 231619538 ps
CPU time 1.29 seconds
Started Jul 21 06:00:31 PM PDT 24
Finished Jul 21 06:00:34 PM PDT 24
Peak memory 198300 kb
Host smart-67297a44-7213-4b04-a6b1-988c356f5fb2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397116811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.2397116811
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2292079427
Short name T507
Test name
Test status
Simulation time 379578992 ps
CPU time 4.34 seconds
Started Jul 21 06:00:41 PM PDT 24
Finished Jul 21 06:00:46 PM PDT 24
Peak memory 198208 kb
Host smart-ebe9978a-7f2b-4d53-b074-a1342ccfa9b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292079427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2292079427
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2073701913
Short name T582
Test name
Test status
Simulation time 67703321 ps
CPU time 1.05 seconds
Started Jul 21 06:00:40 PM PDT 24
Finished Jul 21 06:00:41 PM PDT 24
Peak memory 196036 kb
Host smart-b2530a78-5c49-4b11-8c8e-b50a9b6f58bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073701913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2073701913
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1751527757
Short name T516
Test name
Test status
Simulation time 176170430 ps
CPU time 1 seconds
Started Jul 21 06:00:33 PM PDT 24
Finished Jul 21 06:00:34 PM PDT 24
Peak memory 196696 kb
Host smart-ef8d7e75-b9e5-4446-b930-f59e2cf43f87
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751527757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1751527757
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2995507109
Short name T427
Test name
Test status
Simulation time 14663688128 ps
CPU time 204.92 seconds
Started Jul 21 06:00:42 PM PDT 24
Finished Jul 21 06:04:09 PM PDT 24
Peak memory 198336 kb
Host smart-9730f683-15c2-4c83-a282-226b56ce8678
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995507109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2995507109
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_alert_test.45404340
Short name T394
Test name
Test status
Simulation time 34443571 ps
CPU time 0.57 seconds
Started Jul 21 06:00:34 PM PDT 24
Finished Jul 21 06:00:35 PM PDT 24
Peak memory 194420 kb
Host smart-fd3e505d-5d10-45d3-856a-1c93d4f7504a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45404340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.45404340
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.3491453373
Short name T468
Test name
Test status
Simulation time 19658407 ps
CPU time 0.64 seconds
Started Jul 21 06:00:38 PM PDT 24
Finished Jul 21 06:00:39 PM PDT 24
Peak memory 195012 kb
Host smart-0ffdc112-f9cc-4415-9bdb-68460ca12665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491453373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.3491453373
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1906016527
Short name T455
Test name
Test status
Simulation time 486421373 ps
CPU time 17.76 seconds
Started Jul 21 06:00:37 PM PDT 24
Finished Jul 21 06:00:55 PM PDT 24
Peak memory 195740 kb
Host smart-e563b7b6-33b6-4172-b8cb-ffced92f33a1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906016527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1906016527
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.1425892006
Short name T620
Test name
Test status
Simulation time 55865517 ps
CPU time 0.74 seconds
Started Jul 21 06:00:36 PM PDT 24
Finished Jul 21 06:00:37 PM PDT 24
Peak memory 195556 kb
Host smart-294905fb-9f02-49ce-933c-3fca4fe85928
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425892006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.1425892006
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1453713613
Short name T565
Test name
Test status
Simulation time 131236742 ps
CPU time 1.08 seconds
Started Jul 21 06:00:33 PM PDT 24
Finished Jul 21 06:00:35 PM PDT 24
Peak memory 196216 kb
Host smart-cec48f24-839b-40bc-92f1-d4c500bdefc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453713613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1453713613
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.292563152
Short name T513
Test name
Test status
Simulation time 74803418 ps
CPU time 3.29 seconds
Started Jul 21 06:00:35 PM PDT 24
Finished Jul 21 06:00:39 PM PDT 24
Peak memory 198180 kb
Host smart-a3b0221c-dab2-491a-b2a2-b1bf7369ae72
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292563152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.292563152
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2902199407
Short name T473
Test name
Test status
Simulation time 141296757 ps
CPU time 2.86 seconds
Started Jul 21 06:00:34 PM PDT 24
Finished Jul 21 06:00:38 PM PDT 24
Peak memory 197156 kb
Host smart-ecf3de1b-3ba3-4612-b7a8-9868a6de294d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902199407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2902199407
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2468504469
Short name T597
Test name
Test status
Simulation time 108731120 ps
CPU time 0.88 seconds
Started Jul 21 06:00:43 PM PDT 24
Finished Jul 21 06:00:45 PM PDT 24
Peak memory 197484 kb
Host smart-8f230398-b229-44ed-82ae-47400089c803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468504469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2468504469
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.888662032
Short name T520
Test name
Test status
Simulation time 148765362 ps
CPU time 1.4 seconds
Started Jul 21 06:00:36 PM PDT 24
Finished Jul 21 06:00:38 PM PDT 24
Peak memory 197300 kb
Host smart-a746c465-7af2-46b8-8495-7df1e8f83d8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888662032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.888662032
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.1765763731
Short name T6
Test name
Test status
Simulation time 5707189684 ps
CPU time 6.15 seconds
Started Jul 21 06:00:41 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 198304 kb
Host smart-cd02c18f-d0ff-402f-9e65-92eb5cd0f6e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765763731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.1765763731
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1300303743
Short name T538
Test name
Test status
Simulation time 240511215 ps
CPU time 0.92 seconds
Started Jul 21 06:00:45 PM PDT 24
Finished Jul 21 06:00:47 PM PDT 24
Peak memory 196676 kb
Host smart-1dd7688e-644d-4f5c-a48e-a52790c45f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300303743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1300303743
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.2820625136
Short name T639
Test name
Test status
Simulation time 580498814 ps
CPU time 0.99 seconds
Started Jul 21 06:00:36 PM PDT 24
Finished Jul 21 06:00:38 PM PDT 24
Peak memory 195932 kb
Host smart-9a20d2ff-aae0-47c2-a760-eb608a7952ca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820625136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.2820625136
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1927743027
Short name T8
Test name
Test status
Simulation time 11677264485 ps
CPU time 139.57 seconds
Started Jul 21 06:00:41 PM PDT 24
Finished Jul 21 06:03:02 PM PDT 24
Peak memory 198320 kb
Host smart-9daaaa03-a9a1-4aae-85f3-dfa8e00a11ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927743027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1927743027
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_alert_test.870399490
Short name T59
Test name
Test status
Simulation time 17637766 ps
CPU time 0.6 seconds
Started Jul 21 06:00:38 PM PDT 24
Finished Jul 21 06:00:39 PM PDT 24
Peak memory 195100 kb
Host smart-293a6c72-9a18-4bfb-9c30-1a342459bcb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870399490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.870399490
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3506790413
Short name T392
Test name
Test status
Simulation time 32161074 ps
CPU time 0.76 seconds
Started Jul 21 06:00:41 PM PDT 24
Finished Jul 21 06:00:43 PM PDT 24
Peak memory 195488 kb
Host smart-6dfada14-9a8d-47fa-8c16-9a66d3e5c870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506790413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3506790413
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.1708895813
Short name T149
Test name
Test status
Simulation time 954907144 ps
CPU time 4.14 seconds
Started Jul 21 06:00:43 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 196872 kb
Host smart-c263cc8f-4c52-4ba7-ab1f-89c3e28d7ecc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708895813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stre
ss.1708895813
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2261137138
Short name T525
Test name
Test status
Simulation time 142271036 ps
CPU time 0.81 seconds
Started Jul 21 06:00:49 PM PDT 24
Finished Jul 21 06:00:51 PM PDT 24
Peak memory 196356 kb
Host smart-26ccff03-aaa3-492d-b969-5e9a466a4c4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261137138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2261137138
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.52786436
Short name T154
Test name
Test status
Simulation time 286305932 ps
CPU time 1.5 seconds
Started Jul 21 06:00:45 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 198244 kb
Host smart-fb581b54-4eea-49f2-9baf-7d7e341aaab9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52786436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.52786436
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.3163852879
Short name T647
Test name
Test status
Simulation time 213904606 ps
CPU time 2.37 seconds
Started Jul 21 06:00:40 PM PDT 24
Finished Jul 21 06:00:43 PM PDT 24
Peak memory 198256 kb
Host smart-0389feb4-e7db-496e-946a-ca42003b2054
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163852879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.3163852879
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.3574803446
Short name T207
Test name
Test status
Simulation time 179479234 ps
CPU time 2.03 seconds
Started Jul 21 06:00:39 PM PDT 24
Finished Jul 21 06:00:41 PM PDT 24
Peak memory 197524 kb
Host smart-75c7a243-0ab4-4250-aafc-3b658b528e81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574803446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.3574803446
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.694803582
Short name T621
Test name
Test status
Simulation time 43750195 ps
CPU time 1.06 seconds
Started Jul 21 06:00:46 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 196276 kb
Host smart-4de3f4c6-9658-41a5-bfb8-5487f53f0655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694803582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.694803582
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.887114142
Short name T281
Test name
Test status
Simulation time 684869510 ps
CPU time 1.36 seconds
Started Jul 21 06:00:37 PM PDT 24
Finished Jul 21 06:00:39 PM PDT 24
Peak memory 195996 kb
Host smart-a97723d5-74dc-4fdf-88bc-4d6855d44537
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887114142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullup
_pulldown.887114142
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3090489081
Short name T640
Test name
Test status
Simulation time 60149906 ps
CPU time 2.79 seconds
Started Jul 21 06:00:48 PM PDT 24
Finished Jul 21 06:00:51 PM PDT 24
Peak memory 198268 kb
Host smart-eca5bfef-e413-40a4-85d2-03cccac82fd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090489081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3090489081
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1211858762
Short name T557
Test name
Test status
Simulation time 382320018 ps
CPU time 1.29 seconds
Started Jul 21 06:00:38 PM PDT 24
Finished Jul 21 06:00:40 PM PDT 24
Peak memory 196024 kb
Host smart-4f9e5ce7-f710-4525-9326-5164cf06df97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211858762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1211858762
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.1742180438
Short name T77
Test name
Test status
Simulation time 36033259 ps
CPU time 1.1 seconds
Started Jul 21 06:00:45 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 196412 kb
Host smart-21106c0f-12e8-4bdb-bbad-a5c06571a9b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742180438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.1742180438
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.669908061
Short name T260
Test name
Test status
Simulation time 6079997975 ps
CPU time 152.85 seconds
Started Jul 21 06:00:35 PM PDT 24
Finished Jul 21 06:03:08 PM PDT 24
Peak memory 198396 kb
Host smart-280809d4-10d6-493d-a840-ebe36d0e8327
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669908061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.669908061
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.2530368863
Short name T61
Test name
Test status
Simulation time 104978927675 ps
CPU time 1254.9 seconds
Started Jul 21 06:00:40 PM PDT 24
Finished Jul 21 06:21:36 PM PDT 24
Peak memory 198456 kb
Host smart-43f64fae-7c39-4322-b466-6e4360d3cd2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2530368863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.2530368863
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.3834194640
Short name T404
Test name
Test status
Simulation time 21163932 ps
CPU time 0.55 seconds
Started Jul 21 06:00:46 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 194260 kb
Host smart-79262985-69a5-4193-a62f-9ba3f9695f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834194640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.3834194640
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1119006928
Short name T332
Test name
Test status
Simulation time 49183617 ps
CPU time 0.91 seconds
Started Jul 21 06:00:45 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 196764 kb
Host smart-597b32de-f6af-473f-ba5e-6d901b14ac32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119006928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1119006928
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3811327884
Short name T192
Test name
Test status
Simulation time 906497701 ps
CPU time 22.8 seconds
Started Jul 21 06:00:45 PM PDT 24
Finished Jul 21 06:01:10 PM PDT 24
Peak memory 197196 kb
Host smart-c50af049-011e-4181-b6b1-fdb707c0e9f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811327884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3811327884
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.600513891
Short name T12
Test name
Test status
Simulation time 59534441 ps
CPU time 0.88 seconds
Started Jul 21 06:00:49 PM PDT 24
Finished Jul 21 06:00:51 PM PDT 24
Peak memory 196080 kb
Host smart-05c96ace-ad61-4b7b-902f-87e893a6e301
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600513891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.600513891
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1467793028
Short name T225
Test name
Test status
Simulation time 89952750 ps
CPU time 1.29 seconds
Started Jul 21 06:00:45 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 197420 kb
Host smart-cd761edc-1e54-4099-8c27-ff8c407b2709
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467793028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1467793028
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1694929098
Short name T116
Test name
Test status
Simulation time 51712747 ps
CPU time 1.91 seconds
Started Jul 21 06:00:50 PM PDT 24
Finished Jul 21 06:00:53 PM PDT 24
Peak memory 196556 kb
Host smart-4dcc12c3-1949-45a5-a3fd-bb4cdaf9cc6f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694929098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1694929098
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3451739578
Short name T478
Test name
Test status
Simulation time 36465017 ps
CPU time 1.21 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:00:55 PM PDT 24
Peak memory 196804 kb
Host smart-12929ac4-e412-423f-9680-2823ef386fb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451739578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3451739578
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1370517411
Short name T52
Test name
Test status
Simulation time 110312008 ps
CPU time 1.03 seconds
Started Jul 21 06:00:34 PM PDT 24
Finished Jul 21 06:00:36 PM PDT 24
Peak memory 196280 kb
Host smart-d3a3f5cb-f573-47d8-a74f-40521e7ab603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370517411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1370517411
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.1021643055
Short name T444
Test name
Test status
Simulation time 29617484 ps
CPU time 0.9 seconds
Started Jul 21 06:00:49 PM PDT 24
Finished Jul 21 06:00:51 PM PDT 24
Peak memory 196088 kb
Host smart-794c44e7-eb00-4c5a-b2f7-04ae70e13d3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021643055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.1021643055
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1408599066
Short name T662
Test name
Test status
Simulation time 1315794554 ps
CPU time 4.8 seconds
Started Jul 21 06:00:48 PM PDT 24
Finished Jul 21 06:00:53 PM PDT 24
Peak memory 198232 kb
Host smart-c498e51d-5184-4dfe-9305-92592fc174a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408599066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1408599066
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.1802139371
Short name T321
Test name
Test status
Simulation time 69981433 ps
CPU time 1.01 seconds
Started Jul 21 06:00:38 PM PDT 24
Finished Jul 21 06:00:40 PM PDT 24
Peak memory 196664 kb
Host smart-924ba604-a2c1-49ce-8e2b-74e55a46c9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802139371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.1802139371
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1066833692
Short name T268
Test name
Test status
Simulation time 260085118 ps
CPU time 1.33 seconds
Started Jul 21 06:00:46 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 197364 kb
Host smart-9fd4d451-3588-48ee-8ddf-36ff40249b0e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066833692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1066833692
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.2206439319
Short name T335
Test name
Test status
Simulation time 3109089961 ps
CPU time 76.05 seconds
Started Jul 21 06:00:50 PM PDT 24
Finished Jul 21 06:02:08 PM PDT 24
Peak memory 198472 kb
Host smart-83e16fce-6920-4228-a3b8-11e4e3523ed3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206439319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.2206439319
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2593601521
Short name T564
Test name
Test status
Simulation time 37295726 ps
CPU time 0.6 seconds
Started Jul 21 05:59:47 PM PDT 24
Finished Jul 21 05:59:49 PM PDT 24
Peak memory 194452 kb
Host smart-32ccd84b-6517-4eaa-9b39-2b1931a95ef6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593601521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2593601521
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.739456355
Short name T694
Test name
Test status
Simulation time 32451610 ps
CPU time 0.74 seconds
Started Jul 21 05:59:47 PM PDT 24
Finished Jul 21 05:59:49 PM PDT 24
Peak memory 195344 kb
Host smart-a6b052d5-f423-47b8-9fdd-cfc4af6a0504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739456355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.739456355
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.1644521558
Short name T388
Test name
Test status
Simulation time 219675698 ps
CPU time 7.77 seconds
Started Jul 21 05:59:43 PM PDT 24
Finished Jul 21 05:59:52 PM PDT 24
Peak memory 198076 kb
Host smart-f1196f17-b72f-4bb0-94cb-53666584f9fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644521558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.1644521558
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1494269423
Short name T131
Test name
Test status
Simulation time 48126339 ps
CPU time 0.89 seconds
Started Jul 21 05:59:52 PM PDT 24
Finished Jul 21 05:59:53 PM PDT 24
Peak memory 196788 kb
Host smart-28884378-f915-4596-994a-cb2e8ebf4714
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494269423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1494269423
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.1742293866
Short name T169
Test name
Test status
Simulation time 203800951 ps
CPU time 0.94 seconds
Started Jul 21 05:59:45 PM PDT 24
Finished Jul 21 05:59:47 PM PDT 24
Peak memory 196140 kb
Host smart-9a2f5dc9-3647-45ec-9f97-703b3d341542
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742293866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.1742293866
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3098097567
Short name T223
Test name
Test status
Simulation time 71469976 ps
CPU time 0.96 seconds
Started Jul 21 05:59:45 PM PDT 24
Finished Jul 21 05:59:47 PM PDT 24
Peak memory 196416 kb
Host smart-9583a92b-26d6-4f76-a134-592e987fc004
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098097567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3098097567
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2598173754
Short name T347
Test name
Test status
Simulation time 179837745 ps
CPU time 1.78 seconds
Started Jul 21 05:59:46 PM PDT 24
Finished Jul 21 05:59:49 PM PDT 24
Peak memory 196452 kb
Host smart-d266f3e8-4aba-4005-be0c-825443bfb485
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598173754 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2598173754
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.900928554
Short name T364
Test name
Test status
Simulation time 33793979 ps
CPU time 1.16 seconds
Started Jul 21 05:59:45 PM PDT 24
Finished Jul 21 05:59:48 PM PDT 24
Peak memory 197160 kb
Host smart-0fe806cd-3192-4614-8942-f0dd49f87419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900928554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.900928554
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.4220087537
Short name T652
Test name
Test status
Simulation time 23276935 ps
CPU time 0.76 seconds
Started Jul 21 05:59:43 PM PDT 24
Finished Jul 21 05:59:44 PM PDT 24
Peak memory 196244 kb
Host smart-58e05bd7-9859-446e-b339-dcd47ee49762
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220087537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.4220087537
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3770692412
Short name T276
Test name
Test status
Simulation time 136919459 ps
CPU time 6.19 seconds
Started Jul 21 05:59:50 PM PDT 24
Finished Jul 21 05:59:57 PM PDT 24
Peak memory 198376 kb
Host smart-d4492de6-17f5-4792-96a4-bbce18e742dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770692412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3770692412
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2157837240
Short name T51
Test name
Test status
Simulation time 304168126 ps
CPU time 0.9 seconds
Started Jul 21 05:59:43 PM PDT 24
Finished Jul 21 05:59:45 PM PDT 24
Peak memory 214212 kb
Host smart-1f899540-4c52-490d-9a42-ad8999a2bdb1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157837240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2157837240
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3486531914
Short name T708
Test name
Test status
Simulation time 57409265 ps
CPU time 1.14 seconds
Started Jul 21 05:59:45 PM PDT 24
Finished Jul 21 05:59:48 PM PDT 24
Peak memory 196728 kb
Host smart-7a05be14-727d-41a0-b99c-729e7037e052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486531914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3486531914
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1357294517
Short name T611
Test name
Test status
Simulation time 57230662 ps
CPU time 1.09 seconds
Started Jul 21 05:59:44 PM PDT 24
Finished Jul 21 05:59:46 PM PDT 24
Peak memory 195860 kb
Host smart-70eaa0ad-06ed-4d64-b855-48726606bd33
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357294517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1357294517
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.4088204268
Short name T395
Test name
Test status
Simulation time 3487630244 ps
CPU time 90.66 seconds
Started Jul 21 05:59:51 PM PDT 24
Finished Jul 21 06:01:22 PM PDT 24
Peak memory 198380 kb
Host smart-3f1a5d4b-3e8a-4449-b5ea-33d444c69cb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088204268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.4088204268
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2729823267
Short name T552
Test name
Test status
Simulation time 248824646133 ps
CPU time 2740.62 seconds
Started Jul 21 05:59:50 PM PDT 24
Finished Jul 21 06:45:32 PM PDT 24
Peak memory 198668 kb
Host smart-2373a4c8-8d3b-4fa5-b164-f2417880d0a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2729823267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2729823267
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.1599124725
Short name T580
Test name
Test status
Simulation time 36589772 ps
CPU time 0.59 seconds
Started Jul 21 06:00:42 PM PDT 24
Finished Jul 21 06:00:44 PM PDT 24
Peak memory 194108 kb
Host smart-b66cde6f-5c04-449a-8aba-d0aa89993cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599124725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.1599124725
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.997897101
Short name T397
Test name
Test status
Simulation time 183141504 ps
CPU time 0.78 seconds
Started Jul 21 06:00:49 PM PDT 24
Finished Jul 21 06:00:50 PM PDT 24
Peak memory 195416 kb
Host smart-c218cb37-0474-4a43-88d8-754dc87e1b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997897101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.997897101
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.793139514
Short name T187
Test name
Test status
Simulation time 2916781199 ps
CPU time 18.91 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:01:13 PM PDT 24
Peak memory 197264 kb
Host smart-dd6119af-0a55-4aa8-bc33-d3b62389044a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793139514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stres
s.793139514
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.2574246515
Short name T467
Test name
Test status
Simulation time 52790067 ps
CPU time 0.82 seconds
Started Jul 21 06:00:53 PM PDT 24
Finished Jul 21 06:00:56 PM PDT 24
Peak memory 195964 kb
Host smart-382f6814-7578-4f8c-82ea-6401c5ed8bc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574246515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.2574246515
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.3011074467
Short name T348
Test name
Test status
Simulation time 220090561 ps
CPU time 1.3 seconds
Started Jul 21 06:00:49 PM PDT 24
Finished Jul 21 06:00:51 PM PDT 24
Peak memory 196364 kb
Host smart-e9ac40a9-2973-4a52-9b5f-efd772d09f92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011074467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.3011074467
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.1734981150
Short name T556
Test name
Test status
Simulation time 322101915 ps
CPU time 3.55 seconds
Started Jul 21 06:00:47 PM PDT 24
Finished Jul 21 06:00:51 PM PDT 24
Peak memory 198228 kb
Host smart-928483ca-07d8-4431-8747-244c4746d79a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734981150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.1734981150
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1613786913
Short name T167
Test name
Test status
Simulation time 167533015 ps
CPU time 2.16 seconds
Started Jul 21 06:00:46 PM PDT 24
Finished Jul 21 06:00:50 PM PDT 24
Peak memory 196148 kb
Host smart-ee16aca3-f738-4716-ac8a-ef1532b8bf4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613786913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1613786913
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3720567482
Short name T294
Test name
Test status
Simulation time 40979177 ps
CPU time 0.68 seconds
Started Jul 21 06:00:49 PM PDT 24
Finished Jul 21 06:00:50 PM PDT 24
Peak memory 195500 kb
Host smart-b1acebc0-d0fb-4b6f-a7b4-6d6de8b9d352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720567482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3720567482
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.2373561648
Short name T591
Test name
Test status
Simulation time 22356344 ps
CPU time 0.68 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:00:59 PM PDT 24
Peak memory 195532 kb
Host smart-d08d565c-bfb9-4de7-a9cd-fab3e2aeacc8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373561648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.2373561648
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3925234377
Short name T7
Test name
Test status
Simulation time 810866463 ps
CPU time 5.8 seconds
Started Jul 21 06:00:46 PM PDT 24
Finished Jul 21 06:00:53 PM PDT 24
Peak memory 197928 kb
Host smart-d445219b-3be0-424d-bf13-e048e61bf6b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925234377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3925234377
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.606037426
Short name T690
Test name
Test status
Simulation time 115994300 ps
CPU time 1.21 seconds
Started Jul 21 06:00:51 PM PDT 24
Finished Jul 21 06:00:53 PM PDT 24
Peak memory 195968 kb
Host smart-c6317321-8a5c-431f-b33b-25a453763d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606037426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.606037426
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.4024990701
Short name T55
Test name
Test status
Simulation time 216082185 ps
CPU time 1.11 seconds
Started Jul 21 06:00:47 PM PDT 24
Finished Jul 21 06:00:49 PM PDT 24
Peak memory 195764 kb
Host smart-f7ad11c4-eeb8-4e4f-a5ae-bf82df5fba78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024990701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.4024990701
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.1910927684
Short name T627
Test name
Test status
Simulation time 7753345054 ps
CPU time 204.01 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:04:18 PM PDT 24
Peak memory 198320 kb
Host smart-d82b96cd-aa9f-4085-ba95-4d723d2dd4e2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910927684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.1910927684
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_alert_test.4245484632
Short name T433
Test name
Test status
Simulation time 64519882 ps
CPU time 0.59 seconds
Started Jul 21 06:00:54 PM PDT 24
Finished Jul 21 06:00:57 PM PDT 24
Peak memory 192868 kb
Host smart-39c4f85c-361f-46ba-b155-ecb9dad211fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245484632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.4245484632
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2746553174
Short name T68
Test name
Test status
Simulation time 44352939 ps
CPU time 0.85 seconds
Started Jul 21 06:00:49 PM PDT 24
Finished Jul 21 06:00:51 PM PDT 24
Peak memory 196720 kb
Host smart-c776d4fe-7582-43fc-9903-3bee9bd7383d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746553174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2746553174
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2497848621
Short name T705
Test name
Test status
Simulation time 3064530919 ps
CPU time 24.38 seconds
Started Jul 21 06:00:47 PM PDT 24
Finished Jul 21 06:01:13 PM PDT 24
Peak memory 197240 kb
Host smart-e88e0941-d133-4e89-8f86-ff51f9ac6866
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497848621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2497848621
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.3744196164
Short name T254
Test name
Test status
Simulation time 70468165 ps
CPU time 0.99 seconds
Started Jul 21 06:00:49 PM PDT 24
Finished Jul 21 06:00:50 PM PDT 24
Peak memory 196800 kb
Host smart-3131695f-2c43-4d32-be2e-fe95133e464b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744196164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.3744196164
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.3125535254
Short name T273
Test name
Test status
Simulation time 339085708 ps
CPU time 1.1 seconds
Started Jul 21 06:00:54 PM PDT 24
Finished Jul 21 06:00:57 PM PDT 24
Peak memory 196188 kb
Host smart-21ca092e-7ef7-4d70-bfba-12049c8dff03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125535254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.3125535254
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.267577878
Short name T377
Test name
Test status
Simulation time 87826636 ps
CPU time 3.16 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:00:57 PM PDT 24
Peak memory 198164 kb
Host smart-3f07a563-4173-42be-88fc-bfb758e30c04
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267577878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.gpio_intr_with_filter_rand_intr_event.267577878
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.1879603214
Short name T166
Test name
Test status
Simulation time 205486273 ps
CPU time 2.96 seconds
Started Jul 21 06:00:50 PM PDT 24
Finished Jul 21 06:00:54 PM PDT 24
Peak memory 197296 kb
Host smart-0cecbcc2-8ed4-45e6-9923-7d54326f870a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879603214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.1879603214
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.1249946688
Short name T475
Test name
Test status
Simulation time 27316097 ps
CPU time 0.79 seconds
Started Jul 21 06:00:53 PM PDT 24
Finished Jul 21 06:00:57 PM PDT 24
Peak memory 196404 kb
Host smart-7bbc6946-e76d-43b3-9871-8503421fa305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249946688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.1249946688
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.694583779
Short name T54
Test name
Test status
Simulation time 43436379 ps
CPU time 0.94 seconds
Started Jul 21 06:00:46 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 196184 kb
Host smart-8afebcb6-fa85-4942-8da9-822360b5cc97
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694583779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullup
_pulldown.694583779
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.3401234519
Short name T448
Test name
Test status
Simulation time 1023967184 ps
CPU time 2.79 seconds
Started Jul 21 06:00:48 PM PDT 24
Finished Jul 21 06:00:51 PM PDT 24
Peak memory 198200 kb
Host smart-c59a8ec6-b7f4-42c7-9163-628238075732
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401234519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.3401234519
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.2505860975
Short name T449
Test name
Test status
Simulation time 834987677 ps
CPU time 1.16 seconds
Started Jul 21 06:00:50 PM PDT 24
Finished Jul 21 06:00:53 PM PDT 24
Peak memory 195840 kb
Host smart-5e0c4762-0d81-4bf8-9f68-c72b275ee27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505860975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.2505860975
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3675831397
Short name T430
Test name
Test status
Simulation time 229471286 ps
CPU time 0.93 seconds
Started Jul 21 06:00:49 PM PDT 24
Finished Jul 21 06:00:51 PM PDT 24
Peak memory 195592 kb
Host smart-16feedc0-d924-4060-85fe-33fd9508295f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675831397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3675831397
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.716976968
Short name T331
Test name
Test status
Simulation time 69988042676 ps
CPU time 230.41 seconds
Started Jul 21 06:00:50 PM PDT 24
Finished Jul 21 06:04:41 PM PDT 24
Peak memory 198348 kb
Host smart-d6dd4ffe-4b1e-4ee6-97ae-15a50014a5c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716976968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.716976968
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2109659364
Short name T64
Test name
Test status
Simulation time 107732610773 ps
CPU time 1951.5 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:33:25 PM PDT 24
Peak memory 198508 kb
Host smart-fa8a89d5-2333-4b2f-b72b-73d20f5e42c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2109659364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2109659364
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2027591834
Short name T75
Test name
Test status
Simulation time 14307413 ps
CPU time 0.58 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:00:55 PM PDT 24
Peak memory 194188 kb
Host smart-5b3f1ff9-416c-43ec-98b8-bf6645fe79a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027591834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2027591834
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.1606799039
Short name T252
Test name
Test status
Simulation time 175628964 ps
CPU time 0.87 seconds
Started Jul 21 06:00:53 PM PDT 24
Finished Jul 21 06:00:57 PM PDT 24
Peak memory 195656 kb
Host smart-0c537b86-3960-4a8d-ad9e-0abe80fa10fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606799039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.1606799039
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.756314395
Short name T654
Test name
Test status
Simulation time 938751145 ps
CPU time 24.58 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:01:19 PM PDT 24
Peak memory 197336 kb
Host smart-010e3969-b85a-40b0-a9c6-7bf08810a25a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756314395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stres
s.756314395
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.585501296
Short name T664
Test name
Test status
Simulation time 29212873 ps
CPU time 0.64 seconds
Started Jul 21 06:00:48 PM PDT 24
Finished Jul 21 06:00:50 PM PDT 24
Peak memory 194712 kb
Host smart-1103c2ee-91ac-4280-8a3f-a558afe6ba56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585501296 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.585501296
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.2666189151
Short name T660
Test name
Test status
Simulation time 98327652 ps
CPU time 1.37 seconds
Started Jul 21 06:00:49 PM PDT 24
Finished Jul 21 06:00:51 PM PDT 24
Peak memory 197212 kb
Host smart-8f3ac04d-9521-4567-ba3b-200a26a47b89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666189151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.2666189151
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2122796654
Short name T390
Test name
Test status
Simulation time 78127147 ps
CPU time 2.98 seconds
Started Jul 21 06:00:51 PM PDT 24
Finished Jul 21 06:00:56 PM PDT 24
Peak memory 198336 kb
Host smart-b988057a-06e1-431b-93a9-a74d7d73134e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122796654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2122796654
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.1116244543
Short name T203
Test name
Test status
Simulation time 66772320 ps
CPU time 2.08 seconds
Started Jul 21 06:00:51 PM PDT 24
Finished Jul 21 06:00:55 PM PDT 24
Peak memory 198292 kb
Host smart-d3a48b3a-6128-416b-a8da-94ad67173a47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116244543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.1116244543
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3397520847
Short name T679
Test name
Test status
Simulation time 201513961 ps
CPU time 1.12 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:00:56 PM PDT 24
Peak memory 196208 kb
Host smart-d52ab826-92f6-45a0-bbf8-44bf587b3976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397520847 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3397520847
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1025493467
Short name T202
Test name
Test status
Simulation time 64954445 ps
CPU time 0.72 seconds
Started Jul 21 06:00:54 PM PDT 24
Finished Jul 21 06:00:58 PM PDT 24
Peak memory 196316 kb
Host smart-e7cfffc8-babc-4490-8018-1bbf90aa47dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025493467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1025493467
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.4069104092
Short name T220
Test name
Test status
Simulation time 117729046 ps
CPU time 5.68 seconds
Started Jul 21 06:00:54 PM PDT 24
Finished Jul 21 06:01:02 PM PDT 24
Peak memory 198144 kb
Host smart-3ee244f8-29a8-4c5f-8152-c912df61062a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069104092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.4069104092
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2863913540
Short name T246
Test name
Test status
Simulation time 55500040 ps
CPU time 1.1 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:00:56 PM PDT 24
Peak memory 195744 kb
Host smart-302633a6-8fea-4236-b545-e3d05966b8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863913540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2863913540
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1123241059
Short name T243
Test name
Test status
Simulation time 44631268 ps
CPU time 1.21 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:00:56 PM PDT 24
Peak memory 196812 kb
Host smart-c3081d05-f277-4423-93ec-67170f070fb7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123241059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1123241059
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.4209042268
Short name T215
Test name
Test status
Simulation time 3841023611 ps
CPU time 56.01 seconds
Started Jul 21 06:00:50 PM PDT 24
Finished Jul 21 06:01:47 PM PDT 24
Peak memory 198364 kb
Host smart-56779395-c26b-43f1-925f-762cddcbe788
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209042268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.4209042268
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_alert_test.4069456029
Short name T24
Test name
Test status
Simulation time 23568102 ps
CPU time 0.59 seconds
Started Jul 21 06:01:05 PM PDT 24
Finished Jul 21 06:01:07 PM PDT 24
Peak memory 194844 kb
Host smart-5ded5910-3a84-460b-a990-9438bace4f4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069456029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.4069456029
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.2837602801
Short name T581
Test name
Test status
Simulation time 28034576 ps
CPU time 0.85 seconds
Started Jul 21 06:00:53 PM PDT 24
Finished Jul 21 06:00:56 PM PDT 24
Peak memory 195732 kb
Host smart-f8223507-1b11-4957-97e8-19c936044f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837602801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.2837602801
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.3846370124
Short name T269
Test name
Test status
Simulation time 3993702550 ps
CPU time 26.24 seconds
Started Jul 21 06:00:51 PM PDT 24
Finished Jul 21 06:01:19 PM PDT 24
Peak memory 196860 kb
Host smart-d859d047-ca26-4757-bf95-21118c65cfc2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846370124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.3846370124
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3060245839
Short name T684
Test name
Test status
Simulation time 117307683 ps
CPU time 0.71 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:00:59 PM PDT 24
Peak memory 194956 kb
Host smart-f63926fd-ae30-4f8d-874b-b8fdd788324a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060245839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3060245839
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.1100869037
Short name T700
Test name
Test status
Simulation time 299959364 ps
CPU time 1.3 seconds
Started Jul 21 06:00:47 PM PDT 24
Finished Jul 21 06:00:50 PM PDT 24
Peak memory 198268 kb
Host smart-ffde5f07-08ca-4a45-bb4f-9db02e01eb11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100869037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.1100869037
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3364046671
Short name T648
Test name
Test status
Simulation time 138674016 ps
CPU time 2.67 seconds
Started Jul 21 06:00:53 PM PDT 24
Finished Jul 21 06:00:58 PM PDT 24
Peak memory 198236 kb
Host smart-ab974cc9-7669-4972-94ab-819f687d21cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364046671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3364046671
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.1593951236
Short name T325
Test name
Test status
Simulation time 42119443 ps
CPU time 1.17 seconds
Started Jul 21 06:00:51 PM PDT 24
Finished Jul 21 06:00:54 PM PDT 24
Peak memory 196508 kb
Host smart-17cc768b-559f-4f67-8e0a-ab755b92efc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593951236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger
.1593951236
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.275263080
Short name T382
Test name
Test status
Simulation time 131409169 ps
CPU time 0.91 seconds
Started Jul 21 06:00:54 PM PDT 24
Finished Jul 21 06:01:01 PM PDT 24
Peak memory 196140 kb
Host smart-9b56c2ac-328d-40d8-bb0c-40d64d10f76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275263080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.275263080
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.136371295
Short name T362
Test name
Test status
Simulation time 30746932 ps
CPU time 0.84 seconds
Started Jul 21 06:00:55 PM PDT 24
Finished Jul 21 06:00:59 PM PDT 24
Peak memory 197612 kb
Host smart-83f73922-9285-4958-93af-e103264ef140
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136371295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullup
_pulldown.136371295
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.409058467
Short name T1
Test name
Test status
Simulation time 376158960 ps
CPU time 2.46 seconds
Started Jul 21 06:00:53 PM PDT 24
Finished Jul 21 06:00:58 PM PDT 24
Peak memory 198264 kb
Host smart-d165b109-5747-432d-b0ed-8c0f8bbe0ec0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409058467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.409058467
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3056538343
Short name T470
Test name
Test status
Simulation time 112521734 ps
CPU time 0.83 seconds
Started Jul 21 06:00:54 PM PDT 24
Finished Jul 21 06:00:57 PM PDT 24
Peak memory 196560 kb
Host smart-111e41de-99cb-4cb1-a65e-54655d3fd422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056538343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3056538343
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.3333633205
Short name T703
Test name
Test status
Simulation time 136644649 ps
CPU time 1.02 seconds
Started Jul 21 06:00:49 PM PDT 24
Finished Jul 21 06:00:51 PM PDT 24
Peak memory 195804 kb
Host smart-b2d5278b-9b0a-413d-b387-9496fe72b4e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333633205 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.3333633205
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.4124096698
Short name T505
Test name
Test status
Simulation time 1069632510 ps
CPU time 23.28 seconds
Started Jul 21 06:00:51 PM PDT 24
Finished Jul 21 06:01:15 PM PDT 24
Peak memory 198216 kb
Host smart-56c738cd-acf0-450c-973d-556300faa5d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124096698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.4124096698
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_alert_test.4048256298
Short name T135
Test name
Test status
Simulation time 19580268 ps
CPU time 0.59 seconds
Started Jul 21 06:00:49 PM PDT 24
Finished Jul 21 06:00:51 PM PDT 24
Peak memory 194388 kb
Host smart-8b46d098-af54-46cf-b722-68dff3529ad4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048256298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.4048256298
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.41322428
Short name T145
Test name
Test status
Simulation time 40448022 ps
CPU time 0.77 seconds
Started Jul 21 06:00:55 PM PDT 24
Finished Jul 21 06:01:06 PM PDT 24
Peak memory 195676 kb
Host smart-987a060a-9007-4f1d-9442-20c4e81a9832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41322428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.41322428
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.4203324203
Short name T460
Test name
Test status
Simulation time 778822651 ps
CPU time 21.78 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:01:16 PM PDT 24
Peak memory 197144 kb
Host smart-f1f645e1-ab3b-4a28-bfcb-0f9fcfbf784e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203324203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.4203324203
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2796558509
Short name T439
Test name
Test status
Simulation time 69818557 ps
CPU time 0.88 seconds
Started Jul 21 06:00:55 PM PDT 24
Finished Jul 21 06:00:59 PM PDT 24
Peak memory 196092 kb
Host smart-d447cd69-0670-471c-9a30-52cf6d3de89a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796558509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2796558509
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1533116412
Short name T241
Test name
Test status
Simulation time 136593871 ps
CPU time 1.08 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:00:55 PM PDT 24
Peak memory 196024 kb
Host smart-59d8e608-057a-40b6-b330-19a34c856d7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533116412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1533116412
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.1115410352
Short name T151
Test name
Test status
Simulation time 99515154 ps
CPU time 1.09 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:00:55 PM PDT 24
Peak memory 196652 kb
Host smart-fd9094d0-d50e-4190-bab8-50ed19b869d7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115410352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.1115410352
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.701780015
Short name T229
Test name
Test status
Simulation time 155778688 ps
CPU time 2.51 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:00:56 PM PDT 24
Peak memory 198256 kb
Host smart-c10af116-a1b0-429e-9916-f39defe1199a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701780015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
701780015
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3802964075
Short name T261
Test name
Test status
Simulation time 127874219 ps
CPU time 1.25 seconds
Started Jul 21 06:00:51 PM PDT 24
Finished Jul 21 06:00:55 PM PDT 24
Peak memory 197320 kb
Host smart-06597c7f-879c-4166-bdb5-90af8471ff3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802964075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3802964075
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1887187504
Short name T535
Test name
Test status
Simulation time 67795188 ps
CPU time 0.84 seconds
Started Jul 21 06:00:55 PM PDT 24
Finished Jul 21 06:00:58 PM PDT 24
Peak memory 197568 kb
Host smart-8eb62698-610f-4be1-8ffa-90c51edf0230
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887187504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1887187504
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2717368084
Short name T125
Test name
Test status
Simulation time 331449948 ps
CPU time 3.98 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:00:58 PM PDT 24
Peak memory 198232 kb
Host smart-303b3854-ec9c-42f9-9dac-f35911591796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717368084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2717368084
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.691816897
Short name T315
Test name
Test status
Simulation time 331011581 ps
CPU time 1.49 seconds
Started Jul 21 06:00:52 PM PDT 24
Finished Jul 21 06:00:56 PM PDT 24
Peak memory 197172 kb
Host smart-88510b50-9f33-4de0-8c49-26aadbd521ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691816897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.691816897
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.4186847056
Short name T267
Test name
Test status
Simulation time 160528632 ps
CPU time 0.88 seconds
Started Jul 21 06:00:50 PM PDT 24
Finished Jul 21 06:00:52 PM PDT 24
Peak memory 196656 kb
Host smart-3a160935-a449-4e5c-9a56-7ededc61e7ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186847056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.4186847056
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.773731873
Short name T136
Test name
Test status
Simulation time 7950918683 ps
CPU time 105.49 seconds
Started Jul 21 06:00:55 PM PDT 24
Finished Jul 21 06:02:43 PM PDT 24
Peak memory 198412 kb
Host smart-6acb81cd-4d15-4617-a3ce-ae42def82c70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773731873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.773731873
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3036309864
Short name T469
Test name
Test status
Simulation time 32875605 ps
CPU time 0.53 seconds
Started Jul 21 06:00:56 PM PDT 24
Finished Jul 21 06:00:59 PM PDT 24
Peak memory 194188 kb
Host smart-e6f94a8f-a854-4ede-b10c-d3b0591ab3dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036309864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3036309864
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2043169993
Short name T123
Test name
Test status
Simulation time 305946392 ps
CPU time 0.82 seconds
Started Jul 21 06:00:50 PM PDT 24
Finished Jul 21 06:00:52 PM PDT 24
Peak memory 195492 kb
Host smart-6fc6dc68-44a9-42c7-8d18-c529ada1e51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043169993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2043169993
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2723114432
Short name T492
Test name
Test status
Simulation time 386839214 ps
CPU time 11.15 seconds
Started Jul 21 06:00:51 PM PDT 24
Finished Jul 21 06:01:04 PM PDT 24
Peak memory 195764 kb
Host smart-27c1e942-6897-45c2-9d12-5da2e1041d7b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723114432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2723114432
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.2993538535
Short name T385
Test name
Test status
Simulation time 59151875 ps
CPU time 0.72 seconds
Started Jul 21 06:01:01 PM PDT 24
Finished Jul 21 06:01:02 PM PDT 24
Peak memory 195192 kb
Host smart-62f0e791-b8a7-4c5d-88e6-2d7f0ba273db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993538535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.2993538535
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.1723959523
Short name T550
Test name
Test status
Simulation time 53755076 ps
CPU time 0.63 seconds
Started Jul 21 06:00:51 PM PDT 24
Finished Jul 21 06:00:54 PM PDT 24
Peak memory 195172 kb
Host smart-aa17780e-dd78-473c-a150-423c59326eb9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723959523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.1723959523
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.1948305071
Short name T238
Test name
Test status
Simulation time 224632074 ps
CPU time 1.96 seconds
Started Jul 21 06:00:50 PM PDT 24
Finished Jul 21 06:00:54 PM PDT 24
Peak memory 198344 kb
Host smart-93426500-b08e-49a4-962b-868afd64e5d9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948305071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.1948305071
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1421604108
Short name T536
Test name
Test status
Simulation time 1235008991 ps
CPU time 2.71 seconds
Started Jul 21 06:00:53 PM PDT 24
Finished Jul 21 06:00:59 PM PDT 24
Peak memory 197468 kb
Host smart-a53306ef-7134-4beb-a0ca-e1cba77cbe0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421604108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1421604108
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3766323474
Short name T416
Test name
Test status
Simulation time 99050172 ps
CPU time 0.61 seconds
Started Jul 21 06:00:51 PM PDT 24
Finished Jul 21 06:00:53 PM PDT 24
Peak memory 194440 kb
Host smart-592f1275-fceb-4ab8-9b32-f60ef2f38843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766323474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3766323474
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.939712335
Short name T630
Test name
Test status
Simulation time 99605297 ps
CPU time 1.02 seconds
Started Jul 21 06:00:53 PM PDT 24
Finished Jul 21 06:00:57 PM PDT 24
Peak memory 196972 kb
Host smart-9480157f-0ab0-44df-a012-8fa96741030e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939712335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.939712335
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.150397380
Short name T464
Test name
Test status
Simulation time 123480816 ps
CPU time 5.75 seconds
Started Jul 21 06:00:59 PM PDT 24
Finished Jul 21 06:01:05 PM PDT 24
Peak memory 196512 kb
Host smart-73bfa675-ee68-47cc-8a6e-aa22e9e40467
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150397380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ran
dom_long_reg_writes_reg_reads.150397380
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2783113698
Short name T249
Test name
Test status
Simulation time 137901718 ps
CPU time 1.16 seconds
Started Jul 21 06:00:55 PM PDT 24
Finished Jul 21 06:00:58 PM PDT 24
Peak memory 196028 kb
Host smart-6d61cbfe-21db-473e-ad9a-93cce343345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783113698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2783113698
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.2522651702
Short name T342
Test name
Test status
Simulation time 206644697 ps
CPU time 0.93 seconds
Started Jul 21 06:00:54 PM PDT 24
Finished Jul 21 06:00:58 PM PDT 24
Peak memory 196068 kb
Host smart-505d9ca7-df7d-4d12-ba92-eb8c7a041ae1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522651702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.2522651702
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1355467894
Short name T379
Test name
Test status
Simulation time 17116333856 ps
CPU time 117 seconds
Started Jul 21 06:00:55 PM PDT 24
Finished Jul 21 06:02:54 PM PDT 24
Peak memory 198340 kb
Host smart-cedb1b87-7515-4e77-8ecd-b1bc330efaca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355467894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1355467894
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_alert_test.1701398788
Short name T409
Test name
Test status
Simulation time 39639235 ps
CPU time 0.59 seconds
Started Jul 21 06:00:56 PM PDT 24
Finished Jul 21 06:00:59 PM PDT 24
Peak memory 194160 kb
Host smart-55e7da3b-24ae-4a9b-b09b-f492dd9a906a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701398788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.1701398788
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3004203390
Short name T285
Test name
Test status
Simulation time 63591044 ps
CPU time 0.65 seconds
Started Jul 21 06:00:56 PM PDT 24
Finished Jul 21 06:00:59 PM PDT 24
Peak memory 194160 kb
Host smart-d8dce613-c8b7-4930-9584-c9516d3e0729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004203390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3004203390
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2816527030
Short name T683
Test name
Test status
Simulation time 1178773123 ps
CPU time 17.99 seconds
Started Jul 21 06:00:54 PM PDT 24
Finished Jul 21 06:01:15 PM PDT 24
Peak memory 197400 kb
Host smart-b3339b80-f122-49ce-a89f-01410f1ee127
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816527030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2816527030
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.3317613314
Short name T9
Test name
Test status
Simulation time 67246365 ps
CPU time 0.88 seconds
Started Jul 21 06:00:56 PM PDT 24
Finished Jul 21 06:00:59 PM PDT 24
Peak memory 196388 kb
Host smart-480211c1-99e2-45fd-a86b-3ad158ebcdb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317613314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.3317613314
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1820812637
Short name T263
Test name
Test status
Simulation time 202395987 ps
CPU time 1.26 seconds
Started Jul 21 06:00:54 PM PDT 24
Finished Jul 21 06:00:58 PM PDT 24
Peak memory 196072 kb
Host smart-412090ca-da3e-4768-a693-12a3456174ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820812637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1820812637
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.376262061
Short name T350
Test name
Test status
Simulation time 23063860 ps
CPU time 1 seconds
Started Jul 21 06:00:56 PM PDT 24
Finished Jul 21 06:00:59 PM PDT 24
Peak memory 196584 kb
Host smart-6007fcff-be77-4427-8a9a-4f05518b9206
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376262061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.376262061
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.3886247900
Short name T110
Test name
Test status
Simulation time 49840910 ps
CPU time 1.58 seconds
Started Jul 21 06:00:53 PM PDT 24
Finished Jul 21 06:00:58 PM PDT 24
Peak memory 196284 kb
Host smart-68370c75-b6df-4c92-ae42-d4b4ba77c605
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886247900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.3886247900
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2800667898
Short name T702
Test name
Test status
Simulation time 161096354 ps
CPU time 1.06 seconds
Started Jul 21 06:00:55 PM PDT 24
Finished Jul 21 06:00:59 PM PDT 24
Peak memory 196876 kb
Host smart-0cf49f00-c20f-472e-8cc7-29c7d933de95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800667898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2800667898
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2514468588
Short name T599
Test name
Test status
Simulation time 54511844 ps
CPU time 0.89 seconds
Started Jul 21 06:00:59 PM PDT 24
Finished Jul 21 06:01:01 PM PDT 24
Peak memory 197544 kb
Host smart-b08103f0-6ae1-4f7c-b5b0-43cdde81d8dc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514468588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2514468588
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3731058428
Short name T632
Test name
Test status
Simulation time 347357696 ps
CPU time 3.3 seconds
Started Jul 21 06:00:53 PM PDT 24
Finished Jul 21 06:01:00 PM PDT 24
Peak memory 198208 kb
Host smart-cd34a5d7-11e8-40ac-99c2-a857c2492fbf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731058428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3731058428
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3885408712
Short name T126
Test name
Test status
Simulation time 51102830 ps
CPU time 1.07 seconds
Started Jul 21 06:01:02 PM PDT 24
Finished Jul 21 06:01:04 PM PDT 24
Peak memory 195708 kb
Host smart-7867f15c-f0e5-4584-b0c8-01dd21292a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885408712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3885408712
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.1453627771
Short name T685
Test name
Test status
Simulation time 81955148 ps
CPU time 1.04 seconds
Started Jul 21 06:00:59 PM PDT 24
Finished Jul 21 06:01:01 PM PDT 24
Peak memory 195940 kb
Host smart-90b11c69-e5fa-4ab8-9cc8-b45a0d2a073f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453627771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.1453627771
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.2006387510
Short name T354
Test name
Test status
Simulation time 1650380314 ps
CPU time 22.7 seconds
Started Jul 21 06:00:56 PM PDT 24
Finished Jul 21 06:01:21 PM PDT 24
Peak memory 198340 kb
Host smart-37901cbd-b08c-4d81-b4eb-9c45c09095b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006387510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.2006387510
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.3951802245
Short name T706
Test name
Test status
Simulation time 73994802148 ps
CPU time 1984.22 seconds
Started Jul 21 06:00:59 PM PDT 24
Finished Jul 21 06:34:04 PM PDT 24
Peak memory 198476 kb
Host smart-416d064d-dd10-4d7e-98ab-deeb7726d8f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3951802245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.3951802245
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.2214670803
Short name T413
Test name
Test status
Simulation time 16769456 ps
CPU time 0.57 seconds
Started Jul 21 06:00:54 PM PDT 24
Finished Jul 21 06:00:57 PM PDT 24
Peak memory 194880 kb
Host smart-0f2071ee-0991-4728-899e-28e0e0e99411
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214670803 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.2214670803
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.3287593652
Short name T573
Test name
Test status
Simulation time 42436297 ps
CPU time 0.63 seconds
Started Jul 21 06:01:02 PM PDT 24
Finished Jul 21 06:01:04 PM PDT 24
Peak memory 194956 kb
Host smart-a503175e-4cb8-49bf-bf55-495970b8316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287593652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.3287593652
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.957192086
Short name T569
Test name
Test status
Simulation time 2429921402 ps
CPU time 21.55 seconds
Started Jul 21 06:00:58 PM PDT 24
Finished Jul 21 06:01:21 PM PDT 24
Peak memory 197220 kb
Host smart-e2e8e34b-39cb-4d69-a22a-5f7d11a3d118
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957192086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.957192086
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.1961104387
Short name T650
Test name
Test status
Simulation time 70492585 ps
CPU time 0.97 seconds
Started Jul 21 06:01:18 PM PDT 24
Finished Jul 21 06:01:19 PM PDT 24
Peak memory 197932 kb
Host smart-f6469eec-3dce-4b58-b6d6-cb221568b68d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961104387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.1961104387
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1086343853
Short name T583
Test name
Test status
Simulation time 59128690 ps
CPU time 0.99 seconds
Started Jul 21 06:01:10 PM PDT 24
Finished Jul 21 06:01:12 PM PDT 24
Peak memory 197100 kb
Host smart-1a3e3143-b3f1-4933-b892-9a0271f8d3a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086343853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1086343853
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.2776725307
Short name T707
Test name
Test status
Simulation time 100071420 ps
CPU time 1.29 seconds
Started Jul 21 06:00:54 PM PDT 24
Finished Jul 21 06:00:58 PM PDT 24
Peak memory 197024 kb
Host smart-7a8e8782-075b-449f-8653-2f2fac00bb9d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776725307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.gpio_intr_with_filter_rand_intr_event.2776725307
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.660659055
Short name T576
Test name
Test status
Simulation time 75771626 ps
CPU time 2.45 seconds
Started Jul 21 06:00:59 PM PDT 24
Finished Jul 21 06:01:02 PM PDT 24
Peak memory 198244 kb
Host smart-230d90d8-bb3b-4e76-8317-729ad7c34027
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660659055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
660659055
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.4202241835
Short name T424
Test name
Test status
Simulation time 186579328 ps
CPU time 0.78 seconds
Started Jul 21 06:01:05 PM PDT 24
Finished Jul 21 06:01:06 PM PDT 24
Peak memory 195696 kb
Host smart-d006217e-0ebe-42ac-a510-740dfdb4b593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202241835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.4202241835
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.464349556
Short name T462
Test name
Test status
Simulation time 188720055 ps
CPU time 1.05 seconds
Started Jul 21 06:01:03 PM PDT 24
Finished Jul 21 06:01:05 PM PDT 24
Peak memory 196316 kb
Host smart-aa54e9d1-66ec-4d74-a260-61e5fb8d98d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464349556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.464349556
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.440392249
Short name T5
Test name
Test status
Simulation time 395586874 ps
CPU time 4.93 seconds
Started Jul 21 06:01:03 PM PDT 24
Finished Jul 21 06:01:09 PM PDT 24
Peak memory 198336 kb
Host smart-be3aec24-7a97-4e0c-a7d3-ad5f057d43ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440392249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ran
dom_long_reg_writes_reg_reads.440392249
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2483576768
Short name T22
Test name
Test status
Simulation time 280900843 ps
CPU time 1.21 seconds
Started Jul 21 06:00:55 PM PDT 24
Finished Jul 21 06:00:59 PM PDT 24
Peak memory 197080 kb
Host smart-2d6e3059-226c-487b-9518-588eac37ba45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483576768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2483576768
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_stress_all.1423342875
Short name T274
Test name
Test status
Simulation time 24719430524 ps
CPU time 156.79 seconds
Started Jul 21 06:00:59 PM PDT 24
Finished Jul 21 06:03:37 PM PDT 24
Peak memory 198304 kb
Host smart-8f7748ed-ad8e-4282-8116-188cb9dd0c5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423342875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.1423342875
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.827092913
Short name T62
Test name
Test status
Simulation time 55110876059 ps
CPU time 1381.39 seconds
Started Jul 21 06:00:59 PM PDT 24
Finished Jul 21 06:24:01 PM PDT 24
Peak memory 198416 kb
Host smart-57881c8f-adb0-4cb0-b51c-501e8ce1e688
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=827092913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.827092913
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.2860394751
Short name T526
Test name
Test status
Simulation time 16382258 ps
CPU time 0.58 seconds
Started Jul 21 06:01:16 PM PDT 24
Finished Jul 21 06:01:17 PM PDT 24
Peak memory 195124 kb
Host smart-93f3faf1-0ec6-4ad4-be7b-e0d5252c5e6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860394751 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.2860394751
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2009701629
Short name T360
Test name
Test status
Simulation time 20050696 ps
CPU time 0.68 seconds
Started Jul 21 06:00:57 PM PDT 24
Finished Jul 21 06:00:59 PM PDT 24
Peak memory 194308 kb
Host smart-9ce1faad-83d4-4adf-9fe7-67b23236c970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009701629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2009701629
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.3735545995
Short name T560
Test name
Test status
Simulation time 470561571 ps
CPU time 16.49 seconds
Started Jul 21 06:01:13 PM PDT 24
Finished Jul 21 06:01:30 PM PDT 24
Peak memory 197264 kb
Host smart-89d528a5-9841-4ec9-bf65-cf9468b107a0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735545995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.3735545995
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2145098853
Short name T181
Test name
Test status
Simulation time 60449103 ps
CPU time 0.86 seconds
Started Jul 21 06:01:14 PM PDT 24
Finished Jul 21 06:01:15 PM PDT 24
Peak memory 196008 kb
Host smart-070b43b3-d76e-4982-b6ca-85b15fae71d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145098853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2145098853
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.1269447486
Short name T262
Test name
Test status
Simulation time 243072652 ps
CPU time 1.33 seconds
Started Jul 21 06:00:53 PM PDT 24
Finished Jul 21 06:00:57 PM PDT 24
Peak memory 196680 kb
Host smart-77f619b7-7e2b-4894-a78e-f7aefbb5a673
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269447486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.1269447486
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.813107163
Short name T70
Test name
Test status
Simulation time 31522004 ps
CPU time 1.42 seconds
Started Jul 21 06:01:05 PM PDT 24
Finished Jul 21 06:01:07 PM PDT 24
Peak memory 196996 kb
Host smart-8022673a-7818-4b99-8f0e-0af68f256c02
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813107163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 38.gpio_intr_with_filter_rand_intr_event.813107163
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.3135726370
Short name T231
Test name
Test status
Simulation time 1806739132 ps
CPU time 2.89 seconds
Started Jul 21 06:00:56 PM PDT 24
Finished Jul 21 06:01:01 PM PDT 24
Peak memory 197504 kb
Host smart-d9199f54-7c39-4e1a-bef4-b6885c9dbf27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135726370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.3135726370
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.537115647
Short name T616
Test name
Test status
Simulation time 490569251 ps
CPU time 0.85 seconds
Started Jul 21 06:01:02 PM PDT 24
Finished Jul 21 06:01:04 PM PDT 24
Peak memory 196716 kb
Host smart-280c665e-a009-4158-81da-57fd30c6e538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537115647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.537115647
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.2063462730
Short name T201
Test name
Test status
Simulation time 31183184 ps
CPU time 1.1 seconds
Started Jul 21 06:01:03 PM PDT 24
Finished Jul 21 06:01:05 PM PDT 24
Peak memory 196964 kb
Host smart-0f9c7cd0-47dd-4e18-94d7-9adaa4470b75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063462730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.2063462730
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.1523932133
Short name T447
Test name
Test status
Simulation time 157439030 ps
CPU time 2.84 seconds
Started Jul 21 06:01:05 PM PDT 24
Finished Jul 21 06:01:09 PM PDT 24
Peak memory 198216 kb
Host smart-87e9a8d0-ffea-4ff5-9d61-23f84e4ae06b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523932133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.1523932133
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2509751367
Short name T13
Test name
Test status
Simulation time 74368205 ps
CPU time 1.16 seconds
Started Jul 21 06:01:02 PM PDT 24
Finished Jul 21 06:01:04 PM PDT 24
Peak memory 196020 kb
Host smart-e05e5d4a-5c8c-417d-b6ce-3a6f8db93cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509751367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2509751367
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.917442176
Short name T128
Test name
Test status
Simulation time 74064609 ps
CPU time 1.21 seconds
Started Jul 21 06:00:58 PM PDT 24
Finished Jul 21 06:01:00 PM PDT 24
Peak memory 197128 kb
Host smart-877944c4-7e63-4774-8147-434667a0a7cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917442176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.917442176
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.3153384812
Short name T463
Test name
Test status
Simulation time 17760235817 ps
CPU time 202.53 seconds
Started Jul 21 06:01:04 PM PDT 24
Finished Jul 21 06:04:27 PM PDT 24
Peak memory 198312 kb
Host smart-21a84e05-135f-4bf6-b7bb-5dc0563b0a93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153384812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.
gpio_stress_all.3153384812
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1130484593
Short name T67
Test name
Test status
Simulation time 138827282635 ps
CPU time 1826.67 seconds
Started Jul 21 06:01:01 PM PDT 24
Finished Jul 21 06:31:28 PM PDT 24
Peak memory 198452 kb
Host smart-73418333-117a-40d2-adad-9b0ead4bb06b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1130484593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1130484593
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3007274195
Short name T161
Test name
Test status
Simulation time 29918114 ps
CPU time 0.59 seconds
Started Jul 21 06:01:03 PM PDT 24
Finished Jul 21 06:01:04 PM PDT 24
Peak memory 195088 kb
Host smart-3f6e465d-629d-4f9f-8c6b-80bf8c356e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007274195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3007274195
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1594947151
Short name T58
Test name
Test status
Simulation time 16035765 ps
CPU time 0.6 seconds
Started Jul 21 06:01:05 PM PDT 24
Finished Jul 21 06:01:06 PM PDT 24
Peak memory 194076 kb
Host smart-e46f875d-38f5-4194-af00-c75f78b437a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594947151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1594947151
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3714258962
Short name T184
Test name
Test status
Simulation time 412411552 ps
CPU time 21.83 seconds
Started Jul 21 06:01:01 PM PDT 24
Finished Jul 21 06:01:23 PM PDT 24
Peak memory 195656 kb
Host smart-8f390d43-5e9c-4a8d-96fc-f3f0471e0fe4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714258962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3714258962
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2474415298
Short name T443
Test name
Test status
Simulation time 61342191 ps
CPU time 1 seconds
Started Jul 21 06:01:05 PM PDT 24
Finished Jul 21 06:01:06 PM PDT 24
Peak memory 197420 kb
Host smart-4d57b871-74fb-4d7a-9b51-e39793d77aa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474415298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2474415298
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.45067886
Short name T290
Test name
Test status
Simulation time 70507950 ps
CPU time 1.2 seconds
Started Jul 21 06:01:18 PM PDT 24
Finished Jul 21 06:01:20 PM PDT 24
Peak memory 196368 kb
Host smart-2c9d7c56-e468-4a7b-9660-0276a9dfe527
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45067886 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.45067886
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.4233403983
Short name T305
Test name
Test status
Simulation time 124075304 ps
CPU time 1.3 seconds
Started Jul 21 06:01:07 PM PDT 24
Finished Jul 21 06:01:09 PM PDT 24
Peak memory 196784 kb
Host smart-c7d964ad-3ef6-4c92-90e3-7313efbbcf95
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233403983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.4233403983
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1725000874
Short name T428
Test name
Test status
Simulation time 38412296 ps
CPU time 1.25 seconds
Started Jul 21 06:01:02 PM PDT 24
Finished Jul 21 06:01:05 PM PDT 24
Peak memory 196336 kb
Host smart-a041bc60-292d-45b7-b09f-78c3a98b46eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725000874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1725000874
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.158432759
Short name T481
Test name
Test status
Simulation time 57887014 ps
CPU time 0.65 seconds
Started Jul 21 06:01:19 PM PDT 24
Finished Jul 21 06:01:21 PM PDT 24
Peak memory 195172 kb
Host smart-2fd8ed63-a92f-410b-bb7e-50619d2c834a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158432759 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.158432759
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2282942602
Short name T676
Test name
Test status
Simulation time 36404633 ps
CPU time 0.69 seconds
Started Jul 21 06:01:14 PM PDT 24
Finished Jul 21 06:01:15 PM PDT 24
Peak memory 196160 kb
Host smart-a2a7476e-f4e2-4d4a-9634-75ffdfbe10ee
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282942602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2282942602
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2565300000
Short name T15
Test name
Test status
Simulation time 437009136 ps
CPU time 5.21 seconds
Started Jul 21 06:01:02 PM PDT 24
Finished Jul 21 06:01:09 PM PDT 24
Peak memory 198228 kb
Host smart-a0b67df8-4318-463c-b5bb-5988c8659bbd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565300000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2565300000
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2734112741
Short name T511
Test name
Test status
Simulation time 70437038 ps
CPU time 0.91 seconds
Started Jul 21 06:01:02 PM PDT 24
Finished Jul 21 06:01:04 PM PDT 24
Peak memory 195416 kb
Host smart-8a9766c2-6ff7-49e7-903a-0631af6729a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734112741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2734112741
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.1862501178
Short name T429
Test name
Test status
Simulation time 47933929 ps
CPU time 1.14 seconds
Started Jul 21 06:01:09 PM PDT 24
Finished Jul 21 06:01:11 PM PDT 24
Peak memory 196540 kb
Host smart-ad345d86-a8f8-4d60-802d-4c9f58b30559
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862501178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.1862501178
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.2671152547
Short name T318
Test name
Test status
Simulation time 34946545866 ps
CPU time 97.91 seconds
Started Jul 21 06:01:07 PM PDT 24
Finished Jul 21 06:02:46 PM PDT 24
Peak memory 198320 kb
Host smart-bb8be954-a4cc-43ed-b47e-d2ec14a60f69
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671152547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.2671152547
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2707326022
Short name T324
Test name
Test status
Simulation time 45029170 ps
CPU time 0.62 seconds
Started Jul 21 05:59:45 PM PDT 24
Finished Jul 21 05:59:47 PM PDT 24
Peak memory 195140 kb
Host smart-9c965473-f87e-48d7-a58a-95e27ce3d7ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707326022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2707326022
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1669222604
Short name T214
Test name
Test status
Simulation time 197174437 ps
CPU time 1.04 seconds
Started Jul 21 05:59:46 PM PDT 24
Finished Jul 21 05:59:48 PM PDT 24
Peak memory 196236 kb
Host smart-f521bd6a-a317-4e43-bf66-d15ec2e9e101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669222604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1669222604
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.1175426763
Short name T407
Test name
Test status
Simulation time 129606939 ps
CPU time 5.05 seconds
Started Jul 21 05:59:43 PM PDT 24
Finished Jul 21 05:59:49 PM PDT 24
Peak memory 196192 kb
Host smart-5d01ccfe-394e-432e-b3a1-ac54b8d28571
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175426763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.1175426763
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.1452571853
Short name T442
Test name
Test status
Simulation time 145708753 ps
CPU time 0.76 seconds
Started Jul 21 05:59:44 PM PDT 24
Finished Jul 21 05:59:45 PM PDT 24
Peak memory 195980 kb
Host smart-920d5abe-ea03-446c-8e13-1dc2ab7385b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452571853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.1452571853
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.2622806297
Short name T168
Test name
Test status
Simulation time 309189764 ps
CPU time 1.4 seconds
Started Jul 21 05:59:51 PM PDT 24
Finished Jul 21 05:59:54 PM PDT 24
Peak memory 195948 kb
Host smart-873c8cd7-3998-405d-94dd-2e80b0592d09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622806297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.2622806297
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.900775634
Short name T417
Test name
Test status
Simulation time 50641641 ps
CPU time 2.08 seconds
Started Jul 21 05:59:43 PM PDT 24
Finished Jul 21 05:59:46 PM PDT 24
Peak memory 198316 kb
Host smart-46b462f8-cde5-45e1-90a1-f2c2386ee5a7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900775634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.gpio_intr_with_filter_rand_intr_event.900775634
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.983174469
Short name T548
Test name
Test status
Simulation time 152390945 ps
CPU time 2.87 seconds
Started Jul 21 05:59:50 PM PDT 24
Finished Jul 21 05:59:53 PM PDT 24
Peak memory 196228 kb
Host smart-3bab5b58-f1a7-486c-a597-ccc0e60065fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983174469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.983174469
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.4049746431
Short name T293
Test name
Test status
Simulation time 85187929 ps
CPU time 1 seconds
Started Jul 21 05:59:45 PM PDT 24
Finished Jul 21 05:59:48 PM PDT 24
Peak memory 196824 kb
Host smart-78a7fabe-305a-49a2-bc9e-737fb74f27c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049746431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.4049746431
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.597571229
Short name T523
Test name
Test status
Simulation time 77492875 ps
CPU time 0.8 seconds
Started Jul 21 05:59:51 PM PDT 24
Finished Jul 21 05:59:53 PM PDT 24
Peak memory 195648 kb
Host smart-e5ff6e65-79e2-4a4d-9393-edc1e75bc0f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597571229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.597571229
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1505075360
Short name T3
Test name
Test status
Simulation time 396378760 ps
CPU time 4.98 seconds
Started Jul 21 05:59:45 PM PDT 24
Finished Jul 21 05:59:51 PM PDT 24
Peak memory 198196 kb
Host smart-b2912c4b-f44a-4170-9600-138faff8d25a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505075360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1505075360
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2239764338
Short name T40
Test name
Test status
Simulation time 234700610 ps
CPU time 0.79 seconds
Started Jul 21 05:59:51 PM PDT 24
Finished Jul 21 05:59:52 PM PDT 24
Peak memory 214352 kb
Host smart-398903ce-a501-4f44-b4e0-fc1b420dcfc9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239764338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2239764338
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1813408430
Short name T264
Test name
Test status
Simulation time 100940412 ps
CPU time 0.87 seconds
Started Jul 21 05:59:45 PM PDT 24
Finished Jul 21 05:59:47 PM PDT 24
Peak memory 195404 kb
Host smart-d7e56796-ca43-44e6-8bca-74c087247c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813408430 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1813408430
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1878077756
Short name T514
Test name
Test status
Simulation time 50911939 ps
CPU time 0.91 seconds
Started Jul 21 05:59:46 PM PDT 24
Finished Jul 21 05:59:48 PM PDT 24
Peak memory 196512 kb
Host smart-48bdf22f-e54d-4fee-adbe-f95a78b4866a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878077756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1878077756
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.2727197634
Short name T230
Test name
Test status
Simulation time 42983824405 ps
CPU time 189.34 seconds
Started Jul 21 05:59:50 PM PDT 24
Finished Jul 21 06:03:00 PM PDT 24
Peak memory 198500 kb
Host smart-387c9736-76d7-4a69-b748-a59c47723d94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727197634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.2727197634
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.3973397587
Short name T66
Test name
Test status
Simulation time 26611785240 ps
CPU time 459.4 seconds
Started Jul 21 05:59:44 PM PDT 24
Finished Jul 21 06:07:25 PM PDT 24
Peak memory 198480 kb
Host smart-e80929c8-e7a7-4457-b7df-1919520bf24b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3973397587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.3973397587
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3644433107
Short name T411
Test name
Test status
Simulation time 38092417 ps
CPU time 0.69 seconds
Started Jul 21 06:01:02 PM PDT 24
Finished Jul 21 06:01:03 PM PDT 24
Peak memory 195016 kb
Host smart-6681d4ae-950b-4723-ae9c-b2a72f10d9a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644433107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3644433107
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.2386773259
Short name T233
Test name
Test status
Simulation time 19644188 ps
CPU time 0.63 seconds
Started Jul 21 06:01:00 PM PDT 24
Finished Jul 21 06:01:01 PM PDT 24
Peak memory 194208 kb
Host smart-c01bd0d5-7b77-40ae-88c7-d571c340cc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386773259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.2386773259
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.327993890
Short name T607
Test name
Test status
Simulation time 497232721 ps
CPU time 3.89 seconds
Started Jul 21 06:01:13 PM PDT 24
Finished Jul 21 06:01:17 PM PDT 24
Peak memory 196964 kb
Host smart-ab7b079a-29a5-4697-a990-03b7b6792c13
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327993890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.327993890
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.3685748485
Short name T457
Test name
Test status
Simulation time 122313782 ps
CPU time 0.66 seconds
Started Jul 21 06:01:01 PM PDT 24
Finished Jul 21 06:01:02 PM PDT 24
Peak memory 194724 kb
Host smart-1d448a0a-6a90-4ce6-9ccd-bc1f011945fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685748485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.3685748485
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1072443854
Short name T138
Test name
Test status
Simulation time 294518941 ps
CPU time 1.1 seconds
Started Jul 21 06:01:02 PM PDT 24
Finished Jul 21 06:01:04 PM PDT 24
Peak memory 196216 kb
Host smart-39d7c74c-0ce6-417e-9069-59ffcd2ef5bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072443854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1072443854
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.528205749
Short name T371
Test name
Test status
Simulation time 253540578 ps
CPU time 2.65 seconds
Started Jul 21 06:01:09 PM PDT 24
Finished Jul 21 06:01:13 PM PDT 24
Peak memory 196740 kb
Host smart-5ee64170-72aa-4d74-a62b-4811d66f66e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528205749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.528205749
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2724895470
Short name T408
Test name
Test status
Simulation time 581381610 ps
CPU time 1.15 seconds
Started Jul 21 06:01:10 PM PDT 24
Finished Jul 21 06:01:11 PM PDT 24
Peak memory 195744 kb
Host smart-f4be3d13-a8fb-4c70-a022-c35cf8f5566e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724895470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2724895470
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1774866031
Short name T189
Test name
Test status
Simulation time 201786311 ps
CPU time 1.21 seconds
Started Jul 21 06:01:12 PM PDT 24
Finished Jul 21 06:01:14 PM PDT 24
Peak memory 197340 kb
Host smart-ccc919a0-2db5-4156-ac5a-4bd2bbfac78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774866031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1774866031
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2637131408
Short name T474
Test name
Test status
Simulation time 28088023 ps
CPU time 0.83 seconds
Started Jul 21 06:01:04 PM PDT 24
Finished Jul 21 06:01:05 PM PDT 24
Peak memory 195536 kb
Host smart-32c99796-659f-4918-a1fe-e3b76bd548d2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637131408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2637131408
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.2043912820
Short name T604
Test name
Test status
Simulation time 252139419 ps
CPU time 3.18 seconds
Started Jul 21 06:01:00 PM PDT 24
Finished Jul 21 06:01:04 PM PDT 24
Peak memory 198176 kb
Host smart-d9e1471c-c003-4e83-a3b0-6a7752b57df2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043912820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.2043912820
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1584680388
Short name T356
Test name
Test status
Simulation time 64570285 ps
CPU time 1.2 seconds
Started Jul 21 06:01:03 PM PDT 24
Finished Jul 21 06:01:05 PM PDT 24
Peak memory 195852 kb
Host smart-15760a62-9c1d-4e59-97fd-342b62ca0ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584680388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1584680388
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.44204097
Short name T625
Test name
Test status
Simulation time 179786450 ps
CPU time 0.97 seconds
Started Jul 21 06:01:02 PM PDT 24
Finished Jul 21 06:01:04 PM PDT 24
Peak memory 196036 kb
Host smart-34434076-bfdd-4fbe-9859-0ac1550438a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44204097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.44204097
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.1840704220
Short name T341
Test name
Test status
Simulation time 4482214077 ps
CPU time 58.2 seconds
Started Jul 21 06:01:15 PM PDT 24
Finished Jul 21 06:02:14 PM PDT 24
Peak memory 198240 kb
Host smart-802d4b20-a561-47c3-9d21-0cdd35c74c61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840704220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.1840704220
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1357692264
Short name T477
Test name
Test status
Simulation time 14222001 ps
CPU time 0.59 seconds
Started Jul 21 06:01:09 PM PDT 24
Finished Jul 21 06:01:10 PM PDT 24
Peak memory 194212 kb
Host smart-7f2b7c89-f4f0-43e6-a8a5-bd7549fcbc89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357692264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1357692264
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2058470098
Short name T141
Test name
Test status
Simulation time 38266221 ps
CPU time 0.97 seconds
Started Jul 21 06:01:01 PM PDT 24
Finished Jul 21 06:01:03 PM PDT 24
Peak memory 195444 kb
Host smart-44308f70-7b9e-4ecf-a8a1-1d13f7f3f7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058470098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2058470098
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.361496416
Short name T298
Test name
Test status
Simulation time 1511990051 ps
CPU time 24.59 seconds
Started Jul 21 06:01:15 PM PDT 24
Finished Jul 21 06:01:40 PM PDT 24
Peak memory 198184 kb
Host smart-0c9c8c05-963a-40f1-b764-b9db0e75fb29
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361496416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.361496416
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.3788046717
Short name T485
Test name
Test status
Simulation time 126062049 ps
CPU time 0.9 seconds
Started Jul 21 06:01:06 PM PDT 24
Finished Jul 21 06:01:07 PM PDT 24
Peak memory 196992 kb
Host smart-ea4997f5-0b67-4f22-b5d2-47589b4b8c5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788046717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.3788046717
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1688250107
Short name T199
Test name
Test status
Simulation time 143025853 ps
CPU time 1.23 seconds
Started Jul 21 06:01:00 PM PDT 24
Finished Jul 21 06:01:02 PM PDT 24
Peak memory 196028 kb
Host smart-3ae0443d-cb77-4881-995c-0a168d03f908
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688250107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1688250107
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.255934131
Short name T188
Test name
Test status
Simulation time 51377794 ps
CPU time 1.55 seconds
Started Jul 21 06:01:11 PM PDT 24
Finished Jul 21 06:01:13 PM PDT 24
Peak memory 196960 kb
Host smart-4cb1f67f-6602-4d86-82b1-36b1e357bce3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255934131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.gpio_intr_with_filter_rand_intr_event.255934131
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.4238297400
Short name T69
Test name
Test status
Simulation time 829031659 ps
CPU time 2.2 seconds
Started Jul 21 06:01:18 PM PDT 24
Finished Jul 21 06:01:20 PM PDT 24
Peak memory 197408 kb
Host smart-8f80f987-d954-4a87-9386-786828a311f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238297400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.4238297400
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.4024130162
Short name T540
Test name
Test status
Simulation time 35291427 ps
CPU time 0.93 seconds
Started Jul 21 06:01:14 PM PDT 24
Finished Jul 21 06:01:15 PM PDT 24
Peak memory 196004 kb
Host smart-41f6723c-af5f-491d-97f0-afaf844148e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024130162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.4024130162
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.778266666
Short name T656
Test name
Test status
Simulation time 148126041 ps
CPU time 1.08 seconds
Started Jul 21 06:01:04 PM PDT 24
Finished Jul 21 06:01:06 PM PDT 24
Peak memory 196476 kb
Host smart-13c2f9c8-b5b3-4046-a7e2-bd59ef706921
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778266666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullup
_pulldown.778266666
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.1674082874
Short name T617
Test name
Test status
Simulation time 231703445 ps
CPU time 2.96 seconds
Started Jul 21 06:01:05 PM PDT 24
Finished Jul 21 06:01:09 PM PDT 24
Peak memory 198224 kb
Host smart-bfac0c38-265d-4e80-9ff5-5a8f237969a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674082874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.1674082874
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.2933502101
Short name T387
Test name
Test status
Simulation time 189799990 ps
CPU time 1.42 seconds
Started Jul 21 06:01:02 PM PDT 24
Finished Jul 21 06:01:05 PM PDT 24
Peak memory 197120 kb
Host smart-21afeddb-3395-4d31-9ca9-91813e08af9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933502101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.2933502101
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1244119428
Short name T366
Test name
Test status
Simulation time 358387573 ps
CPU time 1.15 seconds
Started Jul 21 06:01:12 PM PDT 24
Finished Jul 21 06:01:14 PM PDT 24
Peak memory 196092 kb
Host smart-600fbca7-bf2d-452e-a682-db35c2094acb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244119428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1244119428
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.675735620
Short name T499
Test name
Test status
Simulation time 3942259654 ps
CPU time 46.55 seconds
Started Jul 21 06:01:13 PM PDT 24
Finished Jul 21 06:02:00 PM PDT 24
Peak memory 198316 kb
Host smart-42620e41-d975-4d98-932d-a72564cf9d0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675735620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.g
pio_stress_all.675735620
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2265266323
Short name T326
Test name
Test status
Simulation time 51190169 ps
CPU time 0.55 seconds
Started Jul 21 06:01:15 PM PDT 24
Finished Jul 21 06:01:15 PM PDT 24
Peak memory 194152 kb
Host smart-a9080d32-8d99-42fd-aac7-32436ecc5a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265266323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2265266323
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.3063583010
Short name T337
Test name
Test status
Simulation time 33913154 ps
CPU time 0.67 seconds
Started Jul 21 06:01:06 PM PDT 24
Finished Jul 21 06:01:07 PM PDT 24
Peak memory 194884 kb
Host smart-6329a6ed-6e9e-4c08-bc97-234e52f64e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063583010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.3063583010
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1024183721
Short name T534
Test name
Test status
Simulation time 720283975 ps
CPU time 20.58 seconds
Started Jul 21 06:01:19 PM PDT 24
Finished Jul 21 06:01:40 PM PDT 24
Peak memory 195796 kb
Host smart-80b29490-402e-4d4e-86de-19e56e6ef517
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024183721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1024183721
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.899965322
Short name T509
Test name
Test status
Simulation time 43681651 ps
CPU time 0.76 seconds
Started Jul 21 06:01:07 PM PDT 24
Finished Jul 21 06:01:08 PM PDT 24
Peak memory 195948 kb
Host smart-41c0e335-d998-4bff-a8e6-4f17f38902ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899965322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.899965322
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.207887976
Short name T400
Test name
Test status
Simulation time 33886442 ps
CPU time 0.98 seconds
Started Jul 21 06:01:07 PM PDT 24
Finished Jul 21 06:01:09 PM PDT 24
Peak memory 196328 kb
Host smart-61176368-fecc-4b57-b927-ce969dfc00b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207887976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.207887976
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3825935148
Short name T218
Test name
Test status
Simulation time 318731095 ps
CPU time 1.73 seconds
Started Jul 21 06:01:09 PM PDT 24
Finished Jul 21 06:01:11 PM PDT 24
Peak memory 198248 kb
Host smart-aaf28dcb-0092-4afa-964d-e32904bea573
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825935148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3825935148
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.1347481769
Short name T422
Test name
Test status
Simulation time 31085699 ps
CPU time 1.06 seconds
Started Jul 21 06:01:10 PM PDT 24
Finished Jul 21 06:01:11 PM PDT 24
Peak memory 195860 kb
Host smart-656fc4a7-da2e-4616-9a83-1793d8ca02db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347481769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.1347481769
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2829404855
Short name T527
Test name
Test status
Simulation time 26943026 ps
CPU time 0.8 seconds
Started Jul 21 06:01:14 PM PDT 24
Finished Jul 21 06:01:15 PM PDT 24
Peak memory 196384 kb
Host smart-3bd54b66-73d8-4d60-9611-3ee01c43b194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829404855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2829404855
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.102213882
Short name T119
Test name
Test status
Simulation time 138653331 ps
CPU time 0.95 seconds
Started Jul 21 06:01:06 PM PDT 24
Finished Jul 21 06:01:07 PM PDT 24
Peak memory 197072 kb
Host smart-3e1bbb14-7e88-4407-995f-67cb64af27fb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102213882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup
_pulldown.102213882
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.3678923299
Short name T300
Test name
Test status
Simulation time 89236851 ps
CPU time 4.01 seconds
Started Jul 21 06:01:16 PM PDT 24
Finished Jul 21 06:01:20 PM PDT 24
Peak memory 198276 kb
Host smart-34774700-4600-4466-ba0e-e5358eeed50d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678923299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.3678923299
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.1644855108
Short name T456
Test name
Test status
Simulation time 47012483 ps
CPU time 1.22 seconds
Started Jul 21 06:01:08 PM PDT 24
Finished Jul 21 06:01:09 PM PDT 24
Peak memory 196160 kb
Host smart-66c94a81-e506-422e-ba00-31c2337b7b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644855108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.1644855108
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3778141266
Short name T479
Test name
Test status
Simulation time 243368833 ps
CPU time 1.2 seconds
Started Jul 21 06:01:07 PM PDT 24
Finished Jul 21 06:01:08 PM PDT 24
Peak memory 197036 kb
Host smart-05ad427a-67fe-4973-a2d6-dcf927b1fdf9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778141266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3778141266
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.1013636272
Short name T533
Test name
Test status
Simulation time 7130406081 ps
CPU time 91.87 seconds
Started Jul 21 06:01:17 PM PDT 24
Finished Jul 21 06:02:49 PM PDT 24
Peak memory 198384 kb
Host smart-9b9fd783-8080-4242-b29e-627c5fe171b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013636272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.1013636272
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3899437119
Short name T682
Test name
Test status
Simulation time 14591962 ps
CPU time 0.56 seconds
Started Jul 21 06:01:18 PM PDT 24
Finished Jul 21 06:01:19 PM PDT 24
Peak memory 194876 kb
Host smart-0d3fd118-4317-4980-9c89-54b74c5de528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899437119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3899437119
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.310865329
Short name T196
Test name
Test status
Simulation time 113767620 ps
CPU time 0.79 seconds
Started Jul 21 06:01:16 PM PDT 24
Finished Jul 21 06:01:18 PM PDT 24
Peak memory 196180 kb
Host smart-576d6661-21d3-44f6-abf3-d1de0d371827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310865329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.310865329
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1323730500
Short name T120
Test name
Test status
Simulation time 1026478154 ps
CPU time 24.47 seconds
Started Jul 21 06:01:19 PM PDT 24
Finished Jul 21 06:01:45 PM PDT 24
Peak memory 195780 kb
Host smart-b5e0399a-f4fa-430d-98ad-8c136bfd186c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323730500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1323730500
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.896695144
Short name T570
Test name
Test status
Simulation time 528686586 ps
CPU time 0.73 seconds
Started Jul 21 06:01:08 PM PDT 24
Finished Jul 21 06:01:09 PM PDT 24
Peak memory 195952 kb
Host smart-a2388fa5-96b1-40c3-9700-371b9e5a0a9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896695144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.896695144
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.3949393682
Short name T297
Test name
Test status
Simulation time 293791721 ps
CPU time 1.27 seconds
Started Jul 21 06:01:07 PM PDT 24
Finished Jul 21 06:01:09 PM PDT 24
Peak memory 196016 kb
Host smart-fb6cb1c5-67f1-4fdc-a4b7-c31a46c7ffc1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949393682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.3949393682
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3110184479
Short name T122
Test name
Test status
Simulation time 83972764 ps
CPU time 3.19 seconds
Started Jul 21 06:01:08 PM PDT 24
Finished Jul 21 06:01:12 PM PDT 24
Peak memory 198212 kb
Host smart-70194c22-357b-4cbe-a628-e850b36bbc65
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110184479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3110184479
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2116123899
Short name T688
Test name
Test status
Simulation time 138511488 ps
CPU time 1.46 seconds
Started Jul 21 06:01:07 PM PDT 24
Finished Jul 21 06:01:09 PM PDT 24
Peak memory 196368 kb
Host smart-5f7862fd-3eb9-4d19-a63e-09d86114b319
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116123899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2116123899
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3266424078
Short name T691
Test name
Test status
Simulation time 300858246 ps
CPU time 0.93 seconds
Started Jul 21 06:01:07 PM PDT 24
Finished Jul 21 06:01:09 PM PDT 24
Peak memory 197508 kb
Host smart-cf5fba53-b9a7-4637-9dfc-984d7ab78354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266424078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3266424078
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1060506447
Short name T137
Test name
Test status
Simulation time 137214042 ps
CPU time 0.73 seconds
Started Jul 21 06:01:08 PM PDT 24
Finished Jul 21 06:01:09 PM PDT 24
Peak memory 195528 kb
Host smart-546b6782-bb05-481a-b17a-5cac566b5a79
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060506447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1060506447
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3565289406
Short name T529
Test name
Test status
Simulation time 2220746146 ps
CPU time 5.79 seconds
Started Jul 21 06:01:09 PM PDT 24
Finished Jul 21 06:01:16 PM PDT 24
Peak memory 198244 kb
Host smart-66ea8274-e129-4ade-95d5-2f8f5e561694
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565289406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3565289406
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1230429612
Short name T677
Test name
Test status
Simulation time 72403314 ps
CPU time 1.15 seconds
Started Jul 21 06:01:15 PM PDT 24
Finished Jul 21 06:01:16 PM PDT 24
Peak memory 196064 kb
Host smart-36f21d5b-9b0f-459b-b3a6-c8b8ae9dccc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230429612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1230429612
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.540879697
Short name T551
Test name
Test status
Simulation time 34219398 ps
CPU time 0.82 seconds
Started Jul 21 06:01:14 PM PDT 24
Finished Jul 21 06:01:15 PM PDT 24
Peak memory 195396 kb
Host smart-4018427d-5cf2-4a12-8379-2eaffa7ce62f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540879697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.540879697
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1964005099
Short name T669
Test name
Test status
Simulation time 27518526626 ps
CPU time 203.97 seconds
Started Jul 21 06:01:18 PM PDT 24
Finished Jul 21 06:04:42 PM PDT 24
Peak memory 198408 kb
Host smart-dbc1b1c7-6e9f-48c0-aee3-db242a737605
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964005099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1964005099
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2455113197
Short name T34
Test name
Test status
Simulation time 146695356242 ps
CPU time 889.11 seconds
Started Jul 21 06:01:22 PM PDT 24
Finished Jul 21 06:16:12 PM PDT 24
Peak memory 198548 kb
Host smart-5eb98d14-1aa9-49a9-9168-381090ac4b14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2455113197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2455113197
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.2733639481
Short name T575
Test name
Test status
Simulation time 15271723 ps
CPU time 0.6 seconds
Started Jul 21 06:01:16 PM PDT 24
Finished Jul 21 06:01:17 PM PDT 24
Peak memory 194788 kb
Host smart-6f909eb3-06c6-47ba-a261-c66171881e86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733639481 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.2733639481
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1081076207
Short name T28
Test name
Test status
Simulation time 104942064 ps
CPU time 0.97 seconds
Started Jul 21 06:01:21 PM PDT 24
Finished Jul 21 06:01:23 PM PDT 24
Peak memory 196108 kb
Host smart-23d84e10-471a-4875-8af9-723beeef524b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081076207 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1081076207
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.3670508233
Short name T351
Test name
Test status
Simulation time 3644202888 ps
CPU time 15.95 seconds
Started Jul 21 06:01:35 PM PDT 24
Finished Jul 21 06:01:51 PM PDT 24
Peak memory 197072 kb
Host smart-05d5a908-584c-4e06-9674-86a501ea216d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670508233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.3670508233
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.1105938449
Short name T545
Test name
Test status
Simulation time 124092689 ps
CPU time 1.1 seconds
Started Jul 21 06:01:15 PM PDT 24
Finished Jul 21 06:01:17 PM PDT 24
Peak memory 196408 kb
Host smart-24213b86-f47e-4dad-9cff-385ebb120bc6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105938449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.1105938449
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.922098269
Short name T386
Test name
Test status
Simulation time 127117689 ps
CPU time 2.04 seconds
Started Jul 21 06:01:17 PM PDT 24
Finished Jul 21 06:01:20 PM PDT 24
Peak memory 198260 kb
Host smart-ec676f71-7a3b-45c9-ae89-d98f66315370
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922098269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.922098269
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.972631891
Short name T112
Test name
Test status
Simulation time 137554411 ps
CPU time 0.86 seconds
Started Jul 21 06:01:18 PM PDT 24
Finished Jul 21 06:01:19 PM PDT 24
Peak memory 196440 kb
Host smart-229fb71d-482f-41ac-8110-4dc9a3303d54
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972631891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
972631891
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3146382314
Short name T636
Test name
Test status
Simulation time 229050924 ps
CPU time 1.26 seconds
Started Jul 21 06:01:16 PM PDT 24
Finished Jul 21 06:01:18 PM PDT 24
Peak memory 198328 kb
Host smart-7cb08f61-318e-4d6f-ad63-cd14ae9982b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146382314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3146382314
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.3881996927
Short name T554
Test name
Test status
Simulation time 125776660 ps
CPU time 0.94 seconds
Started Jul 21 06:01:20 PM PDT 24
Finished Jul 21 06:01:22 PM PDT 24
Peak memory 196168 kb
Host smart-22632016-bc72-43df-9d99-dd986c95c444
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881996927 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.3881996927
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.282311376
Short name T419
Test name
Test status
Simulation time 195226080 ps
CPU time 4.84 seconds
Started Jul 21 06:01:26 PM PDT 24
Finished Jul 21 06:01:32 PM PDT 24
Peak memory 198248 kb
Host smart-e61e71e2-d0e8-4544-acb6-e353c048f571
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282311376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.282311376
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1881832238
Short name T421
Test name
Test status
Simulation time 324345706 ps
CPU time 1.25 seconds
Started Jul 21 06:01:28 PM PDT 24
Finished Jul 21 06:01:30 PM PDT 24
Peak memory 195552 kb
Host smart-461320fa-fb82-4064-aa11-026bef0a00eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881832238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1881832238
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1491617855
Short name T496
Test name
Test status
Simulation time 82573928 ps
CPU time 1.55 seconds
Started Jul 21 06:01:20 PM PDT 24
Finished Jul 21 06:01:22 PM PDT 24
Peak memory 196476 kb
Host smart-b0adc98f-6e61-4cf2-b384-01e993b14f2a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491617855 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1491617855
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3281937032
Short name T584
Test name
Test status
Simulation time 36390696603 ps
CPU time 193.54 seconds
Started Jul 21 06:01:30 PM PDT 24
Finished Jul 21 06:04:44 PM PDT 24
Peak memory 198308 kb
Host smart-1248c469-d4b5-4939-bdd0-14dd74d3f3b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281937032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3281937032
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_alert_test.2642009725
Short name T271
Test name
Test status
Simulation time 32176031 ps
CPU time 0.57 seconds
Started Jul 21 06:01:37 PM PDT 24
Finished Jul 21 06:01:40 PM PDT 24
Peak memory 194224 kb
Host smart-c550e384-ae11-4fca-a64f-86b2be2a3f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642009725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.2642009725
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1340459215
Short name T595
Test name
Test status
Simulation time 18705885 ps
CPU time 0.74 seconds
Started Jul 21 06:01:15 PM PDT 24
Finished Jul 21 06:01:17 PM PDT 24
Peak memory 195432 kb
Host smart-53ef3a2b-9aa8-48de-8041-99d1040ae33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340459215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1340459215
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.2751602232
Short name T500
Test name
Test status
Simulation time 850517414 ps
CPU time 15.01 seconds
Started Jul 21 06:01:17 PM PDT 24
Finished Jul 21 06:01:32 PM PDT 24
Peak memory 197408 kb
Host smart-4af6d79e-fd35-4ed5-8d56-e33976cd315e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751602232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.2751602232
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1025389414
Short name T689
Test name
Test status
Simulation time 346529025 ps
CPU time 0.95 seconds
Started Jul 21 06:01:19 PM PDT 24
Finished Jul 21 06:01:21 PM PDT 24
Peak memory 196596 kb
Host smart-6adb5424-ca4b-4d82-8f02-15e9421b3500
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025389414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1025389414
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.3706463497
Short name T461
Test name
Test status
Simulation time 112439276 ps
CPU time 1.07 seconds
Started Jul 21 06:01:23 PM PDT 24
Finished Jul 21 06:01:24 PM PDT 24
Peak memory 196216 kb
Host smart-69a9ed17-3af2-4433-8acb-af7dc6dff40f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706463497 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.3706463497
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.3320190660
Short name T180
Test name
Test status
Simulation time 119102824 ps
CPU time 1.32 seconds
Started Jul 21 06:01:19 PM PDT 24
Finished Jul 21 06:01:22 PM PDT 24
Peak memory 196488 kb
Host smart-a7d16cb3-56ed-4818-9134-3241d046260e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320190660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.3320190660
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1943908034
Short name T291
Test name
Test status
Simulation time 102905124 ps
CPU time 2.44 seconds
Started Jul 21 06:01:19 PM PDT 24
Finished Jul 21 06:01:23 PM PDT 24
Peak memory 198328 kb
Host smart-f0e1575b-ae32-4994-a6bf-7a02e5f99871
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943908034 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1943908034
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3354737383
Short name T182
Test name
Test status
Simulation time 269895413 ps
CPU time 1.35 seconds
Started Jul 21 06:01:18 PM PDT 24
Finished Jul 21 06:01:20 PM PDT 24
Peak memory 197324 kb
Host smart-b1cf7c03-de52-441c-b8cf-6175aac951d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354737383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3354737383
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.3447222468
Short name T250
Test name
Test status
Simulation time 21827388 ps
CPU time 0.64 seconds
Started Jul 21 06:01:16 PM PDT 24
Finished Jul 21 06:01:17 PM PDT 24
Peak memory 194476 kb
Host smart-435fdd77-b3fe-4845-9721-ede41101feb4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447222468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.3447222468
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1985975254
Short name T130
Test name
Test status
Simulation time 136352296 ps
CPU time 3.27 seconds
Started Jul 21 06:01:19 PM PDT 24
Finished Jul 21 06:01:23 PM PDT 24
Peak memory 198196 kb
Host smart-f28f5f40-e3e7-425b-ab9b-2336a196f1db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985975254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1985975254
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.1887864613
Short name T568
Test name
Test status
Simulation time 174731251 ps
CPU time 1.02 seconds
Started Jul 21 06:01:15 PM PDT 24
Finished Jul 21 06:01:17 PM PDT 24
Peak memory 196780 kb
Host smart-aa10eec3-6f04-43c5-b168-7afb4cb96899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887864613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.1887864613
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3571056453
Short name T522
Test name
Test status
Simulation time 70267753 ps
CPU time 1.1 seconds
Started Jul 21 06:01:18 PM PDT 24
Finished Jul 21 06:01:20 PM PDT 24
Peak memory 196000 kb
Host smart-e6b67ef4-c2ff-45aa-8405-5eed55393d27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571056453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3571056453
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3999325513
Short name T401
Test name
Test status
Simulation time 5986315059 ps
CPU time 142.38 seconds
Started Jul 21 06:01:20 PM PDT 24
Finished Jul 21 06:03:43 PM PDT 24
Peak memory 198436 kb
Host smart-9712bb4a-09ee-4a9b-8fc4-e901a0994ef0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999325513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3999325513
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.3028981845
Short name T65
Test name
Test status
Simulation time 42582100164 ps
CPU time 1060.98 seconds
Started Jul 21 06:01:25 PM PDT 24
Finished Jul 21 06:19:07 PM PDT 24
Peak memory 198544 kb
Host smart-e455e430-eb94-4b8c-bbff-da1389d8cfe6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3028981845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.3028981845
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.169364300
Short name T11
Test name
Test status
Simulation time 19345895 ps
CPU time 0.62 seconds
Started Jul 21 06:01:26 PM PDT 24
Finished Jul 21 06:01:28 PM PDT 24
Peak memory 194168 kb
Host smart-a8857d3d-2578-4196-a7ef-fa4b6d5b43c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169364300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.169364300
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.398861624
Short name T190
Test name
Test status
Simulation time 55101409 ps
CPU time 0.71 seconds
Started Jul 21 06:01:16 PM PDT 24
Finished Jul 21 06:01:17 PM PDT 24
Peak memory 196180 kb
Host smart-6c9a38f6-29b2-47f1-9e9e-2208b7b232bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398861624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.398861624
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2185904678
Short name T603
Test name
Test status
Simulation time 1380140370 ps
CPU time 10.36 seconds
Started Jul 21 06:01:23 PM PDT 24
Finished Jul 21 06:01:34 PM PDT 24
Peak memory 197244 kb
Host smart-504d64c2-f14f-4d55-b7ef-dc0f56f78cdb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185904678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2185904678
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.177140035
Short name T396
Test name
Test status
Simulation time 27508072 ps
CPU time 0.7 seconds
Started Jul 21 06:01:27 PM PDT 24
Finished Jul 21 06:01:29 PM PDT 24
Peak memory 194892 kb
Host smart-0884cae9-586a-48d0-9b84-3d211121af03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177140035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.177140035
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2604870876
Short name T175
Test name
Test status
Simulation time 47363009 ps
CPU time 1.22 seconds
Started Jul 21 06:01:20 PM PDT 24
Finished Jul 21 06:01:22 PM PDT 24
Peak memory 196252 kb
Host smart-ace0299c-7591-423f-96ab-1901c49abcc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604870876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2604870876
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3125668866
Short name T156
Test name
Test status
Simulation time 339370254 ps
CPU time 3.46 seconds
Started Jul 21 06:01:19 PM PDT 24
Finished Jul 21 06:01:24 PM PDT 24
Peak memory 198252 kb
Host smart-41fedc92-46e7-4a28-91e9-845163f32879
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125668866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3125668866
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1215375359
Short name T610
Test name
Test status
Simulation time 301771230 ps
CPU time 2.45 seconds
Started Jul 21 06:01:16 PM PDT 24
Finished Jul 21 06:01:19 PM PDT 24
Peak memory 196116 kb
Host smart-5a7168eb-721c-4399-b4e5-71171bc1d88d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215375359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1215375359
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.4287865916
Short name T426
Test name
Test status
Simulation time 122182046 ps
CPU time 1.26 seconds
Started Jul 21 06:01:17 PM PDT 24
Finished Jul 21 06:01:19 PM PDT 24
Peak memory 198308 kb
Host smart-03878c37-619b-4206-bd78-c82ad2070b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287865916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.4287865916
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.4024309765
Short name T546
Test name
Test status
Simulation time 145831504 ps
CPU time 0.97 seconds
Started Jul 21 06:01:16 PM PDT 24
Finished Jul 21 06:01:18 PM PDT 24
Peak memory 196264 kb
Host smart-0c880a0f-86ba-436c-a9c9-d4a7001edb24
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024309765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.4024309765
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.2547414735
Short name T148
Test name
Test status
Simulation time 178693626 ps
CPU time 1.93 seconds
Started Jul 21 06:01:28 PM PDT 24
Finished Jul 21 06:01:31 PM PDT 24
Peak memory 198180 kb
Host smart-4cd75189-e2fc-43d5-b2e8-fcc2b800c03d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547414735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.2547414735
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.3645954700
Short name T665
Test name
Test status
Simulation time 131334578 ps
CPU time 1.22 seconds
Started Jul 21 06:01:18 PM PDT 24
Finished Jul 21 06:01:20 PM PDT 24
Peak memory 196084 kb
Host smart-6985c7e4-ec2d-4cb2-9d71-b952a6621df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645954700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.3645954700
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3430117937
Short name T693
Test name
Test status
Simulation time 129575708 ps
CPU time 1.16 seconds
Started Jul 21 06:01:15 PM PDT 24
Finished Jul 21 06:01:17 PM PDT 24
Peak memory 196016 kb
Host smart-9319cc96-27b5-4968-8123-c7b4f6e47aff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430117937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3430117937
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2388881355
Short name T328
Test name
Test status
Simulation time 5463417062 ps
CPU time 35.24 seconds
Started Jul 21 06:01:36 PM PDT 24
Finished Jul 21 06:02:13 PM PDT 24
Peak memory 198304 kb
Host smart-a2a23a32-7ac0-4f10-8cee-ef0f9031e781
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388881355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2388881355
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_alert_test.584548086
Short name T613
Test name
Test status
Simulation time 22869521 ps
CPU time 0.59 seconds
Started Jul 21 06:01:30 PM PDT 24
Finished Jul 21 06:01:31 PM PDT 24
Peak memory 194804 kb
Host smart-b1c7fcc7-9c0a-473d-abf8-124d71884fd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584548086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.584548086
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1766652102
Short name T579
Test name
Test status
Simulation time 102335427 ps
CPU time 0.86 seconds
Started Jul 21 06:01:26 PM PDT 24
Finished Jul 21 06:01:28 PM PDT 24
Peak memory 196836 kb
Host smart-55bcb42c-8929-4b0a-bb0f-741e6b801c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766652102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1766652102
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.2858516641
Short name T563
Test name
Test status
Simulation time 458585468 ps
CPU time 22.9 seconds
Started Jul 21 06:01:24 PM PDT 24
Finished Jul 21 06:01:48 PM PDT 24
Peak memory 198220 kb
Host smart-d6bf67c7-ed09-4de0-a534-a7e6e8311d76
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858516641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.2858516641
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.625828585
Short name T275
Test name
Test status
Simulation time 187665934 ps
CPU time 0.83 seconds
Started Jul 21 06:01:25 PM PDT 24
Finished Jul 21 06:01:27 PM PDT 24
Peak memory 196080 kb
Host smart-41b39f15-cd84-4c38-9023-e4356e209620
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625828585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.625828585
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.2131832429
Short name T217
Test name
Test status
Simulation time 83955471 ps
CPU time 1.18 seconds
Started Jul 21 06:01:30 PM PDT 24
Finished Jul 21 06:01:32 PM PDT 24
Peak memory 196960 kb
Host smart-3706c2a5-9078-4c0e-b4a0-ea2e9f00c298
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131832429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.2131832429
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3972364815
Short name T649
Test name
Test status
Simulation time 512360744 ps
CPU time 1.57 seconds
Started Jul 21 06:01:24 PM PDT 24
Finished Jul 21 06:01:26 PM PDT 24
Peak memory 197032 kb
Host smart-5b09b69c-ab5e-41a6-9b14-882bd2679128
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972364815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3972364815
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.2196550283
Short name T598
Test name
Test status
Simulation time 666513369 ps
CPU time 3.14 seconds
Started Jul 21 06:01:38 PM PDT 24
Finished Jul 21 06:01:43 PM PDT 24
Peak memory 197480 kb
Host smart-fa912519-58ac-4db8-b4c9-eaab78c47be9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196550283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.2196550283
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.808034470
Short name T423
Test name
Test status
Simulation time 43763525 ps
CPU time 0.91 seconds
Started Jul 21 06:01:35 PM PDT 24
Finished Jul 21 06:01:36 PM PDT 24
Peak memory 197372 kb
Host smart-39c24893-9148-43c0-b4ab-120e6e9d6ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808034470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.808034470
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.454386767
Short name T329
Test name
Test status
Simulation time 56745758 ps
CPU time 0.82 seconds
Started Jul 21 06:01:32 PM PDT 24
Finished Jul 21 06:01:33 PM PDT 24
Peak memory 197496 kb
Host smart-8a12b9e2-1c57-4fe9-8721-d1737991e14d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454386767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.454386767
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.109108807
Short name T228
Test name
Test status
Simulation time 352015976 ps
CPU time 1.16 seconds
Started Jul 21 06:01:25 PM PDT 24
Finished Jul 21 06:01:28 PM PDT 24
Peak memory 198196 kb
Host smart-81c6db33-8d30-4de6-bbba-938937202e4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109108807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ran
dom_long_reg_writes_reg_reads.109108807
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3228184276
Short name T319
Test name
Test status
Simulation time 170611425 ps
CPU time 1.25 seconds
Started Jul 21 06:01:25 PM PDT 24
Finished Jul 21 06:01:26 PM PDT 24
Peak memory 196596 kb
Host smart-2290b2dc-fed6-4fb1-b503-d5e4587d3504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228184276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3228184276
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1100893401
Short name T498
Test name
Test status
Simulation time 129424859 ps
CPU time 1.23 seconds
Started Jul 21 06:01:27 PM PDT 24
Finished Jul 21 06:01:29 PM PDT 24
Peak memory 195828 kb
Host smart-251c3fea-1552-4bcd-8fed-37e911476de7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100893401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1100893401
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1394027672
Short name T357
Test name
Test status
Simulation time 3002688711 ps
CPU time 37.15 seconds
Started Jul 21 06:01:36 PM PDT 24
Finished Jul 21 06:02:14 PM PDT 24
Peak memory 198276 kb
Host smart-f477ca42-74df-497f-8419-4309a3a435f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394027672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1394027672
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_alert_test.1206711929
Short name T242
Test name
Test status
Simulation time 26263143 ps
CPU time 0.59 seconds
Started Jul 21 06:01:24 PM PDT 24
Finished Jul 21 06:01:25 PM PDT 24
Peak memory 194388 kb
Host smart-4d0bb833-909c-424d-bd92-656ee607e310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206711929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.1206711929
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1808031836
Short name T142
Test name
Test status
Simulation time 123943920 ps
CPU time 0.85 seconds
Started Jul 21 06:01:29 PM PDT 24
Finished Jul 21 06:01:30 PM PDT 24
Peak memory 195600 kb
Host smart-a929ef3d-4ba9-4534-bfb2-613c66e6f455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808031836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1808031836
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1196032795
Short name T270
Test name
Test status
Simulation time 247207298 ps
CPU time 6.4 seconds
Started Jul 21 06:01:37 PM PDT 24
Finished Jul 21 06:01:45 PM PDT 24
Peak memory 196492 kb
Host smart-cc6e5182-7bf3-4c00-a2c1-3d04fd489a1b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196032795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1196032795
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2404540949
Short name T323
Test name
Test status
Simulation time 67902800 ps
CPU time 0.87 seconds
Started Jul 21 06:01:24 PM PDT 24
Finished Jul 21 06:01:26 PM PDT 24
Peak memory 196836 kb
Host smart-f8329ce5-2bea-421a-a3a1-22608259ffc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404540949 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2404540949
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.2909436561
Short name T445
Test name
Test status
Simulation time 33968739 ps
CPU time 1 seconds
Started Jul 21 06:01:32 PM PDT 24
Finished Jul 21 06:01:33 PM PDT 24
Peak memory 196264 kb
Host smart-b9c90f2d-008c-4acc-95e9-c34939b4f554
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909436561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.2909436561
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3077261987
Short name T487
Test name
Test status
Simulation time 48622335 ps
CPU time 1.55 seconds
Started Jul 21 06:01:27 PM PDT 24
Finished Jul 21 06:01:29 PM PDT 24
Peak memory 196764 kb
Host smart-2012c457-9da3-4d29-8f2a-a6ff32f5228d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077261987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3077261987
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2600117026
Short name T619
Test name
Test status
Simulation time 85187864 ps
CPU time 1.04 seconds
Started Jul 21 06:01:24 PM PDT 24
Finished Jul 21 06:01:25 PM PDT 24
Peak memory 196912 kb
Host smart-dad46e6e-5ec1-48b1-8749-6dedf1ed5eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600117026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2600117026
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.2209774530
Short name T593
Test name
Test status
Simulation time 114127505 ps
CPU time 0.92 seconds
Started Jul 21 06:01:30 PM PDT 24
Finished Jul 21 06:01:31 PM PDT 24
Peak memory 196256 kb
Host smart-4a8c7a11-6330-493a-91f2-44779eed47b4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209774530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.2209774530
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.2592947903
Short name T200
Test name
Test status
Simulation time 214694902 ps
CPU time 5.01 seconds
Started Jul 21 06:01:30 PM PDT 24
Finished Jul 21 06:01:36 PM PDT 24
Peak memory 198260 kb
Host smart-391583d7-189e-4852-af28-a30505cef4a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592947903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.2592947903
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.3383504745
Short name T129
Test name
Test status
Simulation time 51469798 ps
CPU time 0.92 seconds
Started Jul 21 06:01:25 PM PDT 24
Finished Jul 21 06:01:26 PM PDT 24
Peak memory 196632 kb
Host smart-cced2947-ee35-40a4-8214-ef66f7e61d95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383504745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.3383504745
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.2858111359
Short name T153
Test name
Test status
Simulation time 41041088 ps
CPU time 1.3 seconds
Started Jul 21 06:01:30 PM PDT 24
Finished Jul 21 06:01:31 PM PDT 24
Peak memory 198232 kb
Host smart-30019488-35e9-4bae-85cc-74021192c4a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858111359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.2858111359
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.2149891733
Short name T346
Test name
Test status
Simulation time 29167761460 ps
CPU time 108.37 seconds
Started Jul 21 06:01:25 PM PDT 24
Finished Jul 21 06:03:15 PM PDT 24
Peak memory 198468 kb
Host smart-185e355a-f055-4577-a8d1-d472c0d5cf9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149891733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.2149891733
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.609253174
Short name T33
Test name
Test status
Simulation time 802475188897 ps
CPU time 2274.21 seconds
Started Jul 21 06:01:37 PM PDT 24
Finished Jul 21 06:39:33 PM PDT 24
Peak memory 198516 kb
Host smart-7c685720-a217-4c36-bb7c-7971ceb8f7ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=609253174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.609253174
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3847891044
Short name T147
Test name
Test status
Simulation time 12680731 ps
CPU time 0.57 seconds
Started Jul 21 06:01:26 PM PDT 24
Finished Jul 21 06:01:28 PM PDT 24
Peak memory 194096 kb
Host smart-1458c787-83d0-47d7-8101-fe22a0b7f7ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847891044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3847891044
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.879068299
Short name T543
Test name
Test status
Simulation time 16284729 ps
CPU time 0.65 seconds
Started Jul 21 06:01:25 PM PDT 24
Finished Jul 21 06:01:27 PM PDT 24
Peak memory 194920 kb
Host smart-bc800cab-5279-4218-b8d6-9591850c4b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879068299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.879068299
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.1575999379
Short name T378
Test name
Test status
Simulation time 1451095961 ps
CPU time 23.17 seconds
Started Jul 21 06:01:25 PM PDT 24
Finished Jul 21 06:01:50 PM PDT 24
Peak memory 196696 kb
Host smart-14ac33f2-560b-4427-8933-f630a05f557c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575999379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.1575999379
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.4063373052
Short name T191
Test name
Test status
Simulation time 69240410 ps
CPU time 0.75 seconds
Started Jul 21 06:01:33 PM PDT 24
Finished Jul 21 06:01:34 PM PDT 24
Peak memory 196040 kb
Host smart-0fe749bd-d4f4-4aba-895b-9d2379ef8a58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063373052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.4063373052
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1551673744
Short name T602
Test name
Test status
Simulation time 147899955 ps
CPU time 1.37 seconds
Started Jul 21 06:01:29 PM PDT 24
Finished Jul 21 06:01:31 PM PDT 24
Peak memory 198268 kb
Host smart-88362424-d718-4010-853b-c540580ef48b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551673744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1551673744
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.2932221429
Short name T57
Test name
Test status
Simulation time 232135568 ps
CPU time 2.35 seconds
Started Jul 21 06:01:25 PM PDT 24
Finished Jul 21 06:01:28 PM PDT 24
Peak memory 198196 kb
Host smart-6f86f9ad-a10e-4737-814a-52e45a5e6309
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932221429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.2932221429
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.638494687
Short name T265
Test name
Test status
Simulation time 215544600 ps
CPU time 2.45 seconds
Started Jul 21 06:01:28 PM PDT 24
Finished Jul 21 06:01:31 PM PDT 24
Peak memory 198176 kb
Host smart-a70fb0b8-5b79-498c-a7d2-010d5a770036
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638494687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger.
638494687
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3327962892
Short name T696
Test name
Test status
Simulation time 118403359 ps
CPU time 0.96 seconds
Started Jul 21 06:01:27 PM PDT 24
Finished Jul 21 06:01:29 PM PDT 24
Peak memory 196080 kb
Host smart-9530661e-e5e4-44cb-ab0c-48a2aa70a26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327962892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3327962892
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.2893391462
Short name T628
Test name
Test status
Simulation time 59413938 ps
CPU time 1.46 seconds
Started Jul 21 06:01:26 PM PDT 24
Finished Jul 21 06:01:29 PM PDT 24
Peak memory 197228 kb
Host smart-8906a4a1-b2c1-4089-b762-255c71513858
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893391462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.2893391462
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2036245807
Short name T73
Test name
Test status
Simulation time 105011134 ps
CPU time 4.84 seconds
Started Jul 21 06:01:28 PM PDT 24
Finished Jul 21 06:01:34 PM PDT 24
Peak memory 197908 kb
Host smart-360c356b-fb3f-4c9e-a9cb-63394fb607c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036245807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2036245807
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.3609093666
Short name T587
Test name
Test status
Simulation time 238804774 ps
CPU time 1.24 seconds
Started Jul 21 06:01:25 PM PDT 24
Finished Jul 21 06:01:28 PM PDT 24
Peak memory 196096 kb
Host smart-558ff25b-bfd2-48cd-a0c0-9576ed451769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609093666 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.3609093666
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2019516895
Short name T686
Test name
Test status
Simulation time 180924757 ps
CPU time 0.97 seconds
Started Jul 21 06:01:27 PM PDT 24
Finished Jul 21 06:01:29 PM PDT 24
Peak memory 196716 kb
Host smart-b85544c5-19b2-49bf-911c-1b09b1a6fc06
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019516895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2019516895
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2305487232
Short name T680
Test name
Test status
Simulation time 34181940975 ps
CPU time 90.79 seconds
Started Jul 21 06:01:30 PM PDT 24
Finished Jul 21 06:03:02 PM PDT 24
Peak memory 198284 kb
Host smart-9931a38e-0a30-4aef-afc7-1960e9da81a9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305487232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2305487232
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_alert_test.272533789
Short name T412
Test name
Test status
Simulation time 23093787 ps
CPU time 0.58 seconds
Started Jul 21 05:59:52 PM PDT 24
Finished Jul 21 05:59:53 PM PDT 24
Peak memory 194148 kb
Host smart-a455f81d-0e32-46d3-b688-54e8ca228093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272533789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.272533789
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2162289940
Short name T221
Test name
Test status
Simulation time 24619576 ps
CPU time 0.72 seconds
Started Jul 21 05:59:50 PM PDT 24
Finished Jul 21 05:59:51 PM PDT 24
Peak memory 194376 kb
Host smart-5fa92b52-7344-470a-9922-d4b185aaaff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162289940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2162289940
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.3866202632
Short name T127
Test name
Test status
Simulation time 460668662 ps
CPU time 16.61 seconds
Started Jul 21 05:59:59 PM PDT 24
Finished Jul 21 06:00:16 PM PDT 24
Peak memory 197196 kb
Host smart-ea0495bf-749c-4430-b582-1743f614d888
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866202632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.3866202632
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.3501685909
Short name T124
Test name
Test status
Simulation time 58666908 ps
CPU time 0.96 seconds
Started Jul 21 05:59:49 PM PDT 24
Finished Jul 21 05:59:51 PM PDT 24
Peak memory 197040 kb
Host smart-114915e9-9eea-4a39-84b4-505ad0302df1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501685909 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.3501685909
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.3991554328
Short name T16
Test name
Test status
Simulation time 590449816 ps
CPU time 1.22 seconds
Started Jul 21 05:59:48 PM PDT 24
Finished Jul 21 05:59:50 PM PDT 24
Peak memory 196844 kb
Host smart-1d040917-a7fc-4743-85b3-8346687bb971
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991554328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.3991554328
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2546270732
Short name T577
Test name
Test status
Simulation time 127800820 ps
CPU time 3.08 seconds
Started Jul 21 05:59:51 PM PDT 24
Finished Jul 21 05:59:54 PM PDT 24
Peak memory 198240 kb
Host smart-82897fc0-e1ff-4d99-ac37-7dcad03e8f25
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546270732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2546270732
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.1660160617
Short name T609
Test name
Test status
Simulation time 214665035 ps
CPU time 0.84 seconds
Started Jul 21 05:59:49 PM PDT 24
Finished Jul 21 05:59:51 PM PDT 24
Peak memory 194644 kb
Host smart-839ea964-36f6-4a7a-9e09-02ab92eef919
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660160617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
1660160617
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.3123390607
Short name T163
Test name
Test status
Simulation time 22528418 ps
CPU time 0.84 seconds
Started Jul 21 05:59:48 PM PDT 24
Finished Jul 21 05:59:50 PM PDT 24
Peak memory 196812 kb
Host smart-17f5cb2d-4b2f-4d1a-a822-fa36dc933d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123390607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.3123390607
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1335805171
Short name T697
Test name
Test status
Simulation time 73738504 ps
CPU time 0.7 seconds
Started Jul 21 05:59:49 PM PDT 24
Finished Jul 21 05:59:51 PM PDT 24
Peak memory 195584 kb
Host smart-a1bf9dce-f5a0-4830-ba15-0995420819a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335805171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1335805171
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3163327188
Short name T312
Test name
Test status
Simulation time 983927695 ps
CPU time 5.46 seconds
Started Jul 21 06:00:01 PM PDT 24
Finished Jul 21 06:00:08 PM PDT 24
Peak memory 198208 kb
Host smart-5e766ced-7f44-4efd-9d40-13498282ad4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163327188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3163327188
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1658489380
Short name T18
Test name
Test status
Simulation time 251481112 ps
CPU time 1.24 seconds
Started Jul 21 05:59:48 PM PDT 24
Finished Jul 21 05:59:51 PM PDT 24
Peak memory 195832 kb
Host smart-fb03689d-d1f4-4944-bf3b-88f0e5f67532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658489380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1658489380
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1867779653
Short name T282
Test name
Test status
Simulation time 605184504 ps
CPU time 1.07 seconds
Started Jul 21 05:59:52 PM PDT 24
Finished Jul 21 05:59:54 PM PDT 24
Peak memory 195808 kb
Host smart-cb318425-8655-41ae-8055-185e908fb370
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867779653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1867779653
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.2982722595
Short name T245
Test name
Test status
Simulation time 5322922277 ps
CPU time 56.82 seconds
Started Jul 21 05:59:51 PM PDT 24
Finished Jul 21 06:00:48 PM PDT 24
Peak memory 198336 kb
Host smart-97de6799-ac50-4c41-bf72-000b5a1998cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982722595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.2982722595
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1936577562
Short name T212
Test name
Test status
Simulation time 138093735 ps
CPU time 0.62 seconds
Started Jul 21 06:00:01 PM PDT 24
Finished Jul 21 06:00:03 PM PDT 24
Peak memory 194908 kb
Host smart-a9aae57f-9772-472d-a23c-f6078053c0bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936577562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1936577562
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3612412993
Short name T235
Test name
Test status
Simulation time 189926009 ps
CPU time 0.96 seconds
Started Jul 21 05:59:48 PM PDT 24
Finished Jul 21 05:59:50 PM PDT 24
Peak memory 196544 kb
Host smart-fefa74d6-e915-49e9-ad61-8e03c703918a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612412993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3612412993
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.463697358
Short name T659
Test name
Test status
Simulation time 2558168097 ps
CPU time 19.9 seconds
Started Jul 21 05:59:51 PM PDT 24
Finished Jul 21 06:00:12 PM PDT 24
Peak memory 196852 kb
Host smart-e108cb05-68c1-4b9d-adf5-6286ce27fb53
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463697358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.463697358
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1141652750
Short name T666
Test name
Test status
Simulation time 79229770 ps
CPU time 1.03 seconds
Started Jul 21 05:59:50 PM PDT 24
Finished Jul 21 05:59:52 PM PDT 24
Peak memory 196976 kb
Host smart-929cc3fa-c33a-42c0-8103-fbc2d6994054
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141652750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1141652750
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.2475760012
Short name T334
Test name
Test status
Simulation time 20655018 ps
CPU time 0.7 seconds
Started Jul 21 05:59:52 PM PDT 24
Finished Jul 21 05:59:53 PM PDT 24
Peak memory 194512 kb
Host smart-4453d083-5dbc-4655-b451-273321a0df9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475760012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.2475760012
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1672404766
Short name T452
Test name
Test status
Simulation time 52075927 ps
CPU time 2.19 seconds
Started Jul 21 05:59:54 PM PDT 24
Finished Jul 21 05:59:57 PM PDT 24
Peak memory 198236 kb
Host smart-e60d3c4f-e4ff-4d19-9c14-978659c3fe00
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672404766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1672404766
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.1941734705
Short name T695
Test name
Test status
Simulation time 516456402 ps
CPU time 3.25 seconds
Started Jul 21 05:59:48 PM PDT 24
Finished Jul 21 05:59:53 PM PDT 24
Peak memory 196056 kb
Host smart-7a1b64d5-f9ef-4d4d-bfeb-85da88896f49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941734705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
1941734705
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.4119842674
Short name T316
Test name
Test status
Simulation time 23042623 ps
CPU time 0.76 seconds
Started Jul 21 05:59:48 PM PDT 24
Finished Jul 21 05:59:50 PM PDT 24
Peak memory 195596 kb
Host smart-5df5f9ef-cbe3-415a-8e2a-a16706022ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119842674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.4119842674
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.915048980
Short name T197
Test name
Test status
Simulation time 115629822 ps
CPU time 1.15 seconds
Started Jul 21 05:59:49 PM PDT 24
Finished Jul 21 05:59:51 PM PDT 24
Peak memory 196712 kb
Host smart-cba276d9-d508-4fb6-9c7e-4b1575575f61
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915048980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.915048980
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3239388957
Short name T638
Test name
Test status
Simulation time 136285122 ps
CPU time 3.14 seconds
Started Jul 21 05:59:48 PM PDT 24
Finished Jul 21 05:59:52 PM PDT 24
Peak memory 198220 kb
Host smart-9bbba649-32f8-44c0-80aa-a56f2f7bea0f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239388957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3239388957
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.2645338250
Short name T309
Test name
Test status
Simulation time 85032567 ps
CPU time 1.23 seconds
Started Jul 21 05:59:47 PM PDT 24
Finished Jul 21 05:59:50 PM PDT 24
Peak memory 197048 kb
Host smart-797ba0f5-e3e6-4c5f-94ad-829997347876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645338250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.2645338250
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.936722310
Short name T118
Test name
Test status
Simulation time 466094990 ps
CPU time 1.3 seconds
Started Jul 21 05:59:53 PM PDT 24
Finished Jul 21 05:59:55 PM PDT 24
Peak memory 196480 kb
Host smart-2aff2ec2-f1a3-4a12-a4d5-37160453b352
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936722310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.936722310
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.894348365
Short name T406
Test name
Test status
Simulation time 36332816922 ps
CPU time 140.8 seconds
Started Jul 21 05:59:54 PM PDT 24
Finished Jul 21 06:02:15 PM PDT 24
Peak memory 198340 kb
Host smart-7b37803e-8be4-4c6b-ba69-1d06a7ebed8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894348365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.894348365
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.275916403
Short name T466
Test name
Test status
Simulation time 18925412848 ps
CPU time 285.78 seconds
Started Jul 21 06:00:01 PM PDT 24
Finished Jul 21 06:04:48 PM PDT 24
Peak memory 198464 kb
Host smart-2532d7ac-26d4-4143-9f34-d5e708eedc50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=275916403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.275916403
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.1242128417
Short name T521
Test name
Test status
Simulation time 33767328 ps
CPU time 0.58 seconds
Started Jul 21 05:59:56 PM PDT 24
Finished Jul 21 05:59:58 PM PDT 24
Peak memory 194188 kb
Host smart-8fbef987-321c-4016-9253-dd67ffed4389
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242128417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.1242128417
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.4015470307
Short name T661
Test name
Test status
Simulation time 51456832 ps
CPU time 0.91 seconds
Started Jul 21 05:59:53 PM PDT 24
Finished Jul 21 05:59:54 PM PDT 24
Peak memory 195960 kb
Host smart-ee81730c-923b-4c0e-8c17-786ec33b993b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015470307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.4015470307
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.915998971
Short name T403
Test name
Test status
Simulation time 480624505 ps
CPU time 14.8 seconds
Started Jul 21 05:59:56 PM PDT 24
Finished Jul 21 06:00:11 PM PDT 24
Peak memory 195704 kb
Host smart-6f1a82c8-d9d4-4719-b56c-4d33e817534f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915998971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.915998971
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.591952782
Short name T451
Test name
Test status
Simulation time 33707989 ps
CPU time 0.72 seconds
Started Jul 21 05:59:54 PM PDT 24
Finished Jul 21 05:59:55 PM PDT 24
Peak memory 194752 kb
Host smart-51ee14c9-ec52-4a7b-94a9-b3d82559c566
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591952782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.591952782
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.4184056966
Short name T146
Test name
Test status
Simulation time 28978062 ps
CPU time 1.01 seconds
Started Jul 21 05:59:54 PM PDT 24
Finished Jul 21 05:59:56 PM PDT 24
Peak memory 196312 kb
Host smart-c38dfd9f-b46a-4217-84fc-60eda00bd415
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184056966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.4184056966
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2969572395
Short name T310
Test name
Test status
Simulation time 453511936 ps
CPU time 2.13 seconds
Started Jul 21 05:59:56 PM PDT 24
Finished Jul 21 06:00:00 PM PDT 24
Peak memory 198296 kb
Host smart-8c5e7a6d-a6eb-4f9e-8095-ee66949d20b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969572395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2969572395
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1203555487
Short name T155
Test name
Test status
Simulation time 231139427 ps
CPU time 1.96 seconds
Started Jul 21 05:59:57 PM PDT 24
Finished Jul 21 06:00:00 PM PDT 24
Peak memory 196408 kb
Host smart-b174f51f-c976-4468-85fd-d752458267b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203555487 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1203555487
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.484662586
Short name T658
Test name
Test status
Simulation time 176854745 ps
CPU time 0.96 seconds
Started Jul 21 05:59:49 PM PDT 24
Finished Jul 21 05:59:51 PM PDT 24
Peak memory 196788 kb
Host smart-5aadec59-dfb0-4347-9749-411c2d7a5707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484662586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.484662586
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.4086263007
Short name T186
Test name
Test status
Simulation time 43251415 ps
CPU time 0.89 seconds
Started Jul 21 05:59:56 PM PDT 24
Finished Jul 21 05:59:57 PM PDT 24
Peak memory 196244 kb
Host smart-976ed3f9-e400-4694-a0cc-522540ff9ea9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086263007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.4086263007
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.1847432009
Short name T668
Test name
Test status
Simulation time 583303379 ps
CPU time 2 seconds
Started Jul 21 05:59:56 PM PDT 24
Finished Jul 21 05:59:59 PM PDT 24
Peak memory 198272 kb
Host smart-6c11b2f0-6ec6-45fa-9cd3-001f051ca532
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847432009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.1847432009
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.3458837608
Short name T160
Test name
Test status
Simulation time 190141892 ps
CPU time 1.1 seconds
Started Jul 21 05:59:52 PM PDT 24
Finished Jul 21 05:59:54 PM PDT 24
Peak memory 195852 kb
Host smart-f943c5d7-86e2-4a01-9e4f-996e956695a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458837608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.3458837608
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.1472939071
Short name T480
Test name
Test status
Simulation time 41103247 ps
CPU time 0.66 seconds
Started Jul 21 05:59:50 PM PDT 24
Finished Jul 21 05:59:52 PM PDT 24
Peak memory 195132 kb
Host smart-6f2ce7da-3a94-4b68-89df-99e6f526c0b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472939071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.1472939071
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2701232960
Short name T437
Test name
Test status
Simulation time 27440141158 ps
CPU time 85.78 seconds
Started Jul 21 05:59:56 PM PDT 24
Finished Jul 21 06:01:24 PM PDT 24
Peak memory 198380 kb
Host smart-6dd5afcf-0768-4119-a286-b08aba8fe600
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701232960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2701232960
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_alert_test.4288011992
Short name T631
Test name
Test status
Simulation time 76947916 ps
CPU time 0.56 seconds
Started Jul 21 05:59:56 PM PDT 24
Finished Jul 21 05:59:57 PM PDT 24
Peak memory 194132 kb
Host smart-4f53b800-7897-4d8f-9bb8-e7b41e686eea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288011992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.4288011992
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1585709447
Short name T634
Test name
Test status
Simulation time 15241928 ps
CPU time 0.67 seconds
Started Jul 21 05:59:56 PM PDT 24
Finished Jul 21 05:59:58 PM PDT 24
Peak memory 194036 kb
Host smart-d4759ddd-419b-48ce-9216-8057283f014f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585709447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1585709447
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.2843309003
Short name T374
Test name
Test status
Simulation time 806537936 ps
CPU time 25.15 seconds
Started Jul 21 05:59:57 PM PDT 24
Finished Jul 21 06:00:23 PM PDT 24
Peak memory 198216 kb
Host smart-12279f17-0349-4ab3-8837-a7b4170407d5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843309003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.2843309003
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.673575841
Short name T398
Test name
Test status
Simulation time 283472647 ps
CPU time 0.9 seconds
Started Jul 21 05:59:55 PM PDT 24
Finished Jul 21 05:59:56 PM PDT 24
Peak memory 196900 kb
Host smart-c966f715-750b-4ce9-bd52-49317d5092d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673575841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.673575841
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.3410679473
Short name T600
Test name
Test status
Simulation time 62566683 ps
CPU time 1.04 seconds
Started Jul 21 05:59:55 PM PDT 24
Finished Jul 21 05:59:57 PM PDT 24
Peak memory 196048 kb
Host smart-834a8140-5aab-4e58-b8c3-9c1e05378468
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410679473 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.3410679473
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1449326661
Short name T585
Test name
Test status
Simulation time 38656789 ps
CPU time 1.03 seconds
Started Jul 21 06:00:01 PM PDT 24
Finished Jul 21 06:00:03 PM PDT 24
Peak memory 196108 kb
Host smart-3b5ee3dd-1310-46fa-bd0c-b4ee38618c0b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449326661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1449326661
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.329623696
Short name T518
Test name
Test status
Simulation time 442414102 ps
CPU time 3.9 seconds
Started Jul 21 05:59:59 PM PDT 24
Finished Jul 21 06:00:03 PM PDT 24
Peak memory 197456 kb
Host smart-59e8140f-85c5-4103-a4d3-eb88376ffd45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329623696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.329623696
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2295437074
Short name T562
Test name
Test status
Simulation time 251997069 ps
CPU time 0.97 seconds
Started Jul 21 06:00:00 PM PDT 24
Finished Jul 21 06:00:01 PM PDT 24
Peak memory 197020 kb
Host smart-71e55d89-84f7-498d-a5f1-95a145afd0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295437074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2295437074
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3162400040
Short name T251
Test name
Test status
Simulation time 106861749 ps
CPU time 1.27 seconds
Started Jul 21 05:59:55 PM PDT 24
Finished Jul 21 05:59:57 PM PDT 24
Peak memory 197092 kb
Host smart-3ef80531-ed71-4ec2-b3d6-71db22179655
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162400040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3162400040
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2647861894
Short name T486
Test name
Test status
Simulation time 243778296 ps
CPU time 5.41 seconds
Started Jul 21 05:59:56 PM PDT 24
Finished Jul 21 06:00:03 PM PDT 24
Peak memory 198208 kb
Host smart-22af62a6-a407-4983-be71-f6e3118d4033
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647861894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2647861894
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.238209334
Short name T592
Test name
Test status
Simulation time 112479906 ps
CPU time 0.87 seconds
Started Jul 21 05:59:55 PM PDT 24
Finished Jul 21 05:59:57 PM PDT 24
Peak memory 196632 kb
Host smart-3780dc91-2d6b-40f5-bad6-d62158295bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238209334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.238209334
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.946220401
Short name T495
Test name
Test status
Simulation time 73931733 ps
CPU time 1.07 seconds
Started Jul 21 05:59:57 PM PDT 24
Finished Jul 21 05:59:59 PM PDT 24
Peak memory 196124 kb
Host smart-37c34373-7fc1-449f-8264-2ee026fe41ef
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946220401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.946220401
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.509937935
Short name T368
Test name
Test status
Simulation time 4767667304 ps
CPU time 34.84 seconds
Started Jul 21 06:00:00 PM PDT 24
Finished Jul 21 06:00:35 PM PDT 24
Peak memory 198384 kb
Host smart-e47fcb5d-82eb-4137-b976-a1c718888780
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509937935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gp
io_stress_all.509937935
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_alert_test.503349710
Short name T363
Test name
Test status
Simulation time 45743128 ps
CPU time 0.62 seconds
Started Jul 21 06:00:02 PM PDT 24
Finished Jul 21 06:00:03 PM PDT 24
Peak memory 194236 kb
Host smart-33d353bf-1ca0-4a5d-9851-d974e2b96172
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503349710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.503349710
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.1195522134
Short name T503
Test name
Test status
Simulation time 15810376 ps
CPU time 0.6 seconds
Started Jul 21 06:00:01 PM PDT 24
Finished Jul 21 06:00:02 PM PDT 24
Peak memory 194152 kb
Host smart-aa8b7df8-3c33-4600-8d83-13cdb0b2838d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195522134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.1195522134
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1540220206
Short name T343
Test name
Test status
Simulation time 734186619 ps
CPU time 18.66 seconds
Started Jul 21 06:00:01 PM PDT 24
Finished Jul 21 06:00:21 PM PDT 24
Peak memory 196496 kb
Host smart-85063d80-0f8d-4d44-afb9-f4685ee5bde7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540220206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1540220206
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.467195520
Short name T637
Test name
Test status
Simulation time 105955321 ps
CPU time 0.71 seconds
Started Jul 21 06:00:00 PM PDT 24
Finished Jul 21 06:00:02 PM PDT 24
Peak memory 194776 kb
Host smart-7bbfce3c-3d5b-47a0-9c46-1e0871279d2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467195520 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.467195520
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3817422087
Short name T497
Test name
Test status
Simulation time 38464241 ps
CPU time 0.68 seconds
Started Jul 21 06:00:00 PM PDT 24
Finished Jul 21 06:00:01 PM PDT 24
Peak memory 194436 kb
Host smart-361a0c9b-774a-4e60-9ddb-2824b0a4f8a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817422087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3817422087
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1761006680
Short name T31
Test name
Test status
Simulation time 101663459 ps
CPU time 1.23 seconds
Started Jul 21 06:00:04 PM PDT 24
Finished Jul 21 06:00:05 PM PDT 24
Peak memory 197952 kb
Host smart-dd656cf7-06eb-4a75-9fb2-91a55db821ec
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761006680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1761006680
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1886411740
Short name T353
Test name
Test status
Simulation time 2269576590 ps
CPU time 3.11 seconds
Started Jul 21 06:00:00 PM PDT 24
Finished Jul 21 06:00:03 PM PDT 24
Peak memory 198316 kb
Host smart-9c2c8994-1725-463b-acd2-f975ef5a78ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886411740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1886411740
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.343363401
Short name T355
Test name
Test status
Simulation time 32073621 ps
CPU time 1.29 seconds
Started Jul 21 06:00:01 PM PDT 24
Finished Jul 21 06:00:04 PM PDT 24
Peak memory 197352 kb
Host smart-3f706d1f-8723-4aec-95f3-2b2ef84e1ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343363401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.343363401
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.319305245
Short name T150
Test name
Test status
Simulation time 44848064 ps
CPU time 0.74 seconds
Started Jul 21 05:59:58 PM PDT 24
Finished Jul 21 05:59:59 PM PDT 24
Peak memory 196280 kb
Host smart-9d3fae75-074b-4f5f-ba57-00e38a1b5a85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319305245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.319305245
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.577229026
Short name T418
Test name
Test status
Simulation time 383461583 ps
CPU time 4.47 seconds
Started Jul 21 05:59:59 PM PDT 24
Finished Jul 21 06:00:05 PM PDT 24
Peak memory 198100 kb
Host smart-a188c986-f456-440a-81c9-595c99144724
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577229026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand
om_long_reg_writes_reg_reads.577229026
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.3189544218
Short name T615
Test name
Test status
Simulation time 394858439 ps
CPU time 1.05 seconds
Started Jul 21 05:59:57 PM PDT 24
Finished Jul 21 05:59:59 PM PDT 24
Peak memory 196060 kb
Host smart-f9a39c7b-ba99-4bcb-838e-801ed162c39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189544218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.3189544218
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.158554133
Short name T641
Test name
Test status
Simulation time 256287882 ps
CPU time 0.99 seconds
Started Jul 21 05:59:58 PM PDT 24
Finished Jul 21 05:59:59 PM PDT 24
Peak memory 196796 kb
Host smart-8293bb28-1432-427c-a864-6f6e580977bf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158554133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.158554133
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.314087475
Short name T482
Test name
Test status
Simulation time 20838830549 ps
CPU time 127.52 seconds
Started Jul 21 05:59:59 PM PDT 24
Finished Jul 21 06:02:08 PM PDT 24
Peak memory 198208 kb
Host smart-d3058367-264d-4126-ab72-b00888b9ad5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314087475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.314087475
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.766936990
Short name T933
Test name
Test status
Simulation time 159223859 ps
CPU time 1.22 seconds
Started Jul 21 04:22:50 PM PDT 24
Finished Jul 21 04:22:53 PM PDT 24
Peak memory 198396 kb
Host smart-1bd2c8bf-c82c-4304-97a1-ccfd06014d87
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=766936990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.766936990
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2068561770
Short name T908
Test name
Test status
Simulation time 53315803 ps
CPU time 1.04 seconds
Started Jul 21 04:21:01 PM PDT 24
Finished Jul 21 04:21:02 PM PDT 24
Peak memory 192068 kb
Host smart-5d9d379e-41a7-4439-8651-ab28c6adc34f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068561770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2068561770
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.690800697
Short name T914
Test name
Test status
Simulation time 34330383 ps
CPU time 0.91 seconds
Started Jul 21 04:20:53 PM PDT 24
Finished Jul 21 04:20:54 PM PDT 24
Peak memory 198236 kb
Host smart-e74f16b0-17e3-4947-b80c-022e566920fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=690800697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.690800697
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.51906916
Short name T864
Test name
Test status
Simulation time 26774697 ps
CPU time 0.85 seconds
Started Jul 21 04:22:35 PM PDT 24
Finished Jul 21 04:22:37 PM PDT 24
Peak memory 190720 kb
Host smart-25572bf0-63e5-48df-9bbd-4ac4bba0f82a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51906916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.51906916
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1673375201
Short name T863
Test name
Test status
Simulation time 91155311 ps
CPU time 1.22 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:23:09 PM PDT 24
Peak memory 190016 kb
Host smart-e5094ecd-cb5c-4984-838d-abd149070533
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1673375201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1673375201
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3404624349
Short name T858
Test name
Test status
Simulation time 69124140 ps
CPU time 1.06 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:22:56 PM PDT 24
Peak memory 191728 kb
Host smart-546e196b-b5a4-4fa5-9868-3696bafa664a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404624349 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3404624349
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.321653401
Short name T887
Test name
Test status
Simulation time 240885694 ps
CPU time 1.31 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:23:09 PM PDT 24
Peak memory 190124 kb
Host smart-24953e91-bfa1-4bd7-8131-59811a661871
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=321653401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.321653401
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.157924031
Short name T837
Test name
Test status
Simulation time 38154273 ps
CPU time 1.03 seconds
Started Jul 21 04:23:03 PM PDT 24
Finished Jul 21 04:23:05 PM PDT 24
Peak memory 197400 kb
Host smart-d9399f6c-c112-4095-95af-6c4667fcd7c7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157924031 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.157924031
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.1347563378
Short name T901
Test name
Test status
Simulation time 1152932373 ps
CPU time 1.3 seconds
Started Jul 21 04:23:08 PM PDT 24
Finished Jul 21 04:23:10 PM PDT 24
Peak memory 191700 kb
Host smart-f4daedcd-fdfd-42bf-aa72-2781e27e3fb6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1347563378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.1347563378
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3233469810
Short name T916
Test name
Test status
Simulation time 79953429 ps
CPU time 1.06 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:22:55 PM PDT 24
Peak memory 190840 kb
Host smart-f27d2721-ad9e-4bb4-976d-3abdc65d97d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233469810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3233469810
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.964187839
Short name T886
Test name
Test status
Simulation time 60345343 ps
CPU time 1.09 seconds
Started Jul 21 04:23:29 PM PDT 24
Finished Jul 21 04:23:31 PM PDT 24
Peak memory 192016 kb
Host smart-05abb695-390b-4965-852d-d2614fab0368
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=964187839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.964187839
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1797559099
Short name T924
Test name
Test status
Simulation time 96492403 ps
CPU time 1.45 seconds
Started Jul 21 04:20:02 PM PDT 24
Finished Jul 21 04:20:04 PM PDT 24
Peak memory 192148 kb
Host smart-64c2096e-67b1-4287-95a3-0face336ed81
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797559099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1797559099
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.2026373511
Short name T847
Test name
Test status
Simulation time 42895691 ps
CPU time 1.19 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:22:56 PM PDT 24
Peak memory 191712 kb
Host smart-54e3088f-5e8c-472e-a98b-56b1a7f97e61
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2026373511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.2026373511
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3334148941
Short name T894
Test name
Test status
Simulation time 29613827 ps
CPU time 0.75 seconds
Started Jul 21 04:22:50 PM PDT 24
Finished Jul 21 04:22:52 PM PDT 24
Peak memory 191752 kb
Host smart-afdc2b59-e427-469e-9f28-7fe59166b49c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334148941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3334148941
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.2190668200
Short name T899
Test name
Test status
Simulation time 47664567 ps
CPU time 0.85 seconds
Started Jul 21 04:23:30 PM PDT 24
Finished Jul 21 04:23:31 PM PDT 24
Peak memory 191824 kb
Host smart-636f27bb-8070-4603-a350-b7b3c338fca2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2190668200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.2190668200
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.469397957
Short name T861
Test name
Test status
Simulation time 54809383 ps
CPU time 1.06 seconds
Started Jul 21 04:19:01 PM PDT 24
Finished Jul 21 04:19:03 PM PDT 24
Peak memory 197700 kb
Host smart-049593a4-a7dc-4ffe-9769-e16606c34755
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469397957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.469397957
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.732878457
Short name T839
Test name
Test status
Simulation time 224159250 ps
CPU time 0.87 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:23:09 PM PDT 24
Peak memory 191972 kb
Host smart-ba5635ae-0af7-4745-be71-3d8a52bbdeb4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=732878457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.732878457
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2572469013
Short name T869
Test name
Test status
Simulation time 205810699 ps
CPU time 1.11 seconds
Started Jul 21 04:23:30 PM PDT 24
Finished Jul 21 04:23:32 PM PDT 24
Peak memory 191996 kb
Host smart-55fcfda1-14f8-49e4-8d7d-a1fc9e174313
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572469013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2572469013
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.535053093
Short name T923
Test name
Test status
Simulation time 298678813 ps
CPU time 1.07 seconds
Started Jul 21 04:23:30 PM PDT 24
Finished Jul 21 04:23:32 PM PDT 24
Peak memory 192032 kb
Host smart-f05b0f3f-3328-4f8f-b1ac-76e1721a038f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=535053093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.535053093
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.57511245
Short name T892
Test name
Test status
Simulation time 984714019 ps
CPU time 1.39 seconds
Started Jul 21 04:18:49 PM PDT 24
Finished Jul 21 04:18:51 PM PDT 24
Peak memory 198396 kb
Host smart-7d82d055-003c-443b-bc31-017a368ec7a6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57511245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.57511245
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.2174443678
Short name T835
Test name
Test status
Simulation time 350546323 ps
CPU time 1.23 seconds
Started Jul 21 04:23:14 PM PDT 24
Finished Jul 21 04:23:17 PM PDT 24
Peak memory 191140 kb
Host smart-80ebcebd-75e4-458e-8ec7-055f2204aeff
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2174443678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.2174443678
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3806925123
Short name T841
Test name
Test status
Simulation time 72649903 ps
CPU time 1.21 seconds
Started Jul 21 04:19:52 PM PDT 24
Finished Jul 21 04:19:53 PM PDT 24
Peak memory 192148 kb
Host smart-61377134-7939-4916-9c54-9688d9c16f01
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806925123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3806925123
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.390661270
Short name T921
Test name
Test status
Simulation time 297974578 ps
CPU time 1.05 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:22:55 PM PDT 24
Peak memory 190724 kb
Host smart-51e61c27-0bf4-4c47-9809-a87796c5640f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=390661270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.390661270
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.173178295
Short name T915
Test name
Test status
Simulation time 69147568 ps
CPU time 0.99 seconds
Started Jul 21 04:23:08 PM PDT 24
Finished Jul 21 04:23:10 PM PDT 24
Peak memory 192020 kb
Host smart-03206ce8-8b58-4fd6-a653-55184ebe167a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173178295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.173178295
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3080492551
Short name T920
Test name
Test status
Simulation time 38945334 ps
CPU time 1.1 seconds
Started Jul 21 04:22:35 PM PDT 24
Finished Jul 21 04:22:37 PM PDT 24
Peak memory 190844 kb
Host smart-9d66b5e1-87c1-4c68-82be-862d40a51a48
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3080492551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3080492551
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1187776239
Short name T893
Test name
Test status
Simulation time 340925578 ps
CPU time 1.23 seconds
Started Jul 21 04:22:37 PM PDT 24
Finished Jul 21 04:22:39 PM PDT 24
Peak memory 190300 kb
Host smart-88cbde9e-cbf5-46eb-944f-eb794e54d9ba
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187776239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1187776239
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.231563103
Short name T904
Test name
Test status
Simulation time 17337509 ps
CPU time 0.69 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:22:53 PM PDT 24
Peak memory 190988 kb
Host smart-3ed876ee-ae9e-421d-a3ed-dff245321142
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=231563103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.231563103
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1286844266
Short name T843
Test name
Test status
Simulation time 33308084 ps
CPU time 1.02 seconds
Started Jul 21 04:20:28 PM PDT 24
Finished Jul 21 04:20:30 PM PDT 24
Peak memory 192036 kb
Host smart-7caf0cb3-1378-486d-bc54-2598e10913c5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286844266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1286844266
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.1191452696
Short name T930
Test name
Test status
Simulation time 54776565 ps
CPU time 1.44 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:22:56 PM PDT 24
Peak memory 191652 kb
Host smart-d9e7e927-75e0-4bb0-ab5d-891bf10284c7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1191452696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.1191452696
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4138837140
Short name T873
Test name
Test status
Simulation time 44491110 ps
CPU time 0.8 seconds
Started Jul 21 04:23:30 PM PDT 24
Finished Jul 21 04:23:32 PM PDT 24
Peak memory 191824 kb
Host smart-b0ad384f-0854-4e63-ae8b-1d2d65ceb515
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138837140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4138837140
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2690107870
Short name T883
Test name
Test status
Simulation time 104817375 ps
CPU time 0.85 seconds
Started Jul 21 04:23:30 PM PDT 24
Finished Jul 21 04:23:31 PM PDT 24
Peak memory 191824 kb
Host smart-9c86f79a-1171-48ae-97ba-a7092582a649
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2690107870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2690107870
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3150511632
Short name T918
Test name
Test status
Simulation time 29476608 ps
CPU time 0.78 seconds
Started Jul 21 04:21:36 PM PDT 24
Finished Jul 21 04:21:37 PM PDT 24
Peak memory 191868 kb
Host smart-4f33f430-bafc-41fa-96f4-538dffa556a2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150511632 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3150511632
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1499762882
Short name T888
Test name
Test status
Simulation time 94799930 ps
CPU time 1.25 seconds
Started Jul 21 04:18:58 PM PDT 24
Finished Jul 21 04:19:00 PM PDT 24
Peak memory 192368 kb
Host smart-eff2052a-6488-4eb6-987b-95e057c81b9c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1499762882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1499762882
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.363097134
Short name T875
Test name
Test status
Simulation time 94251084 ps
CPU time 1.43 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:22:56 PM PDT 24
Peak memory 196800 kb
Host smart-ee4ca9fc-fd36-4fb1-949a-d1e242f94243
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363097134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.363097134
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.3997616155
Short name T845
Test name
Test status
Simulation time 67977907 ps
CPU time 1.14 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:23:19 PM PDT 24
Peak memory 192028 kb
Host smart-db06e552-8db6-442f-b030-fa59f63ce920
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3997616155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.3997616155
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2002949835
Short name T903
Test name
Test status
Simulation time 127475126 ps
CPU time 1.02 seconds
Started Jul 21 04:21:21 PM PDT 24
Finished Jul 21 04:21:22 PM PDT 24
Peak memory 192068 kb
Host smart-7f76ed4a-3c2a-4971-a742-aac6a3964e8d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002949835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2002949835
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.3537791562
Short name T911
Test name
Test status
Simulation time 336614910 ps
CPU time 1.46 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:22:56 PM PDT 24
Peak memory 198284 kb
Host smart-92e35767-6788-4186-968f-bea2a8901c8a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3537791562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.3537791562
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1388261201
Short name T919
Test name
Test status
Simulation time 87133991 ps
CPU time 0.81 seconds
Started Jul 21 04:23:08 PM PDT 24
Finished Jul 21 04:23:10 PM PDT 24
Peak memory 191820 kb
Host smart-1d8962f1-d453-49a4-b63a-b357c02b5fd8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388261201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1388261201
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3628870971
Short name T877
Test name
Test status
Simulation time 82319721 ps
CPU time 1.12 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:22:57 PM PDT 24
Peak memory 191976 kb
Host smart-b203c1ab-140b-4c7d-b7ff-0a025a49dba1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3628870971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3628870971
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3392433557
Short name T927
Test name
Test status
Simulation time 68455469 ps
CPU time 0.91 seconds
Started Jul 21 04:22:51 PM PDT 24
Finished Jul 21 04:22:53 PM PDT 24
Peak memory 191644 kb
Host smart-67fe9179-141a-4b20-a978-3974e9722cfd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392433557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3392433557
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1926595841
Short name T867
Test name
Test status
Simulation time 54049908 ps
CPU time 0.81 seconds
Started Jul 21 04:22:51 PM PDT 24
Finished Jul 21 04:22:52 PM PDT 24
Peak memory 196316 kb
Host smart-d81ae1db-fd9b-4424-9ee2-b7bb2c22cb98
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1926595841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1926595841
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1463029991
Short name T850
Test name
Test status
Simulation time 61601363 ps
CPU time 0.81 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:23:20 PM PDT 24
Peak memory 191828 kb
Host smart-829db429-aeff-43ac-bf27-404325930985
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463029991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1463029991
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3504005250
Short name T917
Test name
Test status
Simulation time 47908828 ps
CPU time 0.83 seconds
Started Jul 21 04:19:41 PM PDT 24
Finished Jul 21 04:19:43 PM PDT 24
Peak memory 192192 kb
Host smart-11149a5b-ad00-4212-aaee-4df3b4fbbc07
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3504005250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3504005250
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1990872217
Short name T842
Test name
Test status
Simulation time 50396909 ps
CPU time 1.28 seconds
Started Jul 21 04:23:18 PM PDT 24
Finished Jul 21 04:23:20 PM PDT 24
Peak memory 198352 kb
Host smart-c180f80e-c11e-4d96-9fe1-7f584b970057
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990872217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1990872217
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2744975254
Short name T905
Test name
Test status
Simulation time 32600111 ps
CPU time 1.04 seconds
Started Jul 21 04:23:21 PM PDT 24
Finished Jul 21 04:23:23 PM PDT 24
Peak memory 198376 kb
Host smart-4ef32fa1-dbbb-4bba-b3ee-718ebd353d4b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2744975254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2744975254
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3804523791
Short name T860
Test name
Test status
Simulation time 81099256 ps
CPU time 1.03 seconds
Started Jul 21 04:21:19 PM PDT 24
Finished Jul 21 04:21:21 PM PDT 24
Peak memory 191996 kb
Host smart-7f326033-5172-4b09-9c5e-33e18fe8b13f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804523791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3804523791
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.3672998401
Short name T836
Test name
Test status
Simulation time 47885192 ps
CPU time 1.37 seconds
Started Jul 21 04:21:51 PM PDT 24
Finished Jul 21 04:21:53 PM PDT 24
Peak memory 198440 kb
Host smart-0e0ac029-651b-4673-b055-d91f203efdd4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3672998401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.3672998401
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.387219752
Short name T902
Test name
Test status
Simulation time 71644329 ps
CPU time 0.84 seconds
Started Jul 21 04:23:02 PM PDT 24
Finished Jul 21 04:23:03 PM PDT 24
Peak memory 195768 kb
Host smart-326d80df-1a5f-405d-8197-2502c4fb57ed
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387219752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.387219752
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.3289143683
Short name T834
Test name
Test status
Simulation time 104324139 ps
CPU time 1.45 seconds
Started Jul 21 04:20:38 PM PDT 24
Finished Jul 21 04:20:39 PM PDT 24
Peak memory 198404 kb
Host smart-bcf352b2-4224-4bfe-8aef-0f3f13b10352
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3289143683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.3289143683
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3024509703
Short name T848
Test name
Test status
Simulation time 598714049 ps
CPU time 1.04 seconds
Started Jul 21 04:23:01 PM PDT 24
Finished Jul 21 04:23:03 PM PDT 24
Peak memory 190992 kb
Host smart-0fe43f02-befd-4464-a3d7-a0b4ba3ee294
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024509703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3024509703
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4170196945
Short name T896
Test name
Test status
Simulation time 179966075 ps
CPU time 1 seconds
Started Jul 21 04:20:05 PM PDT 24
Finished Jul 21 04:20:06 PM PDT 24
Peak memory 197792 kb
Host smart-cf5d398a-3d50-4bef-873c-3ab3144179f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4170196945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.4170196945
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.963579094
Short name T932
Test name
Test status
Simulation time 186554113 ps
CPU time 1.06 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:22:56 PM PDT 24
Peak memory 191948 kb
Host smart-2f42063b-9095-4fdd-b9e2-ec22d1e1d372
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963579094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.963579094
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.1254642060
Short name T865
Test name
Test status
Simulation time 181935857 ps
CPU time 0.82 seconds
Started Jul 21 04:22:51 PM PDT 24
Finished Jul 21 04:22:52 PM PDT 24
Peak memory 191824 kb
Host smart-3c5a0ed1-b5c1-4c7b-9de5-a837e97eebb1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1254642060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.1254642060
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3242177113
Short name T913
Test name
Test status
Simulation time 207732306 ps
CPU time 0.98 seconds
Started Jul 21 04:22:36 PM PDT 24
Finished Jul 21 04:22:38 PM PDT 24
Peak memory 190992 kb
Host smart-d82d95b5-77a1-4fd9-bf2e-445ff00f9214
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242177113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3242177113
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.1460061294
Short name T851
Test name
Test status
Simulation time 117120681 ps
CPU time 0.96 seconds
Started Jul 21 04:22:54 PM PDT 24
Finished Jul 21 04:22:57 PM PDT 24
Peak memory 191840 kb
Host smart-d4d0a632-37a7-4263-9464-3d07f4e7c024
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1460061294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.1460061294
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1105243424
Short name T890
Test name
Test status
Simulation time 49469452 ps
CPU time 1.25 seconds
Started Jul 21 04:19:45 PM PDT 24
Finished Jul 21 04:19:47 PM PDT 24
Peak memory 198760 kb
Host smart-4696f8f8-b4ff-4309-bdd2-a2a5a259503f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105243424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1105243424
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.1298009879
Short name T870
Test name
Test status
Simulation time 230995937 ps
CPU time 1.43 seconds
Started Jul 21 04:20:16 PM PDT 24
Finished Jul 21 04:20:18 PM PDT 24
Peak memory 198500 kb
Host smart-5d5ad9ce-4e13-4000-a04b-bfd1bb19aba5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1298009879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.1298009879
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3258323366
Short name T880
Test name
Test status
Simulation time 62702586 ps
CPU time 0.75 seconds
Started Jul 21 04:22:36 PM PDT 24
Finished Jul 21 04:22:38 PM PDT 24
Peak memory 189992 kb
Host smart-60c7b194-db7c-4e27-9659-20423c2051db
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258323366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3258323366
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.1303551381
Short name T897
Test name
Test status
Simulation time 94814528 ps
CPU time 0.94 seconds
Started Jul 21 04:22:52 PM PDT 24
Finished Jul 21 04:22:55 PM PDT 24
Peak memory 196372 kb
Host smart-9502b7b6-561b-4119-9da3-d1cbc2fe5329
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1303551381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.1303551381
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3947332721
Short name T882
Test name
Test status
Simulation time 133084713 ps
CPU time 0.77 seconds
Started Jul 21 04:22:50 PM PDT 24
Finished Jul 21 04:22:52 PM PDT 24
Peak memory 196504 kb
Host smart-c5a85e93-2c6b-4715-a8f1-e4c3e8ff3084
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947332721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3947332721
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.3287495735
Short name T856
Test name
Test status
Simulation time 31693966 ps
CPU time 0.91 seconds
Started Jul 21 04:22:37 PM PDT 24
Finished Jul 21 04:22:39 PM PDT 24
Peak memory 190716 kb
Host smart-5df2c78e-6219-4f4c-ab67-2604d58456c5
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3287495735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.3287495735
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2879695392
Short name T889
Test name
Test status
Simulation time 222107296 ps
CPU time 0.77 seconds
Started Jul 21 04:22:36 PM PDT 24
Finished Jul 21 04:22:38 PM PDT 24
Peak memory 190300 kb
Host smart-bfbf7ed6-d2cd-4251-acd1-0e3bb2cb98c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879695392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2879695392
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.84739206
Short name T931
Test name
Test status
Simulation time 29138252 ps
CPU time 0.75 seconds
Started Jul 21 04:22:38 PM PDT 24
Finished Jul 21 04:22:39 PM PDT 24
Peak memory 190724 kb
Host smart-c85083c7-3d26-4f19-9d4d-b608c64c9ff0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=84739206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.84739206
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3476172622
Short name T846
Test name
Test status
Simulation time 62017054 ps
CPU time 1.22 seconds
Started Jul 21 04:18:50 PM PDT 24
Finished Jul 21 04:18:52 PM PDT 24
Peak memory 191864 kb
Host smart-af63fbba-c290-47b3-841c-09f7ca541e57
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476172622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3476172622
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.3535141114
Short name T878
Test name
Test status
Simulation time 23635826 ps
CPU time 0.78 seconds
Started Jul 21 04:20:39 PM PDT 24
Finished Jul 21 04:20:40 PM PDT 24
Peak memory 196492 kb
Host smart-1b9bb41d-80fe-49f8-99af-6f631b44a3fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3535141114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.3535141114
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1164502432
Short name T929
Test name
Test status
Simulation time 52147463 ps
CPU time 1.26 seconds
Started Jul 21 04:23:08 PM PDT 24
Finished Jul 21 04:23:10 PM PDT 24
Peak memory 191992 kb
Host smart-65c293ed-9a4a-4abe-ba1b-df1b0092cb12
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164502432 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1164502432
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.1544265961
Short name T900
Test name
Test status
Simulation time 29254944 ps
CPU time 0.66 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:23:08 PM PDT 24
Peak memory 191816 kb
Host smart-0402976a-ea65-4a0c-9a45-669ec931c7d9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1544265961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.1544265961
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.157828386
Short name T876
Test name
Test status
Simulation time 49249704 ps
CPU time 0.98 seconds
Started Jul 21 04:22:53 PM PDT 24
Finished Jul 21 04:22:56 PM PDT 24
Peak memory 197020 kb
Host smart-cc13635e-190b-4ae4-9e59-6abeadef1019
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157828386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.157828386
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1930178240
Short name T885
Test name
Test status
Simulation time 188767635 ps
CPU time 1.11 seconds
Started Jul 21 04:22:37 PM PDT 24
Finished Jul 21 04:22:40 PM PDT 24
Peak memory 196532 kb
Host smart-ed077df6-113e-4232-9ac5-40faeaa4af27
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1930178240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1930178240
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1347518435
Short name T871
Test name
Test status
Simulation time 609032040 ps
CPU time 1.34 seconds
Started Jul 21 04:22:37 PM PDT 24
Finished Jul 21 04:22:39 PM PDT 24
Peak memory 190148 kb
Host smart-a9019d05-f1a6-431b-87a8-387bdcdffbbe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347518435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1347518435
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.776382991
Short name T891
Test name
Test status
Simulation time 63519215 ps
CPU time 0.9 seconds
Started Jul 21 04:22:36 PM PDT 24
Finished Jul 21 04:22:38 PM PDT 24
Peak memory 195204 kb
Host smart-a4d8dd30-ae5c-4522-b664-892a8ca39955
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=776382991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.776382991
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.769228184
Short name T907
Test name
Test status
Simulation time 39127799 ps
CPU time 1.04 seconds
Started Jul 21 04:20:25 PM PDT 24
Finished Jul 21 04:20:26 PM PDT 24
Peak memory 192408 kb
Host smart-37374ee6-b175-4b63-a4b0-8720fae915a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769228184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.769228184
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3262715488
Short name T868
Test name
Test status
Simulation time 38129180 ps
CPU time 1.03 seconds
Started Jul 21 04:23:42 PM PDT 24
Finished Jul 21 04:23:44 PM PDT 24
Peak memory 198288 kb
Host smart-31e9cc20-f7ff-4c2c-89fb-cefb76247066
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3262715488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3262715488
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1673708811
Short name T853
Test name
Test status
Simulation time 121815919 ps
CPU time 1.15 seconds
Started Jul 21 04:23:41 PM PDT 24
Finished Jul 21 04:23:43 PM PDT 24
Peak memory 192040 kb
Host smart-ed892594-a1bc-45f4-9615-f59e4187812c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673708811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1673708811
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2110420684
Short name T852
Test name
Test status
Simulation time 796339493 ps
CPU time 0.91 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:23:42 PM PDT 24
Peak memory 192004 kb
Host smart-e8951855-ee70-4b06-8c86-e8c9308b9b86
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2110420684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2110420684
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2541813946
Short name T844
Test name
Test status
Simulation time 65547879 ps
CPU time 1.3 seconds
Started Jul 21 04:23:47 PM PDT 24
Finished Jul 21 04:23:48 PM PDT 24
Peak memory 198396 kb
Host smart-73c14f02-5fee-41ba-98c7-2e3d058b56c4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541813946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2541813946
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.4136333599
Short name T926
Test name
Test status
Simulation time 65831923 ps
CPU time 1.02 seconds
Started Jul 21 04:23:56 PM PDT 24
Finished Jul 21 04:23:57 PM PDT 24
Peak memory 192004 kb
Host smart-64f8c456-d926-4b8d-a3c8-8d0eeb9f74b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4136333599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.4136333599
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2453376958
Short name T859
Test name
Test status
Simulation time 26184367 ps
CPU time 0.87 seconds
Started Jul 21 04:23:47 PM PDT 24
Finished Jul 21 04:23:48 PM PDT 24
Peak memory 191844 kb
Host smart-524f691a-9d8d-4d3d-920d-d4975b1dfc36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453376958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2453376958
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3451537308
Short name T854
Test name
Test status
Simulation time 274024704 ps
CPU time 1.31 seconds
Started Jul 21 04:23:55 PM PDT 24
Finished Jul 21 04:23:57 PM PDT 24
Peak memory 192004 kb
Host smart-4376fbbf-ae78-4d1e-88e2-dbc14283c901
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3451537308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3451537308
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1069626967
Short name T884
Test name
Test status
Simulation time 120589300 ps
CPU time 0.83 seconds
Started Jul 21 04:23:57 PM PDT 24
Finished Jul 21 04:23:58 PM PDT 24
Peak memory 196236 kb
Host smart-79fdaca7-c0b3-43f8-a58b-e346dc7d6332
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069626967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1069626967
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.4121158938
Short name T912
Test name
Test status
Simulation time 112627097 ps
CPU time 0.9 seconds
Started Jul 21 04:23:40 PM PDT 24
Finished Jul 21 04:23:42 PM PDT 24
Peak memory 197576 kb
Host smart-728bf95c-7efa-4332-a60a-4a3c5bc99963
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4121158938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.4121158938
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.630944830
Short name T872
Test name
Test status
Simulation time 33872028 ps
CPU time 0.88 seconds
Started Jul 21 04:23:49 PM PDT 24
Finished Jul 21 04:23:51 PM PDT 24
Peak memory 196456 kb
Host smart-5cadc483-6ef3-4ea6-9a94-37537f8246c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630944830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.630944830
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2358123726
Short name T925
Test name
Test status
Simulation time 125286407 ps
CPU time 1.02 seconds
Started Jul 21 04:23:51 PM PDT 24
Finished Jul 21 04:23:52 PM PDT 24
Peak memory 191680 kb
Host smart-12a43f5b-0eaa-424b-a01a-072071d265fd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2358123726 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2358123726
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3307921070
Short name T857
Test name
Test status
Simulation time 193000721 ps
CPU time 1.29 seconds
Started Jul 21 04:24:02 PM PDT 24
Finished Jul 21 04:24:03 PM PDT 24
Peak memory 198376 kb
Host smart-1491bbc8-1543-4179-b51b-192d7b7c3f37
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307921070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3307921070
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2946559142
Short name T881
Test name
Test status
Simulation time 40826547 ps
CPU time 1 seconds
Started Jul 21 04:23:52 PM PDT 24
Finished Jul 21 04:23:53 PM PDT 24
Peak memory 191732 kb
Host smart-cfcc43bc-7963-41f9-9541-460c68437fed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2946559142 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2946559142
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.837337181
Short name T874
Test name
Test status
Simulation time 46040525 ps
CPU time 0.97 seconds
Started Jul 21 04:23:56 PM PDT 24
Finished Jul 21 04:23:58 PM PDT 24
Peak memory 191816 kb
Host smart-d66799ab-a866-42ec-b78e-bd0edf3afc8a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837337181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.837337181
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3205527255
Short name T862
Test name
Test status
Simulation time 32560548 ps
CPU time 0.97 seconds
Started Jul 21 04:23:48 PM PDT 24
Finished Jul 21 04:23:50 PM PDT 24
Peak memory 191968 kb
Host smart-580e09c1-8813-4108-9935-751654cbda8f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3205527255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3205527255
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2152602806
Short name T866
Test name
Test status
Simulation time 56127174 ps
CPU time 1 seconds
Started Jul 21 04:23:57 PM PDT 24
Finished Jul 21 04:23:59 PM PDT 24
Peak memory 191824 kb
Host smart-9ff76b85-7122-4f0a-bfe4-eaddd1675364
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152602806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2152602806
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.3739165934
Short name T895
Test name
Test status
Simulation time 56923044 ps
CPU time 1.06 seconds
Started Jul 21 04:23:54 PM PDT 24
Finished Jul 21 04:23:55 PM PDT 24
Peak memory 191928 kb
Host smart-278e2a37-f78b-4b8c-a030-261174dfe648
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3739165934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.3739165934
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1900375373
Short name T909
Test name
Test status
Simulation time 191502077 ps
CPU time 1.35 seconds
Started Jul 21 04:23:57 PM PDT 24
Finished Jul 21 04:23:59 PM PDT 24
Peak memory 198336 kb
Host smart-8d7e7e71-8e34-4fa2-9770-d096e16ce734
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900375373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1900375373
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.1636976419
Short name T855
Test name
Test status
Simulation time 35210408 ps
CPU time 1.02 seconds
Started Jul 21 04:18:49 PM PDT 24
Finished Jul 21 04:18:51 PM PDT 24
Peak memory 196296 kb
Host smart-cb4aac2c-046b-42fd-a197-c23b30f578f9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1636976419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.1636976419
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.415270809
Short name T840
Test name
Test status
Simulation time 69199971 ps
CPU time 0.95 seconds
Started Jul 21 04:20:28 PM PDT 24
Finished Jul 21 04:20:29 PM PDT 24
Peak memory 192028 kb
Host smart-69799a81-c07a-4474-8dfe-69c32dd49a00
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415270809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.415270809
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2332167342
Short name T879
Test name
Test status
Simulation time 127711903 ps
CPU time 0.78 seconds
Started Jul 21 04:23:37 PM PDT 24
Finished Jul 21 04:23:38 PM PDT 24
Peak memory 191564 kb
Host smart-040deacf-a912-4b1e-964a-5422dcf8bc15
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2332167342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2332167342
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.568217674
Short name T922
Test name
Test status
Simulation time 66283550 ps
CPU time 1.21 seconds
Started Jul 21 04:20:22 PM PDT 24
Finished Jul 21 04:20:24 PM PDT 24
Peak memory 192140 kb
Host smart-71813095-ff6a-46e9-8363-5b49cdfd6df5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568217674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.568217674
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.847084721
Short name T910
Test name
Test status
Simulation time 61678442 ps
CPU time 0.92 seconds
Started Jul 21 04:22:37 PM PDT 24
Finished Jul 21 04:22:39 PM PDT 24
Peak memory 191668 kb
Host smart-045329fd-3d36-4f5c-8693-8ccd8a6c6de1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=847084721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.847084721
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1718531222
Short name T838
Test name
Test status
Simulation time 40514058 ps
CPU time 1.17 seconds
Started Jul 21 04:19:01 PM PDT 24
Finished Jul 21 04:19:03 PM PDT 24
Peak memory 191980 kb
Host smart-f9ee362c-3123-43dd-960b-c99a24fe817d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718531222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1718531222
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3975453891
Short name T898
Test name
Test status
Simulation time 50153180 ps
CPU time 1.06 seconds
Started Jul 21 04:22:37 PM PDT 24
Finished Jul 21 04:22:39 PM PDT 24
Peak memory 195784 kb
Host smart-f394d41b-3624-47b1-a418-c6d58bfca9a7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3975453891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3975453891
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.782342911
Short name T849
Test name
Test status
Simulation time 42461066 ps
CPU time 1.05 seconds
Started Jul 21 04:20:13 PM PDT 24
Finished Jul 21 04:20:14 PM PDT 24
Peak memory 192140 kb
Host smart-02d21946-adde-427c-80d5-db8d60577d2c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782342911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.782342911
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.1076482786
Short name T928
Test name
Test status
Simulation time 87436947 ps
CPU time 1.17 seconds
Started Jul 21 04:19:48 PM PDT 24
Finished Jul 21 04:19:50 PM PDT 24
Peak memory 192068 kb
Host smart-f22c1249-11f5-411a-a058-e53b43655e3b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1076482786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.1076482786
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.552557352
Short name T906
Test name
Test status
Simulation time 64049315 ps
CPU time 1.31 seconds
Started Jul 21 04:23:07 PM PDT 24
Finished Jul 21 04:23:09 PM PDT 24
Peak memory 190432 kb
Host smart-0c1e7da5-73fc-4ce2-adca-07fc32fd59cc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552557352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.552557352
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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