Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	4256651	1			T1	680		T2	372		T11	1
all_pins[1]	4256651	1			T1	680		T2	372		T11	1
all_pins[2]	4256651	1			T1	680		T2	372		T11	1
all_pins[3]	4256651	1			T1	680		T2	372		T11	1
all_pins[4]	4256651	1			T1	680		T2	372		T11	1
all_pins[5]	4256651	1			T1	680		T2	372		T11	1
all_pins[6]	4256651	1			T1	680		T2	372		T11	1
all_pins[7]	4256651	1			T1	680		T2	372		T11	1
all_pins[8]	4256651	1			T1	680		T2	372		T11	1
all_pins[9]	4256651	1			T1	680		T2	372		T11	1
all_pins[10]	4256651	1			T1	680		T2	372		T11	1
all_pins[11]	4256651	1			T1	680		T2	372		T11	1
all_pins[12]	4256651	1			T1	680		T2	372		T11	1
all_pins[13]	4256651	1			T1	680		T2	372		T11	1
all_pins[14]	4256651	1			T1	680		T2	372		T11	1
all_pins[15]	4256651	1			T1	680		T2	372		T11	1
all_pins[16]	4256651	1			T1	680		T2	372		T11	1
all_pins[17]	4256651	1			T1	680		T2	372		T11	1
all_pins[18]	4256651	1			T1	680		T2	372		T11	1
all_pins[19]	4256651	1			T1	680		T2	372		T11	1
all_pins[20]	4256651	1			T1	680		T2	372		T11	1
all_pins[21]	4256651	1			T1	680		T2	372		T11	1
all_pins[22]	4256651	1			T1	680		T2	372		T11	1
all_pins[23]	4256651	1			T1	680		T2	372		T11	1
all_pins[24]	4256651	1			T1	680		T2	372		T11	1
all_pins[25]	4256651	1			T1	680		T2	372		T11	1
all_pins[26]	4256651	1			T1	680		T2	372		T11	1
all_pins[27]	4256651	1			T1	680		T2	372		T11	1
all_pins[28]	4256651	1			T1	680		T2	372		T11	1
all_pins[29]	4256651	1			T1	680		T2	372		T11	1
all_pins[30]	4256651	1			T1	680		T2	372		T11	1
all_pins[31]	4256651	1			T1	680		T2	372		T11	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	84645993	1			T1	13190		T2	7512		T11	32
values[0x1]	51566839	1			T1	8570		T2	4392		T12	1077
transitions[0x0=>0x1]	30915572	1			T1	5044		T2	2599		T12	533
transitions[0x1=>0x0]	30915396	1			T1	5043		T2	2599		T12	532

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2646933	1			T1	329		T2	228		T11	1
all_pins[0]	values[0x1]	1609718	1			T1	351		T2	144		T12	34
all_pins[0]	transitions[0x0=>0x1]	996584	1			T1	227		T2	101		T12	17
all_pins[0]	transitions[0x1=>0x0]	998283	1			T1	119		T2	86		T12	16
all_pins[1]	values[0x0]	2641259	1			T1	355		T2	227		T11	1
all_pins[1]	values[0x1]	1615392	1			T1	325		T2	145		T12	33
all_pins[1]	transitions[0x0=>0x1]	968961	1			T1	155		T2	88		T12	19
all_pins[1]	transitions[0x1=>0x0]	963287	1			T1	181		T2	87		T12	20
all_pins[2]	values[0x0]	2643891	1			T1	427		T2	262		T11	1
all_pins[2]	values[0x1]	1612760	1			T1	253		T2	110		T12	39
all_pins[2]	transitions[0x0=>0x1]	965433	1			T1	146		T2	53		T12	21
all_pins[2]	transitions[0x1=>0x0]	968065	1			T1	218		T2	88		T12	15
all_pins[3]	values[0x0]	2648622	1			T1	410		T2	219		T11	1
all_pins[3]	values[0x1]	1608029	1			T1	270		T2	153		T12	33
all_pins[3]	transitions[0x0=>0x1]	964076	1			T1	179		T2	97		T12	13
all_pins[3]	transitions[0x1=>0x0]	968807	1			T1	162		T2	54		T12	19
all_pins[4]	values[0x0]	2643931	1			T1	411		T2	240		T11	1
all_pins[4]	values[0x1]	1612720	1			T1	269		T2	132		T12	29
all_pins[4]	transitions[0x0=>0x1]	965843	1			T1	169		T2	91		T12	12
all_pins[4]	transitions[0x1=>0x0]	961152	1			T1	170		T2	112		T12	16
all_pins[5]	values[0x0]	2641995	1			T1	371		T2	289		T11	1
all_pins[5]	values[0x1]	1614656	1			T1	309		T2	83		T12	39
all_pins[5]	transitions[0x0=>0x1]	967676	1			T1	169		T2	55		T12	26
all_pins[5]	transitions[0x1=>0x0]	965740	1			T1	129		T2	104		T12	16
all_pins[6]	values[0x0]	2649860	1			T1	468		T2	297		T11	1
all_pins[6]	values[0x1]	1606791	1			T1	212		T2	75		T12	37
all_pins[6]	transitions[0x0=>0x1]	958212	1			T1	120		T2	57		T12	17
all_pins[6]	transitions[0x1=>0x0]	966077	1			T1	217		T2	65		T12	19
all_pins[7]	values[0x0]	2648977	1			T1	435		T2	243		T11	1
all_pins[7]	values[0x1]	1607674	1			T1	245		T2	129		T12	31
all_pins[7]	transitions[0x0=>0x1]	963337	1			T1	169		T2	107		T12	15
all_pins[7]	transitions[0x1=>0x0]	962454	1			T1	136		T2	53		T12	21
all_pins[8]	values[0x0]	2648573	1			T1	410		T2	253		T11	1
all_pins[8]	values[0x1]	1608078	1			T1	270		T2	119		T12	33
all_pins[8]	transitions[0x0=>0x1]	964057	1			T1	189		T2	69		T12	18
all_pins[8]	transitions[0x1=>0x0]	963653	1			T1	164		T2	79		T12	16
all_pins[9]	values[0x0]	2646137	1			T1	380		T2	200		T11	1
all_pins[9]	values[0x1]	1610514	1			T1	300		T2	172		T12	37
all_pins[9]	transitions[0x0=>0x1]	967747	1			T1	167		T2	123		T12	18
all_pins[9]	transitions[0x1=>0x0]	965311	1			T1	137		T2	70		T12	14
all_pins[10]	values[0x0]	2644471	1			T1	434		T2	203		T11	1
all_pins[10]	values[0x1]	1612180	1			T1	246		T2	169		T12	32
all_pins[10]	transitions[0x0=>0x1]	964570	1			T1	139		T2	82		T12	14
all_pins[10]	transitions[0x1=>0x0]	962904	1			T1	193		T2	85		T12	19
all_pins[11]	values[0x0]	2643349	1			T1	388		T2	209		T11	1
all_pins[11]	values[0x1]	1613302	1			T1	292		T2	163		T12	37
all_pins[11]	transitions[0x0=>0x1]	966533	1			T1	186		T2	71		T12	21
all_pins[11]	transitions[0x1=>0x0]	965411	1			T1	140		T2	77		T12	16
all_pins[12]	values[0x0]	2642095	1			T1	475		T2	222		T11	1
all_pins[12]	values[0x1]	1614556	1			T1	205		T2	150		T12	38
all_pins[12]	transitions[0x0=>0x1]	966006	1			T1	111		T2	74		T12	14
all_pins[12]	transitions[0x1=>0x0]	964752	1			T1	198		T2	87		T12	13
all_pins[13]	values[0x0]	2645821	1			T1	382		T2	231		T11	1
all_pins[13]	values[0x1]	1610830	1			T1	298		T2	141		T12	37
all_pins[13]	transitions[0x0=>0x1]	961360	1			T1	216		T2	87		T12	15
all_pins[13]	transitions[0x1=>0x0]	965086	1			T1	123		T2	96		T12	16
all_pins[14]	values[0x0]	2641859	1			T1	367		T2	254		T11	1
all_pins[14]	values[0x1]	1614792	1			T1	313		T2	118		T12	35
all_pins[14]	transitions[0x0=>0x1]	967018	1			T1	163		T2	59		T12	15
all_pins[14]	transitions[0x1=>0x0]	963056	1			T1	148		T2	82		T12	17
all_pins[15]	values[0x0]	2649441	1			T1	380		T2	244		T11	1
all_pins[15]	values[0x1]	1607210	1			T1	300		T2	128		T12	24
all_pins[15]	transitions[0x0=>0x1]	962817	1			T1	157		T2	75		T12	13
all_pins[15]	transitions[0x1=>0x0]	970399	1			T1	170		T2	65		T12	24
all_pins[16]	values[0x0]	2641425	1			T1	443		T2	218		T11	1
all_pins[16]	values[0x1]	1615226	1			T1	237		T2	154		T12	29
all_pins[16]	transitions[0x0=>0x1]	969316	1			T1	142		T2	73		T12	16
all_pins[16]	transitions[0x1=>0x0]	961300	1			T1	205		T2	47		T12	11
all_pins[17]	values[0x0]	2645326	1			T1	409		T2	258		T11	1
all_pins[17]	values[0x1]	1611325	1			T1	271		T2	114		T12	30
all_pins[17]	transitions[0x0=>0x1]	962711	1			T1	149		T2	61		T12	16
all_pins[17]	transitions[0x1=>0x0]	966612	1			T1	115		T2	101		T12	15
all_pins[18]	values[0x0]	2645303	1			T1	396		T2	230		T11	1
all_pins[18]	values[0x1]	1611348	1			T1	284		T2	142		T12	30
all_pins[18]	transitions[0x0=>0x1]	963762	1			T1	153		T2	92		T12	14
all_pins[18]	transitions[0x1=>0x0]	963739	1			T1	140		T2	64		T12	14
all_pins[19]	values[0x0]	2649813	1			T1	451		T2	223		T11	1
all_pins[19]	values[0x1]	1606838	1			T1	229		T2	149		T12	36
all_pins[19]	transitions[0x0=>0x1]	962609	1			T1	127		T2	82		T12	19
all_pins[19]	transitions[0x1=>0x0]	967119	1			T1	182		T2	75		T12	13
all_pins[20]	values[0x0]	2646093	1			T1	436		T2	241		T11	1
all_pins[20]	values[0x1]	1610558	1			T1	244		T2	131		T12	32
all_pins[20]	transitions[0x0=>0x1]	964601	1			T1	181		T2	77		T12	17
all_pins[20]	transitions[0x1=>0x0]	960881	1			T1	166		T2	95		T12	21
all_pins[21]	values[0x0]	2649499	1			T1	416		T2	263		T11	1
all_pins[21]	values[0x1]	1607152	1			T1	264		T2	109		T12	40
all_pins[21]	transitions[0x0=>0x1]	964193	1			T1	129		T2	68		T12	19
all_pins[21]	transitions[0x1=>0x0]	967599	1			T1	109		T2	90		T12	11
all_pins[22]	values[0x0]	2637050	1			T1	368		T2	245		T11	1
all_pins[22]	values[0x1]	1619601	1			T1	312		T2	127		T12	31
all_pins[22]	transitions[0x0=>0x1]	972349	1			T1	175		T2	87		T12	14
all_pins[22]	transitions[0x1=>0x0]	959900	1			T1	127		T2	69		T12	23
all_pins[23]	values[0x0]	2646229	1			T1	402		T2	211		T11	1
all_pins[23]	values[0x1]	1610422	1			T1	278		T2	161		T12	37
all_pins[23]	transitions[0x0=>0x1]	961929	1			T1	126		T2	111		T12	19
all_pins[23]	transitions[0x1=>0x0]	971108	1			T1	160		T2	77		T12	13
all_pins[24]	values[0x0]	2645729	1			T1	513		T2	234		T11	1
all_pins[24]	values[0x1]	1610922	1			T1	167		T2	138		T12	34
all_pins[24]	transitions[0x0=>0x1]	965101	1			T1	102		T2	68		T12	17
all_pins[24]	transitions[0x1=>0x0]	964601	1			T1	213		T2	91		T12	20
all_pins[25]	values[0x0]	2648291	1			T1	380		T2	205		T11	1
all_pins[25]	values[0x1]	1608360	1			T1	300		T2	167		T12	32
all_pins[25]	transitions[0x0=>0x1]	963891	1			T1	219		T2	86		T12	14
all_pins[25]	transitions[0x1=>0x0]	966453	1			T1	86		T2	57		T12	16
all_pins[26]	values[0x0]	2644838	1			T1	441		T2	238		T11	1
all_pins[26]	values[0x1]	1611813	1			T1	239		T2	134		T12	31
all_pins[26]	transitions[0x0=>0x1]	970154	1			T1	122		T2	84		T12	16
all_pins[26]	transitions[0x1=>0x0]	966701	1			T1	183		T2	117		T12	17
all_pins[27]	values[0x0]	2640379	1			T1	406		T2	207		T11	1
all_pins[27]	values[0x1]	1616272	1			T1	274		T2	165		T12	37
all_pins[27]	transitions[0x0=>0x1]	966727	1			T1	172		T2	99		T12	19
all_pins[27]	transitions[0x1=>0x0]	962268	1			T1	137		T2	68		T12	13
all_pins[28]	values[0x0]	2643670	1			T1	424		T2	252		T11	1
all_pins[28]	values[0x1]	1612981	1			T1	256		T2	120		T12	39
all_pins[28]	transitions[0x0=>0x1]	963612	1			T1	127		T2	63		T12	17
all_pins[28]	transitions[0x1=>0x0]	966903	1			T1	145		T2	108		T12	15
all_pins[29]	values[0x0]	2643912	1			T1	438		T2	200		T11	1
all_pins[29]	values[0x1]	1612739	1			T1	242		T2	172		T12	29
all_pins[29]	transitions[0x0=>0x1]	965593	1			T1	155		T2	119		T12	11
all_pins[29]	transitions[0x1=>0x0]	965835	1			T1	169		T2	67		T12	21
all_pins[30]	values[0x0]	2646164	1			T1	409		T2	223		T11	1
all_pins[30]	values[0x1]	1610487	1			T1	271		T2	149		T12	28
all_pins[30]	transitions[0x0=>0x1]	963495	1			T1	165		T2	71		T12	15
all_pins[30]	transitions[0x1=>0x0]	965747	1			T1	136		T2	94		T12	16
all_pins[31]	values[0x0]	2645058	1			T1	436		T2	243		T11	1
all_pins[31]	values[0x1]	1611593	1			T1	244		T2	129		T12	34
all_pins[31]	transitions[0x0=>0x1]	965299	1			T1	138		T2	69		T12	22
all_pins[31]	transitions[0x1=>0x0]	964193	1			T1	165		T2	89		T12	16