Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[1]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[2]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[3]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[4]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[5]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[6]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[7]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[8]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[9]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[10]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[11]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[12]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[13]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[14]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[15]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[16]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[17]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[18]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[19]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[20]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[21]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[22]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[23]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[24]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[25]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[26]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[27]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[28]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[29]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[30]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[31]	13989678	1			T1	1840		T2	844		T11	231

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267900160

1

T1

14207

T2

5930

T11

5266

auto[1]

179769536

1

T1

44673

T2

21078

T11

2126

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

358889724

1

T1

33996

T2

15554

T11

4383

auto[1]

88779972

1

T1

24884

T2

11454

T11

3009

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

332920176

1

T1

30137

T2

13118

T11

4286

auto[1]

114749520

1

T1

28743

T2

13890

T11

3106

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	5195716	1			T1	16		T2	4		T11	63
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	3815238	1			T1	417		T2	197		T11	26
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	1394181	1			T1	321		T2	190		T11	54
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	1771437	1			T1	32		T2	15		T11	42
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	428596	1			T1	559		T2	253		T14	20
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	1384510	1			T1	495		T2	185		T11	46
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	5200743	1			T1	25		T2	14		T11	53
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	3804570	1			T1	582		T2	221		T11	21
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	1395886	1			T1	394		T2	156		T11	38
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	1776911	1			T1	19		T2	7		T11	45
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	428176	1			T1	455		T2	262		T14	12
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	1383392	1			T1	365		T2	184		T11	74
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	5196951	1			T1	24		T2	11		T11	99
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	3811258	1			T1	403		T2	168		T11	21
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	1389172	1			T1	515		T2	181		T11	27
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	1776689	1			T1	22		T2	5		T11	66
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	429345	1			T1	397		T2	240		T14	12
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	1386263	1			T1	479		T2	239		T11	18
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	5204576	1			T1	19		T2	7		T11	70
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	3808137	1			T1	498		T2	286		T11	18
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	1390967	1			T1	402		T2	168		T11	27
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	1776732	1			T1	22		T2	11		T11	54
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	427445	1			T1	521		T2	226		T14	9
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	1381821	1			T1	378		T2	146		T11	62
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	5207262	1			T1	15		T2	7		T11	63
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	3795392	1			T1	532		T2	213		T11	19
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	1398472	1			T1	425		T2	195		T11	70
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	1773192	1			T1	26		T2	11		T11	40
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	427691	1			T1	438		T2	200		T14	11
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	1387669	1			T1	404		T2	218		T11	39
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	5193095	1			T1	16		T2	10		T11	66
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	3811105	1			T1	505		T2	297		T11	20
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	1398177	1			T1	423		T2	108		T11	54
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	1775897	1			T1	23		T2	8		T11	40
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	427786	1			T1	496		T2	247		T14	7
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	1383618	1			T1	377		T2	174		T11	51
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	5194762	1			T1	21		T2	17		T11	60
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	3811536	1			T1	545		T2	272		T11	18
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	1396227	1			T1	358		T2	160		T11	54
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	1773579	1			T1	22		T2	3		T11	49
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	428635	1			T1	547		T2	255		T14	15
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	1384939	1			T1	347		T2	137		T11	50
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	5202691	1			T1	26		T2	12		T11	52
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	3811583	1			T1	451		T2	235		T11	16
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	1401662	1			T1	471		T2	151		T11	48
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	1766162	1			T1	18		T2	9		T11	47
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	425759	1			T1	448		T2	252		T14	21
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	1381821	1			T1	426		T2	185		T11	68
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	5203909	1			T1	23		T2	12		T11	75
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	3806938	1			T1	551		T2	225		T11	18
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	1399159	1			T1	441		T2	186		T11	30
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	1769510	1			T1	11		T2	11		T11	46
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	427195	1			T1	442		T2	245		T14	4
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	1382967	1			T1	372		T2	165		T11	62
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	5199068	1			T1	34		T2	4		T11	83
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	3807174	1			T1	495		T2	229		T11	19
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	1390727	1			T1	521		T2	180		T11	61
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	1782892	1			T1	23		T2	9		T11	32
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	427071	1			T1	426		T2	241		T14	12
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	1382746	1			T1	341		T2	181		T11	36
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	5187037	1			T1	31		T2	17		T11	62
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	3814401	1			T1	582		T2	284		T11	22
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	1394447	1			T1	364		T2	164		T11	48
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	1780331	1			T1	13		T2	2		T11	50
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	428797	1			T1	511		T2	236		T14	11
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	1384665	1			T1	339		T2	141		T11	49
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	5195760	1			T1	20		T2	9		T11	67
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	3817916	1			T1	632		T2	277		T11	19
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	1394036	1			T1	421		T2	169		T11	46
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	1774423	1			T1	22		T2	8		T11	48
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	427598	1			T1	424		T2	232		T14	17
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	1379945	1			T1	321		T2	149		T11	51
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	5194106	1			T1	29		T2	1		T11	56
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	3812906	1			T1	430		T2	222		T11	17
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	1397631	1			T1	466		T2	155		T11	42
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	1770437	1			T1	24		T2	12		T11	66
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	428395	1			T1	490		T2	275		T14	20
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	1386203	1			T1	401		T2	179		T11	50
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	5189805	1			T1	20		T2	8		T11	67
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	3811681	1			T1	561		T2	171		T11	21
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	1397113	1			T1	321		T2	149		T11	43
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	1776075	1			T1	16		T2	11		T11	54
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	428047	1			T1	611		T2	272		T14	7
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	1386957	1			T1	311		T2	233		T11	46
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	5193165	1			T1	6		T2	9		T11	82
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	3813437	1			T1	464		T2	267		T11	20
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	1393988	1			T1	428		T2	241		T11	34
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	1778709	1			T1	33		T2	3		T11	52
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	424959	1			T1	553		T2	158		T14	18
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	1385420	1			T1	356		T2	166		T11	43
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	5202530	1			T1	25		T2	14		T11	69
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	3803009	1			T1	492		T2	187		T11	14
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	1397959	1			T1	420		T2	158		T11	44
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	1775015	1			T1	30		T2	6		T11	56
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	425184	1			T1	497		T2	213		T14	20
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	1385981	1			T1	376		T2	266		T11	48
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	5210702	1			T1	32		T2	7		T11	75
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	3804406	1			T1	540		T2	258		T11	11
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	1390757	1			T1	448		T2	164		T11	73
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	1779140	1			T1	18		T2	12		T11	36
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	425784	1			T1	437		T2	172		T14	13
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	1378889	1			T1	365		T2	231		T11	36
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	5221490	1			T1	15		T2	20		T11	68
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	3794169	1			T1	494		T2	286		T11	22
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	1394961	1			T1	339		T2	198		T11	25
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	1773525	1			T1	28		T11	76		T14	243
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	427219	1			T1	550		T2	170		T14	8
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	1378314	1			T1	414		T2	170		T11	40
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	5194121	1			T1	26		T2	10		T11	67
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	3815087	1			T1	565		T2	246		T11	20
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	1390977	1			T1	341		T2	172		T11	36
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	1785347	1			T1	15		T2	8		T11	44
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	428130	1			T1	443		T2	222		T14	20
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	1376016	1			T1	450		T2	186		T11	64
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	5198087	1			T1	22		T2	7		T11	64
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	3809402	1			T1	428		T2	232		T11	18
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	1389333	1			T1	379		T2	134		T11	58
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	1784770	1			T1	19		T2	4		T11	45
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	428725	1			T1	551		T2	281		T14	12
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	1379361	1			T1	441		T2	186		T11	46
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	5204430	1			T1	25		T2	3		T11	62
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	3813285	1			T1	582		T2	162		T11	22
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	1388493	1			T1	400		T2	184		T11	59
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	1779803	1			T1	18		T2	12		T11	42
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	427619	1			T1	476		T2	247		T14	12
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	1376048	1			T1	339		T2	236		T11	46
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	5201396	1			T1	15		T2	5		T11	70
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	3811940	1			T1	432		T2	200		T11	22
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	1390148	1			T1	382		T2	164		T11	55
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	1781257	1			T1	22		T2	13		T11	34
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	428068	1			T1	579		T2	263		T14	10
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	1376869	1			T1	410		T2	199		T11	50
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	5202031	1			T1	40		T2	3		T11	66
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	3814577	1			T1	574		T2	234		T11	21
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	1384801	1			T1	452		T2	111		T11	36
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	1782593	1			T1	17		T2	16		T11	56
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	426683	1			T1	443		T2	343		T14	15
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	1378993	1			T1	314		T2	137		T11	52
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	5211187	1			T1	16		T2	2		T11	84
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	3807263	1			T1	557		T2	280		T11	18
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	1393866	1			T1	357		T2	204		T11	45
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	1773314	1			T1	29		T2	11		T11	48
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	425957	1			T1	526		T2	189		T14	16
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	1378091	1			T1	355		T2	158		T11	36
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	5196779	1			T1	17		T2	8		T11	56
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	3815732	1			T1	510		T2	177		T11	20
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	1393462	1			T1	330		T2	164		T11	60
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	1778299	1			T1	34		T2	9		T11	50
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	429036	1			T1	621		T2	254		T14	5
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1376370	1			T1	328		T2	232		T11	45
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	5201228	1			T1	18		T2	1		T11	75
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	3813437	1			T1	503		T2	207		T11	18
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	1397360	1			T1	376		T2	166		T11	34
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	1773972	1			T1	23		T2	18		T11	70
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	427080	1			T1	471		T2	272		T14	17
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	1376601	1			T1	449		T2	180		T11	34
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	5199546	1			T1	19		T2	6		T11	68
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	3806678	1			T1	550		T2	194		T11	24
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	1389320	1			T1	382		T2	179		T11	35
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	1778057	1			T1	19		T2	8		T11	58
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	430607	1			T1	505		T2	208		T14	10
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	1385470	1			T1	365		T2	249		T11	46
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	5209093	1			T1	19		T2	13		T11	65
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	3810658	1			T1	570		T2	263		T11	21
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	1392624	1			T1	460		T2	138		T11	41
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	1777936	1			T1	24		T2	9		T11	60
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	425823	1			T1	472		T2	238		T14	13
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1373544	1			T1	295		T2	183		T11	44
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	5209951	1			T1	13		T2	18		T11	56
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	3805083	1			T1	490		T2	285		T11	17
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	1390378	1			T1	353		T2	188		T11	58
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	1776728	1			T1	27		T2	5		T11	50
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	428141	1			T1	609		T2	186		T14	15
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	1379397	1			T1	348		T2	162		T11	50
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	5208471	1			T1	29		T2	10		T11	41
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	3806404	1			T1	620		T2	290		T11	18
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	1388672	1			T1	370		T2	151		T11	64
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	1778161	1			T1	10		T2	6		T11	48
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	428931	1			T1	438		T2	242		T14	8
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	1379039	1			T1	373		T2	145		T11	60
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	5212699	1			T1	22		T2	5		T11	88
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	3799840	1			T1	468		T2	224		T11	17
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	1389494	1			T1	374		T2	181		T11	50
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	1783843	1			T1	28		T2	13		T11	50
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	426161	1			T1	566		T2	202		T14	8
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	1377641	1			T1	382		T2	219		T11	26
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	5208864	1			T1	20		T2	12		T11	75
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	3803744	1			T1	609		T2	179		T11	20
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	1386489	1			T1	373		T2	155		T11	52
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	1783234	1			T1	15		T2	5		T11	44
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	427874	1			T1	462		T2	224		T14	21
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	1379473	1			T1	361		T2	269		T11	40

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal