Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[1]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[2]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[3]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[4]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[5]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[6]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[7]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[8]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[9]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[10]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[11]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[12]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[13]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[14]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[15]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[16]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[17]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[18]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[19]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[20]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[21]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[22]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[23]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[24]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[25]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[26]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[27]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[28]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[29]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[30]	13989678	1			T1	1840		T2	844		T11	231
bins_for_gpio_bits[31]	13989678	1			T1	1840		T2	844		T11	231

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267900160

1

T1

14207

T2

5930

T11

5266

auto[1]

179769536

1

T1

44673

T2

21078

T11

2126

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

267892257

1

T1

14207

T2

5930

T11

5260

auto[1]

179777439

1

T1

44673

T2

21078

T11

2132

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	8114205	1			T1	331		T2	184		T11	150
bins_for_gpio_bits[0]	auto[0]	auto[1]	246887	1			T1	38		T2	25		T11	9
bins_for_gpio_bits[0]	auto[1]	auto[0]	247129	1			T1	38		T2	25		T11	9
bins_for_gpio_bits[0]	auto[1]	auto[1]	5381457	1			T1	1433		T2	610		T11	63
bins_for_gpio_bits[1]	auto[0]	auto[0]	8126341	1			T1	378		T2	154		T11	123
bins_for_gpio_bits[1]	auto[0]	auto[1]	246961	1			T1	60		T2	23		T11	13
bins_for_gpio_bits[1]	auto[1]	auto[0]	247199	1			T1	60		T2	23		T11	13
bins_for_gpio_bits[1]	auto[1]	auto[1]	5369177	1			T1	1342		T2	644		T11	82
bins_for_gpio_bits[2]	auto[0]	auto[0]	8115930	1			T1	485		T2	171		T11	186
bins_for_gpio_bits[2]	auto[0]	auto[1]	246675	1			T1	76		T2	26		T11	6
bins_for_gpio_bits[2]	auto[1]	auto[0]	246882	1			T1	76		T2	26		T11	6
bins_for_gpio_bits[2]	auto[1]	auto[1]	5380191	1			T1	1203		T2	621		T11	33
bins_for_gpio_bits[3]	auto[0]	auto[0]	8125091	1			T1	386		T2	161		T11	142
bins_for_gpio_bits[3]	auto[0]	auto[1]	246951	1			T1	57		T2	25		T11	9
bins_for_gpio_bits[3]	auto[1]	auto[0]	247184	1			T1	57		T2	25		T11	9
bins_for_gpio_bits[3]	auto[1]	auto[1]	5370452	1			T1	1340		T2	633		T11	71
bins_for_gpio_bits[4]	auto[0]	auto[0]	8131666	1			T1	407		T2	177		T11	157
bins_for_gpio_bits[4]	auto[0]	auto[1]	246979	1			T1	59		T2	36		T11	15
bins_for_gpio_bits[4]	auto[1]	auto[0]	247260	1			T1	59		T2	36		T11	16
bins_for_gpio_bits[4]	auto[1]	auto[1]	5363773	1			T1	1315		T2	595		T11	43
bins_for_gpio_bits[5]	auto[0]	auto[0]	8119756	1			T1	406		T2	105		T11	149
bins_for_gpio_bits[5]	auto[0]	auto[1]	247191	1			T1	56		T2	21		T11	10
bins_for_gpio_bits[5]	auto[1]	auto[0]	247413	1			T1	56		T2	21		T11	11
bins_for_gpio_bits[5]	auto[1]	auto[1]	5375318	1			T1	1322		T2	697		T11	61
bins_for_gpio_bits[6]	auto[0]	auto[0]	8117514	1			T1	353		T2	153		T11	151
bins_for_gpio_bits[6]	auto[0]	auto[1]	246802	1			T1	48		T2	27		T11	12
bins_for_gpio_bits[6]	auto[1]	auto[0]	247054	1			T1	48		T2	27		T11	12
bins_for_gpio_bits[6]	auto[1]	auto[1]	5378308	1			T1	1391		T2	637		T11	56
bins_for_gpio_bits[7]	auto[0]	auto[0]	8123332	1			T1	461		T2	147		T11	133
bins_for_gpio_bits[7]	auto[0]	auto[1]	246926	1			T1	54		T2	25		T11	14
bins_for_gpio_bits[7]	auto[1]	auto[0]	247183	1			T1	54		T2	25		T11	14
bins_for_gpio_bits[7]	auto[1]	auto[1]	5372237	1			T1	1271		T2	647		T11	70
bins_for_gpio_bits[8]	auto[0]	auto[0]	8125774	1			T1	408		T2	182		T11	138
bins_for_gpio_bits[8]	auto[0]	auto[1]	246576	1			T1	67		T2	27		T11	13
bins_for_gpio_bits[8]	auto[1]	auto[0]	246804	1			T1	67		T2	27		T11	13
bins_for_gpio_bits[8]	auto[1]	auto[1]	5370524	1			T1	1298		T2	608		T11	67
bins_for_gpio_bits[9]	auto[0]	auto[0]	8125031	1			T1	510		T2	167		T11	166
bins_for_gpio_bits[9]	auto[0]	auto[1]	247366	1			T1	68		T2	26		T11	10
bins_for_gpio_bits[9]	auto[1]	auto[0]	247656	1			T1	68		T2	26		T11	10
bins_for_gpio_bits[9]	auto[1]	auto[1]	5369625	1			T1	1194		T2	625		T11	45
bins_for_gpio_bits[10]	auto[0]	auto[0]	8114439	1			T1	353		T2	162		T11	149
bins_for_gpio_bits[10]	auto[0]	auto[1]	247141	1			T1	55		T2	21		T11	10
bins_for_gpio_bits[10]	auto[1]	auto[0]	247376	1			T1	55		T2	21		T11	11
bins_for_gpio_bits[10]	auto[1]	auto[1]	5380722	1			T1	1377		T2	640		T11	61
bins_for_gpio_bits[11]	auto[0]	auto[0]	8117063	1			T1	402		T2	157		T11	150
bins_for_gpio_bits[11]	auto[0]	auto[1]	246886	1			T1	61		T2	29		T11	10
bins_for_gpio_bits[11]	auto[1]	auto[0]	247156	1			T1	61		T2	29		T11	11
bins_for_gpio_bits[11]	auto[1]	auto[1]	5378573	1			T1	1316		T2	629		T11	60
bins_for_gpio_bits[12]	auto[0]	auto[0]	8113951	1			T1	463		T2	145		T11	153
bins_for_gpio_bits[12]	auto[0]	auto[1]	247990	1			T1	56		T2	23		T11	11
bins_for_gpio_bits[12]	auto[1]	auto[0]	248223	1			T1	56		T2	23		T11	11
bins_for_gpio_bits[12]	auto[1]	auto[1]	5379514	1			T1	1265		T2	653		T11	56
bins_for_gpio_bits[13]	auto[0]	auto[0]	8115020	1			T1	307		T2	141		T11	153
bins_for_gpio_bits[13]	auto[0]	auto[1]	247738	1			T1	50		T2	27		T11	11
bins_for_gpio_bits[13]	auto[1]	auto[0]	247973	1			T1	50		T2	27		T11	11
bins_for_gpio_bits[13]	auto[1]	auto[1]	5378947	1			T1	1433		T2	649		T11	56
bins_for_gpio_bits[14]	auto[0]	auto[0]	8118422	1			T1	420		T2	221		T11	156
bins_for_gpio_bits[14]	auto[0]	auto[1]	247189	1			T1	47		T2	32		T11	11
bins_for_gpio_bits[14]	auto[1]	auto[0]	247440	1			T1	47		T2	32		T11	12
bins_for_gpio_bits[14]	auto[1]	auto[1]	5376627	1			T1	1326		T2	559		T11	52
bins_for_gpio_bits[15]	auto[0]	auto[0]	8127761	1			T1	410		T2	155		T11	157
bins_for_gpio_bits[15]	auto[0]	auto[1]	247481	1			T1	65		T2	23		T11	12
bins_for_gpio_bits[15]	auto[1]	auto[0]	247743	1			T1	65		T2	23		T11	12
bins_for_gpio_bits[15]	auto[1]	auto[1]	5366693	1			T1	1300		T2	643		T11	50
bins_for_gpio_bits[16]	auto[0]	auto[0]	8133269	1			T1	439		T2	153		T11	175
bins_for_gpio_bits[16]	auto[0]	auto[1]	247075	1			T1	59		T2	30		T11	9
bins_for_gpio_bits[16]	auto[1]	auto[0]	247330	1			T1	59		T2	30		T11	9
bins_for_gpio_bits[16]	auto[1]	auto[1]	5362004	1			T1	1283		T2	631		T11	38
bins_for_gpio_bits[17]	auto[0]	auto[0]	8142862	1			T1	331		T2	192		T11	160
bins_for_gpio_bits[17]	auto[0]	auto[1]	246887	1			T1	51		T2	26		T11	9
bins_for_gpio_bits[17]	auto[1]	auto[0]	247114	1			T1	51		T2	26		T11	9
bins_for_gpio_bits[17]	auto[1]	auto[1]	5352815	1			T1	1407		T2	600		T11	53
bins_for_gpio_bits[18]	auto[0]	auto[0]	8122867	1			T1	331		T2	165		T11	137
bins_for_gpio_bits[18]	auto[0]	auto[1]	247320	1			T1	51		T2	25		T11	10
bins_for_gpio_bits[18]	auto[1]	auto[0]	247578	1			T1	51		T2	25		T11	10
bins_for_gpio_bits[18]	auto[1]	auto[1]	5371913	1			T1	1407		T2	629		T11	74
bins_for_gpio_bits[19]	auto[0]	auto[0]	8125390	1			T1	371		T2	122		T11	157
bins_for_gpio_bits[19]	auto[0]	auto[1]	246533	1			T1	49		T2	23		T11	10
bins_for_gpio_bits[19]	auto[1]	auto[0]	246800	1			T1	49		T2	23		T11	10
bins_for_gpio_bits[19]	auto[1]	auto[1]	5370955	1			T1	1371		T2	676		T11	54
bins_for_gpio_bits[20]	auto[0]	auto[0]	8125823	1			T1	392		T2	178		T11	151
bins_for_gpio_bits[20]	auto[0]	auto[1]	246694	1			T1	51		T2	21		T11	12
bins_for_gpio_bits[20]	auto[1]	auto[0]	246903	1			T1	51		T2	21		T11	12
bins_for_gpio_bits[20]	auto[1]	auto[1]	5370258	1			T1	1346		T2	624		T11	56
bins_for_gpio_bits[21]	auto[0]	auto[0]	8125675	1			T1	367		T2	160		T11	145
bins_for_gpio_bits[21]	auto[0]	auto[1]	246841	1			T1	52		T2	22		T11	14
bins_for_gpio_bits[21]	auto[1]	auto[0]	247126	1			T1	52		T2	22		T11	14
bins_for_gpio_bits[21]	auto[1]	auto[1]	5370036	1			T1	1369		T2	640		T11	58
bins_for_gpio_bits[22]	auto[0]	auto[0]	8122822	1			T1	440		T2	115		T11	147
bins_for_gpio_bits[22]	auto[0]	auto[1]	246352	1			T1	69		T2	15		T11	11
bins_for_gpio_bits[22]	auto[1]	auto[0]	246603	1			T1	69		T2	15		T11	11
bins_for_gpio_bits[22]	auto[1]	auto[1]	5373901	1			T1	1262		T2	699		T11	62
bins_for_gpio_bits[23]	auto[0]	auto[0]	8131489	1			T1	346		T2	185		T11	169
bins_for_gpio_bits[23]	auto[0]	auto[1]	246643	1			T1	56		T2	32		T11	8
bins_for_gpio_bits[23]	auto[1]	auto[0]	246878	1			T1	56		T2	32		T11	8
bins_for_gpio_bits[23]	auto[1]	auto[1]	5364668	1			T1	1382		T2	595		T11	46
bins_for_gpio_bits[24]	auto[0]	auto[0]	8120995	1			T1	330		T2	159		T11	153
bins_for_gpio_bits[24]	auto[0]	auto[1]	247297	1			T1	51		T2	22		T11	12
bins_for_gpio_bits[24]	auto[1]	auto[0]	247545	1			T1	51		T2	22		T11	13
bins_for_gpio_bits[24]	auto[1]	auto[1]	5373841	1			T1	1408		T2	641		T11	53
bins_for_gpio_bits[25]	auto[0]	auto[0]	8125431	1			T1	369		T2	164		T11	170
bins_for_gpio_bits[25]	auto[0]	auto[1]	246893	1			T1	48		T2	21		T11	9
bins_for_gpio_bits[25]	auto[1]	auto[0]	247129	1			T1	48		T2	21		T11	9
bins_for_gpio_bits[25]	auto[1]	auto[1]	5370225	1			T1	1375		T2	638		T11	43
bins_for_gpio_bits[26]	auto[0]	auto[0]	8119145	1			T1	369		T2	166		T11	149
bins_for_gpio_bits[26]	auto[0]	auto[1]	247486	1			T1	51		T2	27		T11	12
bins_for_gpio_bits[26]	auto[1]	auto[0]	247778	1			T1	51		T2	27		T11	12
bins_for_gpio_bits[26]	auto[1]	auto[1]	5375269	1			T1	1369		T2	624		T11	58
bins_for_gpio_bits[27]	auto[0]	auto[0]	8132563	1			T1	448		T2	134		T11	153
bins_for_gpio_bits[27]	auto[0]	auto[1]	246830	1			T1	55		T2	26		T11	13
bins_for_gpio_bits[27]	auto[1]	auto[0]	247090	1			T1	55		T2	26		T11	13
bins_for_gpio_bits[27]	auto[1]	auto[1]	5363195	1			T1	1282		T2	658		T11	52
bins_for_gpio_bits[28]	auto[0]	auto[0]	8129711	1			T1	346		T2	178		T11	149
bins_for_gpio_bits[28]	auto[0]	auto[1]	247070	1			T1	47		T2	33		T11	15
bins_for_gpio_bits[28]	auto[1]	auto[0]	247346	1			T1	47		T2	33		T11	15
bins_for_gpio_bits[28]	auto[1]	auto[1]	5365551	1			T1	1400		T2	600		T11	52
bins_for_gpio_bits[29]	auto[0]	auto[0]	8128017	1			T1	350		T2	139		T11	135
bins_for_gpio_bits[29]	auto[0]	auto[1]	247060	1			T1	59		T2	28		T11	18
bins_for_gpio_bits[29]	auto[1]	auto[0]	247287	1			T1	59		T2	28		T11	18
bins_for_gpio_bits[29]	auto[1]	auto[1]	5367314	1			T1	1372		T2	649		T11	60
bins_for_gpio_bits[30]	auto[0]	auto[0]	8138177	1			T1	373		T2	172		T11	178
bins_for_gpio_bits[30]	auto[0]	auto[1]	247663	1			T1	51		T2	27		T11	10
bins_for_gpio_bits[30]	auto[1]	auto[0]	247859	1			T1	51		T2	27		T11	10
bins_for_gpio_bits[30]	auto[1]	auto[1]	5355979	1			T1	1365		T2	618		T11	33
bins_for_gpio_bits[31]	auto[0]	auto[0]	8131523	1			T1	351		T2	143		T11	160
bins_for_gpio_bits[31]	auto[0]	auto[1]	246819	1			T1	57		T2	29		T11	11
bins_for_gpio_bits[31]	auto[1]	auto[0]	247064	1			T1	57		T2	29		T11	11
bins_for_gpio_bits[31]	auto[1]	auto[1]	5364272	1			T1	1375		T2	643		T11	49