Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8203714 |
1 |
|
|
T1 |
744 |
|
T2 |
426 |
|
T11 |
135 |
| auto[1] |
6004029 |
1 |
|
|
T1 |
1188 |
|
T2 |
512 |
|
T13 |
537 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13450283 |
1 |
|
|
T1 |
1914 |
|
T2 |
922 |
|
T11 |
135 |
| auto[1] |
757460 |
1 |
|
|
T1 |
18 |
|
T2 |
16 |
|
T13 |
101 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8239094 |
1 |
|
|
T1 |
1099 |
|
T2 |
616 |
|
T11 |
135 |
| auto[1] |
5968649 |
1 |
|
|
T1 |
833 |
|
T2 |
322 |
|
T13 |
538 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2611437 |
1 |
|
|
T1 |
295 |
|
T2 |
134 |
|
T13 |
178 |
| auto[1] |
auto[0] |
auto[1] |
378777 |
1 |
|
|
T1 |
8 |
|
T2 |
6 |
|
T13 |
46 |
| auto[1] |
auto[1] |
auto[0] |
2599752 |
1 |
|
|
T1 |
520 |
|
T2 |
172 |
|
T13 |
259 |
| auto[1] |
auto[1] |
auto[1] |
378683 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T13 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8216384 |
1 |
|
|
T1 |
876 |
|
T2 |
461 |
|
T11 |
135 |
| auto[1] |
5991359 |
1 |
|
|
T1 |
1056 |
|
T2 |
477 |
|
T13 |
598 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13446389 |
1 |
|
|
T1 |
1897 |
|
T2 |
916 |
|
T11 |
135 |
| auto[1] |
761354 |
1 |
|
|
T1 |
35 |
|
T2 |
22 |
|
T13 |
96 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8207711 |
1 |
|
|
T1 |
1083 |
|
T2 |
479 |
|
T11 |
135 |
| auto[1] |
6000032 |
1 |
|
|
T1 |
849 |
|
T2 |
459 |
|
T13 |
526 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2614730 |
1 |
|
|
T1 |
443 |
|
T2 |
244 |
|
T13 |
211 |
| auto[1] |
auto[0] |
auto[1] |
380205 |
1 |
|
|
T1 |
18 |
|
T2 |
11 |
|
T13 |
50 |
| auto[1] |
auto[1] |
auto[0] |
2623948 |
1 |
|
|
T1 |
371 |
|
T2 |
193 |
|
T13 |
219 |
| auto[1] |
auto[1] |
auto[1] |
381149 |
1 |
|
|
T1 |
17 |
|
T2 |
11 |
|
T13 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8222247 |
1 |
|
|
T1 |
1060 |
|
T2 |
379 |
|
T11 |
135 |
| auto[1] |
5985496 |
1 |
|
|
T1 |
872 |
|
T2 |
559 |
|
T13 |
624 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13448245 |
1 |
|
|
T1 |
1894 |
|
T2 |
919 |
|
T11 |
135 |
| auto[1] |
759498 |
1 |
|
|
T1 |
38 |
|
T2 |
19 |
|
T13 |
116 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8232380 |
1 |
|
|
T1 |
949 |
|
T2 |
477 |
|
T11 |
135 |
| auto[1] |
5975363 |
1 |
|
|
T1 |
983 |
|
T2 |
461 |
|
T13 |
539 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2608825 |
1 |
|
|
T1 |
519 |
|
T2 |
166 |
|
T13 |
191 |
| auto[1] |
auto[0] |
auto[1] |
380986 |
1 |
|
|
T1 |
24 |
|
T2 |
6 |
|
T13 |
61 |
| auto[1] |
auto[1] |
auto[0] |
2607040 |
1 |
|
|
T1 |
426 |
|
T2 |
276 |
|
T13 |
232 |
| auto[1] |
auto[1] |
auto[1] |
378512 |
1 |
|
|
T1 |
14 |
|
T2 |
13 |
|
T13 |
55 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8212117 |
1 |
|
|
T1 |
855 |
|
T2 |
480 |
|
T11 |
135 |
| auto[1] |
5995626 |
1 |
|
|
T1 |
1077 |
|
T2 |
458 |
|
T13 |
563 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13451963 |
1 |
|
|
T1 |
1904 |
|
T2 |
926 |
|
T11 |
135 |
| auto[1] |
755780 |
1 |
|
|
T1 |
28 |
|
T2 |
12 |
|
T13 |
85 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8248671 |
1 |
|
|
T1 |
1033 |
|
T2 |
519 |
|
T11 |
135 |
| auto[1] |
5959072 |
1 |
|
|
T1 |
899 |
|
T2 |
419 |
|
T13 |
438 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2597015 |
1 |
|
|
T1 |
348 |
|
T2 |
184 |
|
T13 |
205 |
| auto[1] |
auto[0] |
auto[1] |
376941 |
1 |
|
|
T1 |
15 |
|
T2 |
8 |
|
T13 |
54 |
| auto[1] |
auto[1] |
auto[0] |
2606277 |
1 |
|
|
T1 |
523 |
|
T2 |
223 |
|
T13 |
148 |
| auto[1] |
auto[1] |
auto[1] |
378839 |
1 |
|
|
T1 |
13 |
|
T2 |
4 |
|
T13 |
31 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8183350 |
1 |
|
|
T1 |
1138 |
|
T2 |
497 |
|
T11 |
135 |
| auto[1] |
6024393 |
1 |
|
|
T1 |
794 |
|
T2 |
441 |
|
T13 |
483 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13448506 |
1 |
|
|
T1 |
1901 |
|
T2 |
923 |
|
T11 |
135 |
| auto[1] |
759237 |
1 |
|
|
T1 |
31 |
|
T2 |
15 |
|
T13 |
134 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8239184 |
1 |
|
|
T1 |
1071 |
|
T2 |
433 |
|
T11 |
135 |
| auto[1] |
5968559 |
1 |
|
|
T1 |
861 |
|
T2 |
505 |
|
T13 |
651 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2609032 |
1 |
|
|
T1 |
539 |
|
T2 |
269 |
|
T13 |
271 |
| auto[1] |
auto[0] |
auto[1] |
380481 |
1 |
|
|
T1 |
21 |
|
T2 |
7 |
|
T13 |
70 |
| auto[1] |
auto[1] |
auto[0] |
2600290 |
1 |
|
|
T1 |
291 |
|
T2 |
221 |
|
T13 |
246 |
| auto[1] |
auto[1] |
auto[1] |
378756 |
1 |
|
|
T1 |
10 |
|
T2 |
8 |
|
T13 |
64 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8238411 |
1 |
|
|
T1 |
765 |
|
T2 |
476 |
|
T11 |
135 |
| auto[1] |
5969332 |
1 |
|
|
T1 |
1167 |
|
T2 |
462 |
|
T13 |
551 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13446436 |
1 |
|
|
T1 |
1911 |
|
T2 |
920 |
|
T11 |
135 |
| auto[1] |
761307 |
1 |
|
|
T1 |
21 |
|
T2 |
18 |
|
T13 |
146 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8212404 |
1 |
|
|
T1 |
1233 |
|
T2 |
414 |
|
T11 |
135 |
| auto[1] |
5995339 |
1 |
|
|
T1 |
699 |
|
T2 |
524 |
|
T13 |
709 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2641750 |
1 |
|
|
T1 |
273 |
|
T2 |
277 |
|
T13 |
269 |
| auto[1] |
auto[0] |
auto[1] |
384280 |
1 |
|
|
T1 |
9 |
|
T2 |
9 |
|
T13 |
78 |
| auto[1] |
auto[1] |
auto[0] |
2592282 |
1 |
|
|
T1 |
405 |
|
T2 |
229 |
|
T13 |
294 |
| auto[1] |
auto[1] |
auto[1] |
377027 |
1 |
|
|
T1 |
12 |
|
T2 |
9 |
|
T13 |
68 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8179799 |
1 |
|
|
T1 |
907 |
|
T2 |
490 |
|
T11 |
135 |
| auto[1] |
6027944 |
1 |
|
|
T1 |
1025 |
|
T2 |
448 |
|
T13 |
510 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13442511 |
1 |
|
|
T1 |
1901 |
|
T2 |
917 |
|
T11 |
135 |
| auto[1] |
765232 |
1 |
|
|
T1 |
31 |
|
T2 |
21 |
|
T13 |
102 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8192560 |
1 |
|
|
T1 |
1018 |
|
T2 |
411 |
|
T11 |
135 |
| auto[1] |
6015183 |
1 |
|
|
T1 |
914 |
|
T2 |
527 |
|
T13 |
527 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2606388 |
1 |
|
|
T1 |
432 |
|
T2 |
300 |
|
T13 |
240 |
| auto[1] |
auto[0] |
auto[1] |
379319 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T13 |
58 |
| auto[1] |
auto[1] |
auto[0] |
2643563 |
1 |
|
|
T1 |
451 |
|
T2 |
206 |
|
T13 |
185 |
| auto[1] |
auto[1] |
auto[1] |
385913 |
1 |
|
|
T1 |
16 |
|
T2 |
12 |
|
T13 |
44 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8205251 |
1 |
|
|
T1 |
958 |
|
T2 |
501 |
|
T11 |
135 |
| auto[1] |
6002492 |
1 |
|
|
T1 |
974 |
|
T2 |
437 |
|
T13 |
505 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13450340 |
1 |
|
|
T1 |
1890 |
|
T2 |
923 |
|
T11 |
135 |
| auto[1] |
757403 |
1 |
|
|
T1 |
42 |
|
T2 |
15 |
|
T13 |
58 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8239139 |
1 |
|
|
T1 |
1125 |
|
T2 |
525 |
|
T11 |
135 |
| auto[1] |
5968604 |
1 |
|
|
T1 |
807 |
|
T2 |
413 |
|
T13 |
346 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2607167 |
1 |
|
|
T1 |
369 |
|
T2 |
248 |
|
T13 |
201 |
| auto[1] |
auto[0] |
auto[1] |
378197 |
1 |
|
|
T1 |
19 |
|
T2 |
10 |
|
T13 |
41 |
| auto[1] |
auto[1] |
auto[0] |
2604034 |
1 |
|
|
T1 |
396 |
|
T2 |
150 |
|
T13 |
87 |
| auto[1] |
auto[1] |
auto[1] |
379206 |
1 |
|
|
T1 |
23 |
|
T2 |
5 |
|
T13 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8188392 |
1 |
|
|
T1 |
973 |
|
T2 |
415 |
|
T11 |
135 |
| auto[1] |
6019351 |
1 |
|
|
T1 |
959 |
|
T2 |
523 |
|
T13 |
406 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13440105 |
1 |
|
|
T1 |
1895 |
|
T2 |
915 |
|
T11 |
135 |
| auto[1] |
767638 |
1 |
|
|
T1 |
37 |
|
T2 |
23 |
|
T13 |
78 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8180351 |
1 |
|
|
T1 |
980 |
|
T2 |
463 |
|
T11 |
135 |
| auto[1] |
6027392 |
1 |
|
|
T1 |
952 |
|
T2 |
475 |
|
T13 |
403 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2627810 |
1 |
|
|
T1 |
466 |
|
T2 |
209 |
|
T13 |
315 |
| auto[1] |
auto[0] |
auto[1] |
383212 |
1 |
|
|
T1 |
15 |
|
T2 |
12 |
|
T13 |
76 |
| auto[1] |
auto[1] |
auto[0] |
2631944 |
1 |
|
|
T1 |
449 |
|
T2 |
243 |
|
T13 |
10 |
| auto[1] |
auto[1] |
auto[1] |
384426 |
1 |
|
|
T1 |
22 |
|
T2 |
11 |
|
T13 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8214015 |
1 |
|
|
T1 |
925 |
|
T2 |
626 |
|
T11 |
135 |
| auto[1] |
5993728 |
1 |
|
|
T1 |
1007 |
|
T2 |
312 |
|
T13 |
404 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13441650 |
1 |
|
|
T1 |
1910 |
|
T2 |
923 |
|
T11 |
135 |
| auto[1] |
766093 |
1 |
|
|
T1 |
22 |
|
T2 |
15 |
|
T13 |
96 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8182119 |
1 |
|
|
T1 |
1176 |
|
T2 |
515 |
|
T11 |
135 |
| auto[1] |
6025624 |
1 |
|
|
T1 |
756 |
|
T2 |
423 |
|
T13 |
490 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2631584 |
1 |
|
|
T1 |
371 |
|
T2 |
298 |
|
T13 |
233 |
| auto[1] |
auto[0] |
auto[1] |
382702 |
1 |
|
|
T1 |
11 |
|
T2 |
10 |
|
T13 |
58 |
| auto[1] |
auto[1] |
auto[0] |
2627947 |
1 |
|
|
T1 |
363 |
|
T2 |
110 |
|
T13 |
161 |
| auto[1] |
auto[1] |
auto[1] |
383391 |
1 |
|
|
T1 |
11 |
|
T2 |
5 |
|
T13 |
38 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8207757 |
1 |
|
|
T1 |
1026 |
|
T2 |
485 |
|
T11 |
135 |
| auto[1] |
5999986 |
1 |
|
|
T1 |
906 |
|
T2 |
453 |
|
T13 |
435 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13448811 |
1 |
|
|
T1 |
1896 |
|
T2 |
924 |
|
T11 |
135 |
| auto[1] |
758932 |
1 |
|
|
T1 |
36 |
|
T2 |
14 |
|
T13 |
134 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8228320 |
1 |
|
|
T1 |
981 |
|
T2 |
482 |
|
T11 |
135 |
| auto[1] |
5979423 |
1 |
|
|
T1 |
951 |
|
T2 |
456 |
|
T13 |
622 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2608544 |
1 |
|
|
T1 |
511 |
|
T2 |
193 |
|
T13 |
281 |
| auto[1] |
auto[0] |
auto[1] |
378372 |
1 |
|
|
T1 |
19 |
|
T2 |
7 |
|
T13 |
69 |
| auto[1] |
auto[1] |
auto[0] |
2611947 |
1 |
|
|
T1 |
404 |
|
T2 |
249 |
|
T13 |
207 |
| auto[1] |
auto[1] |
auto[1] |
380560 |
1 |
|
|
T1 |
17 |
|
T2 |
7 |
|
T13 |
65 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8205060 |
1 |
|
|
T1 |
1118 |
|
T2 |
439 |
|
T11 |
135 |
| auto[1] |
6002683 |
1 |
|
|
T1 |
814 |
|
T2 |
499 |
|
T13 |
567 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13448376 |
1 |
|
|
T1 |
1900 |
|
T2 |
923 |
|
T11 |
135 |
| auto[1] |
759367 |
1 |
|
|
T1 |
32 |
|
T2 |
15 |
|
T13 |
117 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8223425 |
1 |
|
|
T1 |
918 |
|
T2 |
436 |
|
T11 |
135 |
| auto[1] |
5984318 |
1 |
|
|
T1 |
1014 |
|
T2 |
502 |
|
T13 |
646 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2615957 |
1 |
|
|
T1 |
615 |
|
T2 |
214 |
|
T13 |
227 |
| auto[1] |
auto[0] |
auto[1] |
380596 |
1 |
|
|
T1 |
16 |
|
T2 |
10 |
|
T13 |
49 |
| auto[1] |
auto[1] |
auto[0] |
2608994 |
1 |
|
|
T1 |
367 |
|
T2 |
273 |
|
T13 |
302 |
| auto[1] |
auto[1] |
auto[1] |
378771 |
1 |
|
|
T1 |
16 |
|
T2 |
5 |
|
T13 |
68 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8217357 |
1 |
|
|
T1 |
989 |
|
T2 |
562 |
|
T11 |
135 |
| auto[1] |
5990386 |
1 |
|
|
T1 |
943 |
|
T2 |
376 |
|
T13 |
451 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13451394 |
1 |
|
|
T1 |
1877 |
|
T2 |
921 |
|
T11 |
135 |
| auto[1] |
756349 |
1 |
|
|
T1 |
55 |
|
T2 |
17 |
|
T13 |
64 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8241816 |
1 |
|
|
T1 |
791 |
|
T2 |
519 |
|
T11 |
135 |
| auto[1] |
5965927 |
1 |
|
|
T1 |
1141 |
|
T2 |
419 |
|
T13 |
352 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2607279 |
1 |
|
|
T1 |
510 |
|
T2 |
217 |
|
T13 |
158 |
| auto[1] |
auto[0] |
auto[1] |
378343 |
1 |
|
|
T1 |
27 |
|
T2 |
11 |
|
T13 |
35 |
| auto[1] |
auto[1] |
auto[0] |
2602299 |
1 |
|
|
T1 |
576 |
|
T2 |
185 |
|
T13 |
130 |
| auto[1] |
auto[1] |
auto[1] |
378006 |
1 |
|
|
T1 |
28 |
|
T2 |
6 |
|
T13 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8239539 |
1 |
|
|
T1 |
1005 |
|
T2 |
467 |
|
T11 |
135 |
| auto[1] |
5968204 |
1 |
|
|
T1 |
927 |
|
T2 |
471 |
|
T13 |
368 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13448682 |
1 |
|
|
T1 |
1900 |
|
T2 |
921 |
|
T11 |
135 |
| auto[1] |
759061 |
1 |
|
|
T1 |
32 |
|
T2 |
17 |
|
T13 |
124 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8238898 |
1 |
|
|
T1 |
1114 |
|
T2 |
338 |
|
T11 |
135 |
| auto[1] |
5968845 |
1 |
|
|
T1 |
818 |
|
T2 |
600 |
|
T13 |
638 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2610700 |
1 |
|
|
T1 |
389 |
|
T2 |
269 |
|
T13 |
369 |
| auto[1] |
auto[0] |
auto[1] |
379650 |
1 |
|
|
T1 |
18 |
|
T2 |
10 |
|
T13 |
92 |
| auto[1] |
auto[1] |
auto[0] |
2599084 |
1 |
|
|
T1 |
397 |
|
T2 |
314 |
|
T13 |
145 |
| auto[1] |
auto[1] |
auto[1] |
379411 |
1 |
|
|
T1 |
14 |
|
T2 |
7 |
|
T13 |
32 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8215368 |
1 |
|
|
T1 |
959 |
|
T2 |
583 |
|
T11 |
135 |
| auto[1] |
5992375 |
1 |
|
|
T1 |
973 |
|
T2 |
355 |
|
T13 |
491 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13449081 |
1 |
|
|
T1 |
1894 |
|
T2 |
926 |
|
T11 |
135 |
| auto[1] |
758662 |
1 |
|
|
T1 |
38 |
|
T2 |
12 |
|
T13 |
94 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8228627 |
1 |
|
|
T1 |
1015 |
|
T2 |
416 |
|
T11 |
135 |
| auto[1] |
5979116 |
1 |
|
|
T1 |
917 |
|
T2 |
522 |
|
T13 |
482 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2602620 |
1 |
|
|
T1 |
438 |
|
T2 |
352 |
|
T13 |
176 |
| auto[1] |
auto[0] |
auto[1] |
378323 |
1 |
|
|
T1 |
21 |
|
T2 |
8 |
|
T13 |
41 |
| auto[1] |
auto[1] |
auto[0] |
2617834 |
1 |
|
|
T1 |
441 |
|
T2 |
158 |
|
T13 |
212 |
| auto[1] |
auto[1] |
auto[1] |
380339 |
1 |
|
|
T1 |
17 |
|
T2 |
4 |
|
T13 |
53 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8205273 |
1 |
|
|
T1 |
916 |
|
T2 |
481 |
|
T11 |
135 |
| auto[1] |
6002470 |
1 |
|
|
T1 |
1016 |
|
T2 |
457 |
|
T13 |
527 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13446699 |
1 |
|
|
T1 |
1894 |
|
T2 |
927 |
|
T11 |
135 |
| auto[1] |
761044 |
1 |
|
|
T1 |
38 |
|
T2 |
11 |
|
T13 |
103 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8212329 |
1 |
|
|
T1 |
1112 |
|
T2 |
407 |
|
T11 |
135 |
| auto[1] |
5995414 |
1 |
|
|
T1 |
820 |
|
T2 |
531 |
|
T13 |
570 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2629484 |
1 |
|
|
T1 |
367 |
|
T2 |
284 |
|
T13 |
233 |
| auto[1] |
auto[0] |
auto[1] |
383219 |
1 |
|
|
T1 |
20 |
|
T2 |
10 |
|
T13 |
57 |
| auto[1] |
auto[1] |
auto[0] |
2604886 |
1 |
|
|
T1 |
415 |
|
T2 |
236 |
|
T13 |
234 |
| auto[1] |
auto[1] |
auto[1] |
377825 |
1 |
|
|
T1 |
18 |
|
T2 |
1 |
|
T13 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8244776 |
1 |
|
|
T1 |
912 |
|
T2 |
497 |
|
T11 |
135 |
| auto[1] |
5962967 |
1 |
|
|
T1 |
1020 |
|
T2 |
441 |
|
T13 |
432 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13444900 |
1 |
|
|
T1 |
1888 |
|
T2 |
922 |
|
T11 |
135 |
| auto[1] |
762843 |
1 |
|
|
T1 |
44 |
|
T2 |
16 |
|
T13 |
92 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8202835 |
1 |
|
|
T1 |
817 |
|
T2 |
515 |
|
T11 |
135 |
| auto[1] |
6004908 |
1 |
|
|
T1 |
1115 |
|
T2 |
423 |
|
T13 |
473 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2648676 |
1 |
|
|
T1 |
503 |
|
T2 |
246 |
|
T13 |
246 |
| auto[1] |
auto[0] |
auto[1] |
385873 |
1 |
|
|
T1 |
19 |
|
T2 |
11 |
|
T13 |
59 |
| auto[1] |
auto[1] |
auto[0] |
2593389 |
1 |
|
|
T1 |
568 |
|
T2 |
161 |
|
T13 |
135 |
| auto[1] |
auto[1] |
auto[1] |
376970 |
1 |
|
|
T1 |
25 |
|
T2 |
5 |
|
T13 |
33 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8255106 |
1 |
|
|
T1 |
1226 |
|
T2 |
440 |
|
T11 |
135 |
| auto[1] |
5952637 |
1 |
|
|
T1 |
706 |
|
T2 |
498 |
|
T13 |
695 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13449438 |
1 |
|
|
T1 |
1893 |
|
T2 |
925 |
|
T11 |
135 |
| auto[1] |
758305 |
1 |
|
|
T1 |
39 |
|
T2 |
13 |
|
T13 |
109 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8232181 |
1 |
|
|
T1 |
930 |
|
T2 |
482 |
|
T11 |
135 |
| auto[1] |
5975562 |
1 |
|
|
T1 |
1002 |
|
T2 |
456 |
|
T13 |
574 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2624436 |
1 |
|
|
T1 |
625 |
|
T2 |
186 |
|
T13 |
176 |
| auto[1] |
auto[0] |
auto[1] |
381695 |
1 |
|
|
T1 |
32 |
|
T2 |
5 |
|
T13 |
46 |
| auto[1] |
auto[1] |
auto[0] |
2592821 |
1 |
|
|
T1 |
338 |
|
T2 |
257 |
|
T13 |
289 |
| auto[1] |
auto[1] |
auto[1] |
376610 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T13 |
63 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8234075 |
1 |
|
|
T1 |
799 |
|
T2 |
422 |
|
T11 |
135 |
| auto[1] |
5973668 |
1 |
|
|
T1 |
1133 |
|
T2 |
516 |
|
T13 |
421 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13442018 |
1 |
|
|
T1 |
1889 |
|
T2 |
918 |
|
T11 |
135 |
| auto[1] |
765725 |
1 |
|
|
T1 |
43 |
|
T2 |
20 |
|
T13 |
137 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8191793 |
1 |
|
|
T1 |
911 |
|
T2 |
450 |
|
T11 |
135 |
| auto[1] |
6015950 |
1 |
|
|
T1 |
1021 |
|
T2 |
488 |
|
T13 |
651 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2626903 |
1 |
|
|
T1 |
387 |
|
T2 |
184 |
|
T13 |
298 |
| auto[1] |
auto[0] |
auto[1] |
383159 |
1 |
|
|
T1 |
15 |
|
T2 |
9 |
|
T13 |
85 |
| auto[1] |
auto[1] |
auto[0] |
2623322 |
1 |
|
|
T1 |
591 |
|
T2 |
284 |
|
T13 |
216 |
| auto[1] |
auto[1] |
auto[1] |
382566 |
1 |
|
|
T1 |
28 |
|
T2 |
11 |
|
T13 |
52 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |