Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8232471 |
1 |
|
|
T1 |
832 |
|
T2 |
661 |
|
T11 |
135 |
| auto[1] |
5975272 |
1 |
|
|
T1 |
1100 |
|
T2 |
277 |
|
T13 |
418 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13448069 |
1 |
|
|
T1 |
1895 |
|
T2 |
921 |
|
T11 |
135 |
| auto[1] |
759674 |
1 |
|
|
T1 |
37 |
|
T2 |
17 |
|
T13 |
104 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8227792 |
1 |
|
|
T1 |
1033 |
|
T2 |
567 |
|
T11 |
135 |
| auto[1] |
5979951 |
1 |
|
|
T1 |
899 |
|
T2 |
371 |
|
T13 |
547 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2636629 |
1 |
|
|
T1 |
353 |
|
T2 |
236 |
|
T13 |
276 |
| auto[1] |
auto[0] |
auto[1] |
385132 |
1 |
|
|
T1 |
12 |
|
T2 |
9 |
|
T13 |
63 |
| auto[1] |
auto[1] |
auto[0] |
2583648 |
1 |
|
|
T1 |
509 |
|
T2 |
118 |
|
T13 |
167 |
| auto[1] |
auto[1] |
auto[1] |
374542 |
1 |
|
|
T1 |
25 |
|
T2 |
8 |
|
T13 |
41 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |