Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8211039 |
1 |
|
|
T1 |
1106 |
|
T2 |
616 |
|
T11 |
135 |
| auto[1] |
5996704 |
1 |
|
|
T1 |
826 |
|
T2 |
322 |
|
T13 |
420 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13442742 |
1 |
|
|
T1 |
1891 |
|
T2 |
925 |
|
T11 |
135 |
| auto[1] |
765001 |
1 |
|
|
T1 |
41 |
|
T2 |
13 |
|
T13 |
97 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8193417 |
1 |
|
|
T1 |
945 |
|
T2 |
519 |
|
T11 |
135 |
| auto[1] |
6014326 |
1 |
|
|
T1 |
987 |
|
T2 |
419 |
|
T13 |
541 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2610716 |
1 |
|
|
T1 |
493 |
|
T2 |
234 |
|
T13 |
323 |
| auto[1] |
auto[0] |
auto[1] |
379501 |
1 |
|
|
T1 |
27 |
|
T2 |
7 |
|
T13 |
74 |
| auto[1] |
auto[1] |
auto[0] |
2638609 |
1 |
|
|
T1 |
453 |
|
T2 |
172 |
|
T13 |
121 |
| auto[1] |
auto[1] |
auto[1] |
385500 |
1 |
|
|
T1 |
14 |
|
T2 |
6 |
|
T13 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |