Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8218580 |
1 |
|
|
T1 |
974 |
|
T2 |
514 |
|
T11 |
135 |
| auto[1] |
5989163 |
1 |
|
|
T1 |
958 |
|
T2 |
424 |
|
T13 |
676 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13450970 |
1 |
|
|
T1 |
1893 |
|
T2 |
921 |
|
T11 |
135 |
| auto[1] |
756773 |
1 |
|
|
T1 |
39 |
|
T2 |
17 |
|
T13 |
109 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8235336 |
1 |
|
|
T1 |
1018 |
|
T2 |
595 |
|
T11 |
135 |
| auto[1] |
5972407 |
1 |
|
|
T1 |
914 |
|
T2 |
343 |
|
T13 |
559 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2608474 |
1 |
|
|
T1 |
438 |
|
T2 |
187 |
|
T13 |
224 |
| auto[1] |
auto[0] |
auto[1] |
379731 |
1 |
|
|
T1 |
21 |
|
T2 |
9 |
|
T13 |
63 |
| auto[1] |
auto[1] |
auto[0] |
2607160 |
1 |
|
|
T1 |
437 |
|
T2 |
139 |
|
T13 |
226 |
| auto[1] |
auto[1] |
auto[1] |
377042 |
1 |
|
|
T1 |
18 |
|
T2 |
8 |
|
T13 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |