Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8228032 |
1 |
|
|
T1 |
908 |
|
T2 |
572 |
|
T11 |
135 |
| auto[1] |
5979711 |
1 |
|
|
T1 |
1024 |
|
T2 |
366 |
|
T13 |
701 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13453059 |
1 |
|
|
T1 |
1898 |
|
T2 |
919 |
|
T11 |
135 |
| auto[1] |
754684 |
1 |
|
|
T1 |
34 |
|
T2 |
19 |
|
T13 |
144 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8255658 |
1 |
|
|
T1 |
1105 |
|
T2 |
474 |
|
T11 |
135 |
| auto[1] |
5952085 |
1 |
|
|
T1 |
827 |
|
T2 |
464 |
|
T13 |
748 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2608090 |
1 |
|
|
T1 |
349 |
|
T2 |
265 |
|
T13 |
296 |
| auto[1] |
auto[0] |
auto[1] |
378970 |
1 |
|
|
T1 |
10 |
|
T2 |
11 |
|
T13 |
66 |
| auto[1] |
auto[1] |
auto[0] |
2589311 |
1 |
|
|
T1 |
444 |
|
T2 |
180 |
|
T13 |
308 |
| auto[1] |
auto[1] |
auto[1] |
375714 |
1 |
|
|
T1 |
24 |
|
T2 |
8 |
|
T13 |
78 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |