Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8230856 |
1 |
|
|
T1 |
1004 |
|
T2 |
413 |
|
T11 |
135 |
| auto[1] |
5976887 |
1 |
|
|
T1 |
928 |
|
T2 |
525 |
|
T13 |
483 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13444027 |
1 |
|
|
T1 |
1891 |
|
T2 |
925 |
|
T11 |
135 |
| auto[1] |
763716 |
1 |
|
|
T1 |
41 |
|
T2 |
13 |
|
T13 |
146 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8202996 |
1 |
|
|
T1 |
1083 |
|
T2 |
491 |
|
T11 |
135 |
| auto[1] |
6004747 |
1 |
|
|
T1 |
849 |
|
T2 |
447 |
|
T13 |
692 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2634052 |
1 |
|
|
T1 |
432 |
|
T2 |
160 |
|
T13 |
320 |
| auto[1] |
auto[0] |
auto[1] |
384028 |
1 |
|
|
T1 |
19 |
|
T2 |
6 |
|
T13 |
85 |
| auto[1] |
auto[1] |
auto[0] |
2606979 |
1 |
|
|
T1 |
376 |
|
T2 |
274 |
|
T13 |
226 |
| auto[1] |
auto[1] |
auto[1] |
379688 |
1 |
|
|
T1 |
22 |
|
T2 |
7 |
|
T13 |
61 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |