Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8203714 |
1 |
|
|
T1 |
744 |
|
T2 |
426 |
|
T11 |
135 |
| auto[1] |
6004029 |
1 |
|
|
T1 |
1188 |
|
T2 |
512 |
|
T13 |
537 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11747504 |
1 |
|
|
T1 |
997 |
|
T2 |
609 |
|
T11 |
135 |
| auto[1] |
2460239 |
1 |
|
|
T1 |
935 |
|
T2 |
329 |
|
T13 |
316 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8212008 |
1 |
|
|
T1 |
762 |
|
T2 |
462 |
|
T11 |
135 |
| auto[1] |
5995735 |
1 |
|
|
T1 |
1170 |
|
T2 |
476 |
|
T13 |
679 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1763991 |
1 |
|
|
T1 |
114 |
|
T2 |
60 |
|
T13 |
213 |
| auto[1] |
auto[0] |
auto[1] |
1230772 |
1 |
|
|
T1 |
332 |
|
T2 |
179 |
|
T13 |
164 |
| auto[1] |
auto[1] |
auto[0] |
1771505 |
1 |
|
|
T1 |
121 |
|
T2 |
87 |
|
T13 |
150 |
| auto[1] |
auto[1] |
auto[1] |
1229467 |
1 |
|
|
T1 |
603 |
|
T2 |
150 |
|
T13 |
152 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |