Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8216384 |
1 |
|
|
T1 |
876 |
|
T2 |
461 |
|
T11 |
135 |
| auto[1] |
5991359 |
1 |
|
|
T1 |
1056 |
|
T2 |
477 |
|
T13 |
598 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11750382 |
1 |
|
|
T1 |
1037 |
|
T2 |
591 |
|
T11 |
135 |
| auto[1] |
2457361 |
1 |
|
|
T1 |
895 |
|
T2 |
347 |
|
T13 |
336 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8198627 |
1 |
|
|
T1 |
746 |
|
T2 |
485 |
|
T11 |
135 |
| auto[1] |
6009116 |
1 |
|
|
T1 |
1186 |
|
T2 |
453 |
|
T13 |
655 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1775618 |
1 |
|
|
T1 |
115 |
|
T2 |
9 |
|
T13 |
153 |
| auto[1] |
auto[0] |
auto[1] |
1230099 |
1 |
|
|
T1 |
364 |
|
T2 |
178 |
|
T13 |
191 |
| auto[1] |
auto[1] |
auto[0] |
1776137 |
1 |
|
|
T1 |
176 |
|
T2 |
97 |
|
T13 |
166 |
| auto[1] |
auto[1] |
auto[1] |
1227262 |
1 |
|
|
T1 |
531 |
|
T2 |
169 |
|
T13 |
145 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |