Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8222247 |
1 |
|
|
T1 |
1060 |
|
T2 |
379 |
|
T11 |
135 |
| auto[1] |
5985496 |
1 |
|
|
T1 |
872 |
|
T2 |
559 |
|
T13 |
624 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11747664 |
1 |
|
|
T1 |
1135 |
|
T2 |
605 |
|
T11 |
135 |
| auto[1] |
2460079 |
1 |
|
|
T1 |
797 |
|
T2 |
333 |
|
T13 |
302 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8207024 |
1 |
|
|
T1 |
906 |
|
T2 |
506 |
|
T11 |
135 |
| auto[1] |
6000719 |
1 |
|
|
T1 |
1026 |
|
T2 |
432 |
|
T13 |
561 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1777066 |
1 |
|
|
T1 |
135 |
|
T2 |
42 |
|
T13 |
112 |
| auto[1] |
auto[0] |
auto[1] |
1238289 |
1 |
|
|
T1 |
453 |
|
T2 |
138 |
|
T13 |
160 |
| auto[1] |
auto[1] |
auto[0] |
1763574 |
1 |
|
|
T1 |
94 |
|
T2 |
57 |
|
T13 |
147 |
| auto[1] |
auto[1] |
auto[1] |
1221790 |
1 |
|
|
T1 |
344 |
|
T2 |
195 |
|
T13 |
142 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |