Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8212117 |
1 |
|
|
T1 |
855 |
|
T2 |
480 |
|
T11 |
135 |
| auto[1] |
5995626 |
1 |
|
|
T1 |
1077 |
|
T2 |
458 |
|
T13 |
563 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11745322 |
1 |
|
|
T1 |
1354 |
|
T2 |
568 |
|
T11 |
135 |
| auto[1] |
2462421 |
1 |
|
|
T1 |
578 |
|
T2 |
370 |
|
T13 |
230 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8203074 |
1 |
|
|
T1 |
1090 |
|
T2 |
489 |
|
T11 |
135 |
| auto[1] |
6004669 |
1 |
|
|
T1 |
842 |
|
T2 |
449 |
|
T13 |
473 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1779638 |
1 |
|
|
T1 |
127 |
|
T2 |
44 |
|
T13 |
113 |
| auto[1] |
auto[0] |
auto[1] |
1233934 |
1 |
|
|
T1 |
336 |
|
T2 |
194 |
|
T13 |
97 |
| auto[1] |
auto[1] |
auto[0] |
1762610 |
1 |
|
|
T1 |
137 |
|
T2 |
35 |
|
T13 |
130 |
| auto[1] |
auto[1] |
auto[1] |
1228487 |
1 |
|
|
T1 |
242 |
|
T2 |
176 |
|
T13 |
133 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |