Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8220881 |
1 |
|
|
T1 |
1050 |
|
T2 |
537 |
|
T11 |
135 |
| auto[1] |
5986862 |
1 |
|
|
T1 |
882 |
|
T2 |
401 |
|
T13 |
503 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13446337 |
1 |
|
|
T1 |
1903 |
|
T2 |
915 |
|
T11 |
135 |
| auto[1] |
761406 |
1 |
|
|
T1 |
29 |
|
T2 |
23 |
|
T13 |
135 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8210421 |
1 |
|
|
T1 |
1014 |
|
T2 |
418 |
|
T11 |
135 |
| auto[1] |
5997322 |
1 |
|
|
T1 |
918 |
|
T2 |
520 |
|
T13 |
688 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
2624657 |
1 |
|
|
T1 |
578 |
|
T2 |
344 |
|
T13 |
364 |
| auto[1] |
auto[0] |
auto[1] |
381959 |
1 |
|
|
T1 |
20 |
|
T2 |
13 |
|
T13 |
89 |
| auto[1] |
auto[1] |
auto[0] |
2611259 |
1 |
|
|
T1 |
311 |
|
T2 |
153 |
|
T13 |
189 |
| auto[1] |
auto[1] |
auto[1] |
379447 |
1 |
|
|
T1 |
9 |
|
T2 |
10 |
|
T13 |
46 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |