Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8238411 |
1 |
|
|
T1 |
765 |
|
T2 |
476 |
|
T11 |
135 |
| auto[1] |
5969332 |
1 |
|
|
T1 |
1167 |
|
T2 |
462 |
|
T13 |
551 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11758188 |
1 |
|
|
T1 |
1112 |
|
T2 |
574 |
|
T11 |
135 |
| auto[1] |
2449555 |
1 |
|
|
T1 |
820 |
|
T2 |
364 |
|
T13 |
305 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8228564 |
1 |
|
|
T1 |
887 |
|
T2 |
460 |
|
T11 |
135 |
| auto[1] |
5979179 |
1 |
|
|
T1 |
1045 |
|
T2 |
478 |
|
T13 |
632 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1770431 |
1 |
|
|
T1 |
73 |
|
T2 |
53 |
|
T13 |
159 |
| auto[1] |
auto[0] |
auto[1] |
1224825 |
1 |
|
|
T1 |
317 |
|
T2 |
160 |
|
T13 |
153 |
| auto[1] |
auto[1] |
auto[0] |
1759193 |
1 |
|
|
T1 |
152 |
|
T2 |
61 |
|
T13 |
168 |
| auto[1] |
auto[1] |
auto[1] |
1224730 |
1 |
|
|
T1 |
503 |
|
T2 |
204 |
|
T13 |
152 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |