Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8179799 |
1 |
|
|
T1 |
907 |
|
T2 |
490 |
|
T11 |
135 |
| auto[1] |
6027944 |
1 |
|
|
T1 |
1025 |
|
T2 |
448 |
|
T13 |
510 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11753667 |
1 |
|
|
T1 |
1206 |
|
T2 |
671 |
|
T11 |
135 |
| auto[1] |
2454076 |
1 |
|
|
T1 |
726 |
|
T2 |
267 |
|
T13 |
191 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8217733 |
1 |
|
|
T1 |
979 |
|
T2 |
615 |
|
T11 |
135 |
| auto[1] |
5990010 |
1 |
|
|
T1 |
953 |
|
T2 |
323 |
|
T13 |
377 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1760024 |
1 |
|
|
T1 |
121 |
|
T2 |
36 |
|
T13 |
111 |
| auto[1] |
auto[0] |
auto[1] |
1220527 |
1 |
|
|
T1 |
357 |
|
T2 |
151 |
|
T13 |
111 |
| auto[1] |
auto[1] |
auto[0] |
1775910 |
1 |
|
|
T1 |
106 |
|
T2 |
20 |
|
T13 |
75 |
| auto[1] |
auto[1] |
auto[1] |
1233549 |
1 |
|
|
T1 |
369 |
|
T2 |
116 |
|
T13 |
80 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |